board/freescale/mx6slevk/mx6slevk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  */
   7
   8 #include <net.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-ddr.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/io.h>
  20 #include <linux/sizes.h>
  21 #include <common.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <i2c.h>
  24 #include <mmc.h>
  25 #include <power/pmic.h>
  26 #include <power/pfuze100_pmic.h>
  27 #include "../common/pfuze.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  32         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  33         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  34
  35 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP |                    \
  36         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  37         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  40         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  41         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  42
  43 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  44                         PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
  45                         PAD_CTL_DSE_80ohm | PAD_CTL_HYS |       \
  46                         PAD_CTL_SRE_FAST)
  47
  48 #define ETH_PHY_POWER   IMX_GPIO_NR(4, 21)
  49
  50 int dram_init(void)
  51 {
  52         gd->ram_size = imx_ddr_size();
  53
  54         return 0;
  55 }
  56
  57 static iomux_v3_cfg_t const uart1_pads[] = {
  58         MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  59         MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  60 };
  61
  62 #ifdef CONFIG_SPL_BUILD
  63 static iomux_v3_cfg_t const usdhc1_pads[] = {
  64         /* 8 bit SD */
  65         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67         MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68         MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  69         MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  70         MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  71         MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75
  76         /*CD pin*/
  77         MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  78 };
  79
  80 static iomux_v3_cfg_t const usdhc2_pads[] = {
  81         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87
  88         /*CD pin*/
  89         MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
  90 };
  91
  92 static iomux_v3_cfg_t const usdhc3_pads[] = {
  93         MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99
 100         /*CD pin*/
 101         MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 102 };
 103 #endif
 104
 105 static void setup_iomux_uart(void)
 106 {
 107         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 108 }
 109
 110 int board_mmc_get_env_dev(int devno)
 111 {
 112         return devno;
 113 }
 114
 115 #ifdef CONFIG_DM_PMIC_PFUZE100
 116 int power_init_board(void)
 117 {
 118         struct udevice *dev;
 119         int ret;
 120         u32 dev_id, rev_id, i;
 121         u32 switch_num = 6;
 122         u32 offset = PFUZE100_SW1CMODE;
 123
 124         ret = pmic_get("pfuze100@08", &dev);
 125         if (ret == -ENODEV)
 126                 return 0;
 127
 128         if (ret != 0)
 129                 return ret;
 130
 131         dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
 132         rev_id = pmic_reg_read(dev, PFUZE100_REVID);
 133         printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 134
 135         /* set SW1AB staby volatage 0.975V */
 136         pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
 137
 138         /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 139         pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
 140
 141         /* set SW1C staby volatage 0.975V */
 142         pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
 143
 144         /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
 145         pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
 146
 147         /* Init mode to APS_PFM */
 148         pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
 149
 150         for (i = 0; i < switch_num - 1; i++)
 151                 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
 152
 153         return 0;
 154 }
 155 #endif
 156
 157 #ifdef CONFIG_FEC_MXC
 158
 159 static int setup_fec(void)
 160 {
 161         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 162
 163         /* clear gpr1[14], gpr1[18:17] to select anatop clock */
 164         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 165
 166         return enable_fec_anatop_clock(0, ENET_50MHZ);
 167 }
 168 #endif
 169
 170 int board_early_init_f(void)
 171 {
 172         setup_iomux_uart();
 173
 174         return 0;
 175 }
 176
 177 int board_init(void)
 178 {
 179         /* address of boot parameters */
 180         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 181
 182 #ifdef  CONFIG_FEC_MXC
 183         setup_fec();
 184 #endif
 185
 186         return 0;
 187 }
 188
 189 int checkboard(void)
 190 {
 191         puts("Board: MX6SLEVK\n");
 192
 193         return 0;
 194 }
 195
 196 #ifdef CONFIG_SPL_BUILD
 197 #include <spl.h>
 198 #include <linux/libfdt.h>
 199
 200 #define USDHC1_CD_GPIO  IMX_GPIO_NR(4, 7)
 201 #define USDHC2_CD_GPIO  IMX_GPIO_NR(5, 0)
 202 #define USDHC3_CD_GPIO  IMX_GPIO_NR(3, 22)
 203
 204 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 205         {USDHC1_BASE_ADDR},
 206         {USDHC2_BASE_ADDR, 0, 4},
 207         {USDHC3_BASE_ADDR, 0, 4},
 208 };
 209
 210 int board_mmc_getcd(struct mmc *mmc)
 211 {
 212         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 213         int ret = 0;
 214
 215         switch (cfg->esdhc_base) {
 216         case USDHC1_BASE_ADDR:
 217                 gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
 218                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 219                 break;
 220         case USDHC2_BASE_ADDR:
 221                 gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
 222                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 223                 break;
 224         case USDHC3_BASE_ADDR:
 225                 gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
 226                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 227                 break;
 228         }
 229
 230         return ret;
 231 }
 232
 233 int board_mmc_init(bd_t *bis)
 234 {
 235         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 236         u32 val;
 237         u32 port;
 238
 239         val = readl(&src_regs->sbmr1);
 240
 241         /* Boot from USDHC */
 242         port = (val >> 11) & 0x3;
 243         switch (port) {
 244         case 0:
 245                 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 246                                                  ARRAY_SIZE(usdhc1_pads));
 247                 gpio_direction_input(USDHC1_CD_GPIO);
 248                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 249                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 250                 break;
 251         case 1:
 252                 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
 253                                                  ARRAY_SIZE(usdhc2_pads));
 254                 gpio_direction_input(USDHC2_CD_GPIO);
 255                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 256                 usdhc_cfg[0].max_bus_width = 4;
 257                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 258                 break;
 259         case 2:
 260                 imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
 261                                                  ARRAY_SIZE(usdhc3_pads));
 262                 gpio_direction_input(USDHC3_CD_GPIO);
 263                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 264                 usdhc_cfg[0].max_bus_width = 4;
 265                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 266                 break;
 267         }
 268
 269         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 270         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 271 }
 272
 273 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
 274         .dram_sdqs0 = 0x00003030,
 275         .dram_sdqs1 = 0x00003030,
 276         .dram_sdqs2 = 0x00003030,
 277         .dram_sdqs3 = 0x00003030,
 278         .dram_dqm0 = 0x00000030,
 279         .dram_dqm1 = 0x00000030,
 280         .dram_dqm2 = 0x00000030,
 281         .dram_dqm3 = 0x00000030,
 282         .dram_cas  = 0x00000030,
 283         .dram_ras  = 0x00000030,
 284         .dram_sdclk_0 = 0x00000028,
 285         .dram_reset = 0x00000030,
 286         .dram_sdba2 = 0x00000000,
 287         .dram_odt0 = 0x00000008,
 288         .dram_odt1 = 0x00000008,
 289 };
 290
 291 const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
 292         .grp_b0ds = 0x00000030,
 293         .grp_b1ds = 0x00000030,
 294         .grp_b2ds = 0x00000030,
 295         .grp_b3ds = 0x00000030,
 296         .grp_addds = 0x00000030,
 297         .grp_ctlds = 0x00000030,
 298         .grp_ddrmode_ctl = 0x00020000,
 299         .grp_ddrpke = 0x00000000,
 300         .grp_ddrmode = 0x00020000,
 301         .grp_ddr_type = 0x00080000,
 302 };
 303
 304 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 305         .p0_mpdgctrl0 =  0x20000000,
 306         .p0_mpdgctrl1 =  0x00000000,
 307         .p0_mprddlctl =  0x4241444a,
 308         .p0_mpwrdlctl =  0x3030312b,
 309         .mpzqlp2ctl = 0x1b4700c7,
 310 };
 311
 312 static struct mx6_lpddr2_cfg mem_ddr = {
 313         .mem_speed = 800,
 314         .density = 4,
 315         .width = 32,
 316         .banks = 8,
 317         .rowaddr = 14,
 318         .coladdr = 10,
 319         .trcd_lp = 2000,
 320         .trppb_lp = 2000,
 321         .trpab_lp = 2250,
 322         .trasmin = 4200,
 323 };
 324
 325 static void ccgr_init(void)
 326 {
 327         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 328
 329         writel(0xFFFFFFFF, &ccm->CCGR0);
 330         writel(0xFFFFFFFF, &ccm->CCGR1);
 331         writel(0xFFFFFFFF, &ccm->CCGR2);
 332         writel(0xFFFFFFFF, &ccm->CCGR3);
 333         writel(0xFFFFFFFF, &ccm->CCGR4);
 334         writel(0xFFFFFFFF, &ccm->CCGR5);
 335         writel(0xFFFFFFFF, &ccm->CCGR6);
 336
 337         writel(0x00260324, &ccm->cbcmr);
 338 }
 339
 340 static void spl_dram_init(void)
 341 {
 342         struct mx6_ddr_sysinfo sysinfo = {
 343                 .dsize = mem_ddr.width / 32,
 344                 .cs_density = 20,
 345                 .ncs = 2,
 346                 .cs1_mirror = 0,
 347                 .walat = 0,
 348                 .ralat = 2,
 349                 .mif3_mode = 3,
 350                 .bi_on = 1,
 351                 .rtt_wr = 0,        /* LPDDR2 does not need rtt_wr rtt_nom */
 352                 .rtt_nom = 0,
 353                 .sde_to_rst = 0,    /* LPDDR2 does not need this field */
 354                 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
 355                 .ddr_type = DDR_TYPE_LPDDR2,
 356                 .refsel = 0,    /* Refresh cycles at 64KHz */
 357                 .refr = 3,      /* 4 refresh commands per refresh cycle */
 358         };
 359         mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 360         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 361 }
 362
 363 void board_init_f(ulong dummy)
 364 {
 365         /* setup AIPS and disable watchdog */
 366         arch_cpu_init();
 367
 368         ccgr_init();
 369
 370         /* iomux and setup of i2c */
 371         board_early_init_f();
 372
 373         /* setup GP timer */
 374         timer_init();
 375
 376         /* UART clocks enabled and gd valid - init serial console */
 377         preloader_console_init();
 378
 379         /* DDR initialization */
 380         spl_dram_init();
 381
 382         /* Clear the BSS. */
 383         memset(__bss_start, 0, __bss_end - __bss_start);
 384
 385         /* load/boot image from boot device */
 386         board_init_r(NULL, 0);
 387 }
 388 #endif