1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
13 #include <asm/processor.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_pci.h>
17 #include <fsl_ddr_sdram.h>
18 #include <asm/fsl_serdes.h>
19 #include <spd_sdram.h>
22 #include <linux/libfdt.h>
23 #include <fdt_support.h>
27 const qe_iop_conf_t qe_iop_conf_tab[] = {
29 {4, 10, 1, 0, 2}, /* TxD0 */
30 {4, 9, 1, 0, 2}, /* TxD1 */
31 {4, 8, 1, 0, 2}, /* TxD2 */
32 {4, 7, 1, 0, 2}, /* TxD3 */
33 {4, 23, 1, 0, 2}, /* TxD4 */
34 {4, 22, 1, 0, 2}, /* TxD5 */
35 {4, 21, 1, 0, 2}, /* TxD6 */
36 {4, 20, 1, 0, 2}, /* TxD7 */
37 {4, 15, 2, 0, 2}, /* RxD0 */
38 {4, 14, 2, 0, 2}, /* RxD1 */
39 {4, 13, 2, 0, 2}, /* RxD2 */
40 {4, 12, 2, 0, 2}, /* RxD3 */
41 {4, 29, 2, 0, 2}, /* RxD4 */
42 {4, 28, 2, 0, 2}, /* RxD5 */
43 {4, 27, 2, 0, 2}, /* RxD6 */
44 {4, 26, 2, 0, 2}, /* RxD7 */
45 {4, 11, 1, 0, 2}, /* TX_EN */
46 {4, 24, 1, 0, 2}, /* TX_ER */
47 {4, 16, 2, 0, 2}, /* RX_DV */
48 {4, 30, 2, 0, 2}, /* RX_ER */
49 {4, 17, 2, 0, 2}, /* RX_CLK */
50 {4, 19, 1, 0, 2}, /* GTX_CLK */
51 {1, 31, 2, 0, 3}, /* GTX125 */
54 {5, 10, 1, 0, 2}, /* TxD0 */
55 {5, 9, 1, 0, 2}, /* TxD1 */
56 {5, 8, 1, 0, 2}, /* TxD2 */
57 {5, 7, 1, 0, 2}, /* TxD3 */
58 {5, 23, 1, 0, 2}, /* TxD4 */
59 {5, 22, 1, 0, 2}, /* TxD5 */
60 {5, 21, 1, 0, 2}, /* TxD6 */
61 {5, 20, 1, 0, 2}, /* TxD7 */
62 {5, 15, 2, 0, 2}, /* RxD0 */
63 {5, 14, 2, 0, 2}, /* RxD1 */
64 {5, 13, 2, 0, 2}, /* RxD2 */
65 {5, 12, 2, 0, 2}, /* RxD3 */
66 {5, 29, 2, 0, 2}, /* RxD4 */
67 {5, 28, 2, 0, 2}, /* RxD5 */
68 {5, 27, 2, 0, 3}, /* RxD6 */
69 {5, 26, 2, 0, 2}, /* RxD7 */
70 {5, 11, 1, 0, 2}, /* TX_EN */
71 {5, 24, 1, 0, 2}, /* TX_ER */
72 {5, 16, 2, 0, 2}, /* RX_DV */
73 {5, 30, 2, 0, 2}, /* RX_ER */
74 {5, 17, 2, 0, 2}, /* RX_CLK */
75 {5, 19, 1, 0, 2}, /* GTX_CLK */
76 {1, 31, 2, 0, 3}, /* GTX125 */
77 {4, 6, 3, 0, 2}, /* MDIO */
78 {4, 5, 1, 0, 2}, /* MDC */
81 {2, 0, 1, 0, 2}, /* UART_SOUT1 */
82 {2, 1, 1, 0, 2}, /* UART_RTS1 */
83 {2, 2, 2, 0, 2}, /* UART_CTS1 */
84 {2, 3, 2, 0, 2}, /* UART_SIN1 */
86 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
89 void local_bus_init(void);
91 int board_early_init_f (void)
94 * Initialize local bus.
98 enable_8568mds_duart();
99 enable_8568mds_flash_write();
100 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
101 reset_8568mds_uccs();
103 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
104 enable_8568mds_qe_mdio();
107 #ifdef CONFIG_SYS_I2C2_OFFSET
108 /* Enable I2C2_SCL and I2C2_SDA */
109 volatile struct par_io *port_c;
110 port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
111 port_c->cpdir2 |= 0x0f000000;
112 port_c->cppar2 &= ~0x0f000000;
113 port_c->cppar2 |= 0x0a000000;
119 int checkboard (void)
121 printf ("Board: 8568 MDS\n");
127 * Initialize Local Bus
132 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
133 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
138 get_sys_info(&sysinfo);
139 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
141 gur->lbiuiplldcr1 = 0x00078080;
143 gur->lbiuiplldcr0 = 0x7c0f1bf0;
144 } else if (clkdiv == 8) {
145 gur->lbiuiplldcr0 = 0x6c0f1bf0;
146 } else if (clkdiv == 4) {
147 gur->lbiuiplldcr0 = 0x5c0f1bf0;
150 lbc->lcrr |= 0x00030000;
152 asm("sync;isync;msync");
156 * Initialize SDRAM memory on the Local Bus.
158 void lbc_sdram_init(void)
160 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
163 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
164 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
168 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
172 * Setup SDRAM Base and Option Registers
174 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
175 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
178 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
181 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
182 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
186 * MPC8568 uses "new" 15-16 style addressing.
188 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
189 lsdmr_common |= LSDMR_BSMA1516;
192 * Issue PRECHARGE ALL command.
194 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
197 ppcDcbf((unsigned long) sdram_addr);
201 * Issue 8 AUTO REFRESH commands.
203 for (idx = 0; idx < 8; idx++) {
204 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
207 ppcDcbf((unsigned long) sdram_addr);
212 * Issue 8 MODE-set command.
214 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
217 ppcDcbf((unsigned long) sdram_addr);
221 * Issue NORMAL OP command.
223 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
226 ppcDcbf((unsigned long) sdram_addr);
227 udelay(200); /* Overkill. Must wait > 200 bus cycles */
229 #endif /* enable SDRAM init */
232 #if defined(CONFIG_PCI)
233 #ifndef CONFIG_PCI_PNP
234 static struct pci_config_table pci_mpc8568mds_config_table[] = {
236 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
237 pci_cfgfunc_config_device,
240 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
246 static struct pci_controller pci1_hose;
247 #endif /* CONFIG_PCI */
250 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
255 u8 val8, orig_i2c_bus;
257 * Assign PIB PMC2/3 to PCI bus
260 /*switch temporarily to I2C bus #2 */
261 orig_i2c_bus = i2c_get_bus_num();
265 i2c_write(0x23, 0x6, 1, &val8, 1);
266 i2c_write(0x23, 0x7, 1, &val8, 1);
268 i2c_write(0x23, 0x2, 1, &val8, 1);
269 i2c_write(0x23, 0x3, 1, &val8, 1);
272 i2c_write(0x26, 0x6, 1, &val8, 1);
274 i2c_write(0x26, 0x7, 1, &val8, 1);
276 i2c_write(0x26, 0x2, 1, &val8, 1);
278 i2c_write(0x26, 0x3, 1, &val8, 1);
281 i2c_write(0x27, 0x6, 1, &val8, 1);
282 i2c_write(0x27, 0x7, 1, &val8, 1);
284 i2c_write(0x27, 0x2, 1, &val8, 1);
286 i2c_write(0x27, 0x3, 1, &val8, 1);
289 i2c_set_bus_num(orig_i2c_bus);
293 void pci_init_board(void)
295 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
296 int first_free_busno = 0;
298 struct fsl_pci_info pci_info;
299 u32 devdisr, pordevsr, io_sel;
300 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
302 devdisr = in_be32(&gur->devdisr);
303 pordevsr = in_be32(&gur->pordevsr);
304 porpllsr = in_be32(&gur->porpllsr);
305 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
307 debug(" %s: devdisr=%x, io_sel=%x\n", __func__, devdisr, io_sel);
309 pci_speed = 66666000;
311 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
312 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
314 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
315 SET_STD_PCI_INFO(pci_info, 1);
316 set_next_law(pci_info.mem_phys,
317 law_size_bits(pci_info.mem_size), pci_info.law);
318 set_next_law(pci_info.io_phys,
319 law_size_bits(pci_info.io_size), pci_info.law);
321 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
322 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
324 (pci_speed == 33333000) ? "33" :
325 (pci_speed == 66666000) ? "66" : "unknown",
326 pci_clk_sel ? "sync" : "async",
327 pci_agent ? "agent" : "host",
328 pci_arb ? "arbiter" : "external-arbiter",
331 #ifndef CONFIG_PCI_PNP
332 pci1_hose.config_table = pci_mpc8568mds_config_table;
334 first_free_busno = fsl_pci_init_port(&pci_info,
335 &pci1_hose, first_free_busno);
337 printf("PCI: disabled\n");
342 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
345 fsl_pcie_init_board(first_free_busno);
347 #endif /* CONFIG_PCI */
349 #if defined(CONFIG_OF_BOARD_SETUP)
350 int ft_board_setup(void *blob, bd_t *bd)
352 ft_cpu_setup(blob, bd);