1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 #include <asm/processor.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_pci.h>
15 #include <fsl_ddr_sdram.h>
16 #include <asm/fsl_serdes.h>
18 #include <linux/libfdt.h>
19 #include <fdt_support.h>
24 #include "../common/cadmus.h"
25 #include "../common/eeprom.h"
26 #include "../common/via.h"
28 void local_bus_init(void);
32 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
35 /* PCI slot in USER bits CSR[6:7] by convention. */
36 uint pci_slot = get_pci_slot ();
38 uint cpu_board_rev = get_cpu_board_revision ();
40 puts("Board: MPC8548CDS");
41 printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
42 get_board_version(), pci_slot);
43 printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
44 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
45 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
47 * Initialize local bus.
52 * Hack TSEC 3 and 4 IO voltages.
54 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
56 ecm->eedr = 0xffffffff; /* clear ecm errors */
57 ecm->eeer = 0xffffffff; /* enable ecm errors */
62 * Initialize Local Bus
67 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
68 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
73 get_sys_info(&sysinfo);
74 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
76 gur->lbiuiplldcr1 = 0x00078080;
78 gur->lbiuiplldcr0 = 0x7c0f1bf0;
79 } else if (clkdiv == 8) {
80 gur->lbiuiplldcr0 = 0x6c0f1bf0;
81 } else if (clkdiv == 4) {
82 gur->lbiuiplldcr0 = 0x5c0f1bf0;
85 lbc->lcrr |= 0x00030000;
87 asm("sync;isync;msync");
89 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
90 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
94 * Initialize SDRAM memory on the Local Bus.
96 void lbc_sdram_init(void)
98 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
101 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
102 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
106 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
110 * Setup SDRAM Base and Option Registers
112 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
113 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
114 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
117 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
118 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
122 * MPC8548 uses "new" 15-16 style addressing.
124 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
125 lsdmr_common |= LSDMR_BSMA1516;
128 * Issue PRECHARGE ALL command.
130 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
133 ppcDcbf((unsigned long) sdram_addr);
137 * Issue 8 AUTO REFRESH commands.
139 for (idx = 0; idx < 8; idx++) {
140 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
143 ppcDcbf((unsigned long) sdram_addr);
148 * Issue 8 MODE-set command.
150 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
153 ppcDcbf((unsigned long) sdram_addr);
157 * Issue NORMAL OP command.
159 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
162 ppcDcbf((unsigned long) sdram_addr);
163 udelay(200); /* Overkill. Must wait > 200 bus cycles */
165 #endif /* enable SDRAM init */
168 #if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
169 /* For some reason the Tundra PCI bridge shows up on itself as a
170 * different device. Work around that by refusing to configure it.
172 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
174 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
175 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
176 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
177 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
178 mpc85xx_config_via_usbide, {0,0,0}},
179 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
180 mpc85xx_config_via_usb, {0,0,0}},
181 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
182 mpc85xx_config_via_usb2, {0,0,0}},
183 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
184 mpc85xx_config_via_power, {0,0,0}},
185 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
186 mpc85xx_config_via_ac97, {0,0,0}},
190 static struct pci_controller pci1_hose;
191 #endif /* CONFIG_PCI */
193 #if !defined(CONFIG_DM_PCI)
194 void pci_init_board(void)
196 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
197 struct fsl_pci_info pci_info;
198 u32 devdisr, pordevsr, io_sel;
199 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
200 int first_free_busno = 0;
203 devdisr = in_be32(&gur->devdisr);
204 pordevsr = in_be32(&gur->pordevsr);
205 porpllsr = in_be32(&gur->porpllsr);
206 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
208 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
211 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
212 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
213 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
214 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
216 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
217 SET_STD_PCI_INFO(pci_info, 1);
218 set_next_law(pci_info.mem_phys,
219 law_size_bits(pci_info.mem_size), pci_info.law);
220 set_next_law(pci_info.io_phys,
221 law_size_bits(pci_info.io_size), pci_info.law);
223 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
224 printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
226 strmhz(buf, pci_speed),
227 pci_clk_sel ? "sync" : "async",
228 pci_agent ? "agent" : "host",
229 pci_arb ? "arbiter" : "external-arbiter",
232 pci1_hose.config_table = pci_mpc85xxcds_config_table;
233 first_free_busno = fsl_pci_init_port(&pci_info,
234 &pci1_hose, first_free_busno);
236 #ifdef CONFIG_PCIX_CHECK
237 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
239 if (CONFIG_SYS_CLK_FREQ < 66000000)
240 printf("PCI-X will only work at 66 MHz\n");
242 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
243 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
244 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
248 printf("PCI1: disabled\n");
253 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
258 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
259 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
261 printf("PCI2: 32 bit, 66 MHz, %s\n",
262 pci2_clk_sel ? "sync" : "async");
264 printf("PCI2: disabled\n");
268 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
269 #endif /* CONFIG_PCI2 */
271 fsl_pcie_init_board(first_free_busno);
275 void configure_rgmii(void)
279 /* Change the resistors for the PHY */
280 /* This is needed to get the RGMII working for the 1.3+
282 if (get_board_version() == 0x13) {
283 miiphy_write(DEFAULT_MII_NAME,
284 TSEC1_PHY_ADDR, 29, 18);
286 miiphy_read(DEFAULT_MII_NAME,
287 TSEC1_PHY_ADDR, 30, &temp);
289 temp = (temp & 0xf03f);
290 temp |= 2 << 9; /* 36 ohm */
291 temp |= 2 << 6; /* 39 ohm */
293 miiphy_write(DEFAULT_MII_NAME,
294 TSEC1_PHY_ADDR, 30, temp);
296 miiphy_write(DEFAULT_MII_NAME,
297 TSEC1_PHY_ADDR, 29, 3);
299 miiphy_write(DEFAULT_MII_NAME,
300 TSEC1_PHY_ADDR, 30, 0x8000);
306 int board_eth_init(bd_t *bis)
308 #ifdef CONFIG_TSEC_ENET
309 struct fsl_pq_mdio_info mdio_info;
310 struct tsec_info_struct tsec_info[4];
314 SET_STD_TSEC_INFO(tsec_info[num], 1);
318 SET_STD_TSEC_INFO(tsec_info[num], 2);
322 /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
323 if (get_board_version() >= 0x13) {
324 SET_STD_TSEC_INFO(tsec_info[num], 3);
325 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
330 /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
331 if (get_board_version() >= 0x13) {
332 SET_STD_TSEC_INFO(tsec_info[num], 4);
333 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
339 printf("No TSECs initialized\n");
344 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
345 mdio_info.name = DEFAULT_MII_NAME;
346 fsl_pq_mdio_init(bis, &mdio_info);
348 tsec_eth_init(bis, tsec_info, num);
352 return pci_eth_init(bis);
355 #if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
356 void ft_pci_setup(void *blob, bd_t *bd)