board/freescale/imx8mn_evk/spl.c

   1 /*
   2  * Copyright 2018-2019 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <hang.h>
  10 #include <image.h>
  11 #include <spl.h>
  12 #include <asm/io.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/imx8mn_pins.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/arch/ddr.h>
  19
  20 #include <dm/uclass.h>
  21 #include <dm/device.h>
  22 #include <dm/uclass-internal.h>
  23 #include <dm/device-internal.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 int spl_board_boot_device(enum boot_device boot_dev_spl)
  28 {
  29         return BOOT_DEVICE_BOOTROM;
  30 }
  31
  32 void spl_dram_init(void)
  33 {
  34         ddr_init(&dram_timing);
  35 }
  36
  37 void spl_board_init(void)
  38 {
  39         struct udevice *dev;
  40         int ret;
  41
  42         puts("Normal Boot\n");
  43
  44         ret = uclass_get_device_by_name(UCLASS_CLK,
  45                                         "clock-controller@30380000",
  46                                         &dev);
  47         if (ret < 0)
  48                 printf("Failed to find clock node. Check device tree\n");
  49 }
  50
  51 #ifdef CONFIG_SPL_LOAD_FIT
  52 int board_fit_config_name_match(const char *name)
  53 {
  54         /* Just empty function now - can't decide what to choose */
  55         debug("%s: %s\n", __func__, name);
  56
  57         return 0;
  58 }
  59 #endif
  60
  61 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  62 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  63
  64 static iomux_v3_cfg_t const uart_pads[] = {
  65         IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  66         IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  67 };
  68
  69 static iomux_v3_cfg_t const wdog_pads[] = {
  70         IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  71 };
  72
  73 int board_early_init_f(void)
  74 {
  75         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  76
  77         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  78
  79         set_wdog_reset(wdog);
  80
  81         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  82
  83         init_uart_clk(1);
  84
  85         return 0;
  86 }
  87
  88 void board_init_f(ulong dummy)
  89 {
  90         int ret;
  91
  92         arch_cpu_init();
  93
  94         init_uart_clk(1);
  95
  96         board_early_init_f();
  97
  98         timer_init();
  99
 100         preloader_console_init();
 101
 102         /* Clear the BSS. */
 103         memset(__bss_start, 0, __bss_end - __bss_start);
 104
 105         ret = spl_init();
 106         if (ret) {
 107                 debug("spl_init() failed: %d\n", ret);
 108                 hang();
 109         }
 110
 111         enable_tzc380();
 112
 113         /* DDR initialization */
 114         spl_dram_init();
 115
 116         board_init_r(NULL, 0);
 117 }