board/freescale/imx8mm_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <hang.h>
   9 #include <image.h>
  10 #include <spl.h>
  11 #include <asm/io.h>
  12 #include <asm/mach-imx/iomux-v3.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx8mm_pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/arch/ddr.h>
  18
  19 #include <dm/uclass.h>
  20 #include <dm/device.h>
  21 #include <dm/uclass-internal.h>
  22 #include <dm/device-internal.h>
  23
  24 #include <power/pmic.h>
  25 #include <power/bd71837.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int spl_board_boot_device(enum boot_device boot_dev_spl)
  30 {
  31         switch (boot_dev_spl) {
  32         case SD2_BOOT:
  33         case MMC2_BOOT:
  34                 return BOOT_DEVICE_MMC1;
  35         case SD3_BOOT:
  36         case MMC3_BOOT:
  37                 return BOOT_DEVICE_MMC2;
  38         default:
  39                 return BOOT_DEVICE_NONE;
  40         }
  41 }
  42
  43 static void spl_dram_init(void)
  44 {
  45         ddr_init(&dram_timing);
  46 }
  47
  48 void spl_board_init(void)
  49 {
  50         puts("Normal Boot\n");
  51 }
  52
  53 #ifdef CONFIG_SPL_LOAD_FIT
  54 int board_fit_config_name_match(const char *name)
  55 {
  56         /* Just empty function now - can't decide what to choose */
  57         debug("%s: %s\n", __func__, name);
  58
  59         return 0;
  60 }
  61 #endif
  62
  63 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  64 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  65
  66 static iomux_v3_cfg_t const uart_pads[] = {
  67         IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  68         IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  69 };
  70
  71 static iomux_v3_cfg_t const wdog_pads[] = {
  72         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  73 };
  74
  75 int board_early_init_f(void)
  76 {
  77         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  78
  79         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  80
  81         set_wdog_reset(wdog);
  82
  83         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  84
  85         return 0;
  86 }
  87
  88 static int power_init_board(void)
  89 {
  90         struct udevice *dev;
  91         int ret;
  92
  93         ret = pmic_get("pmic@4b", &dev);
  94         if (ret == -ENODEV) {
  95                 puts("No pmic\n");
  96                 return 0;
  97         }
  98         if (ret != 0)
  99                 return ret;
 100
 101         /* decrease RESET key long push time from the default 10s to 10ms */
 102         pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
 103
 104         /* unlock the PMIC regs */
 105         pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
 106
 107         /* increase VDD_SOC to typical value 0.85v before first DRAM access */
 108         pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 109
 110         /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
 111         pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 112
 113 #ifndef CONFIG_IMX8M_LPDDR4
 114         /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
 115         pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
 116 #endif
 117
 118         /* lock the PMIC regs */
 119         pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
 120
 121         return 0;
 122 }
 123
 124 void board_init_f(ulong dummy)
 125 {
 126         struct udevice *dev;
 127         int ret;
 128
 129         arch_cpu_init();
 130
 131         init_uart_clk(1);
 132
 133         board_early_init_f();
 134
 135         timer_init();
 136
 137         preloader_console_init();
 138
 139         /* Clear the BSS. */
 140         memset(__bss_start, 0, __bss_end - __bss_start);
 141
 142         ret = spl_early_init();
 143         if (ret) {
 144                 debug("spl_early_init() failed: %d\n", ret);
 145                 hang();
 146         }
 147
 148         ret = uclass_get_device_by_name(UCLASS_CLK,
 149                                         "clock-controller@30380000",
 150                                         &dev);
 151         if (ret < 0) {
 152                 printf("Failed to find clock node. Check device tree\n");
 153                 hang();
 154         }
 155
 156         enable_tzc380();
 157
 158         power_init_board();
 159
 160         /* DDR initialization */
 161         spl_dram_init();
 162
 163         board_init_r(NULL, 0);
 164 }