1 // SPDX-License-Identifier: GPL-2.0+
3 * Board functions for Compulab CM-FX6 board
5 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
7 * Author: Nikita Kiryanov <nikita@compulab.co.il>
13 #include <dwc_ahsata.h>
15 #include <fsl_esdhc_imx.h>
23 #include <fdt_support.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/arch/iomux.h>
29 #include <asm/arch/mxc_hdmi.h>
30 #include <asm/mach-imx/mxc_i2c.h>
31 #include <asm/mach-imx/sata.h>
32 #include <asm/mach-imx/video.h>
35 #include <dm/platform_data/serial_mxc.h>
36 #include <dm/device-internal.h>
37 #include <jffs2/load_kernel.h>
39 #include "../common/eeprom.h"
40 #include "../common/common.h"
42 DECLARE_GLOBAL_DATA_PTR;
44 #ifdef CONFIG_SPLASH_SCREEN
45 static struct splash_location cm_fx6_splash_locations[] = {
48 .storage = SPLASH_STORAGE_SF,
49 .flags = SPLASH_STORAGE_RAW,
54 .storage = SPLASH_STORAGE_MMC,
55 .flags = SPLASH_STORAGE_FS,
60 .storage = SPLASH_STORAGE_USB,
61 .flags = SPLASH_STORAGE_FS,
66 .storage = SPLASH_STORAGE_SATA,
67 .flags = SPLASH_STORAGE_FS,
72 int splash_screen_prepare(void)
74 return splash_source_load(cm_fx6_splash_locations,
75 ARRAY_SIZE(cm_fx6_splash_locations));
79 #ifdef CONFIG_IMX_HDMI
80 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
82 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
84 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
85 imx_enable_hdmi_phy();
88 static struct display_info_t preset_hdmi_1024X768 = {
91 .pixfmt = IPU_PIX_FMT_RGB24,
92 .enable = cm_fx6_enable_hdmi,
106 .vmode = FB_VMODE_NONINTERLACED,
110 static void cm_fx6_setup_display(void)
112 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
115 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
118 int board_video_skip(void)
121 struct display_info_t *preset;
122 char const *panel = env_get("displaytype");
124 if (!panel) /* Also accept panel for backward compatibility */
125 panel = env_get("panel");
130 if (!strcmp(panel, "HDMI"))
131 preset = &preset_hdmi_1024X768;
135 ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
137 printf("Can't init display %s: %d\n", preset->mode.name, ret);
141 preset->enable(preset);
142 printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
148 static inline void cm_fx6_setup_display(void) {}
149 #endif /* CONFIG_VIDEO_IPUV3 */
151 int ipu_displays_init(void)
153 return board_video_skip();
156 #ifdef CONFIG_DWC_AHSATA
157 static int cm_fx6_issd_gpios[] = {
158 /* The order of the GPIOs in the array is important! */
163 CM_FX6_SATA_NSTANDBY1,
164 CM_FX6_SATA_NSTANDBY2,
167 static void cm_fx6_sata_power(int on)
171 if (!on) { /* tell the iSSD that the power will be removed */
172 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
176 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
177 gpio_direction_output(cm_fx6_issd_gpios[i], on);
181 if (!on) /* for compatibility lower the power loss interrupt */
182 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
185 static iomux_v3_cfg_t const sata_pads[] = {
187 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
188 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
189 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
190 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
192 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
193 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
194 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
195 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
196 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
199 static int cm_fx6_setup_issd(void)
203 SETUP_IOMUX_PADS(sata_pads);
205 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
206 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
211 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
218 #define CM_FX6_SATA_INIT_RETRIES 10
221 static int cm_fx6_setup_issd(void) { return 0; }
224 #ifdef CONFIG_SYS_I2C_MXC
225 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
226 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
227 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
230 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
231 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
233 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
234 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
238 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
239 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
241 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
242 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
246 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
247 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
249 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
250 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
254 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
258 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
260 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
265 static int cm_fx6_setup_i2c(void)
269 /* i2c<x>_pads are wierd macro variables; we can't use an array */
270 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
273 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
276 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
283 static int cm_fx6_setup_i2c(void) { return 0; }
286 #ifdef CONFIG_USB_EHCI_MX6
287 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
288 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
289 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
290 #define MX6_USBNC_BASEADDR 0x2184800
291 #define USBNC_USB_H1_PWR_POL (1 << 9)
293 static int cm_fx6_setup_usb_host(void)
297 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
301 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
302 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
307 static int cm_fx6_setup_usb_otg(void)
310 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
312 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
314 printf("USB OTG pwr gpio request failed: %d\n", err);
318 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
319 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
320 MUX_PAD_CTRL(WEAK_PULLDOWN));
321 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
322 /* disable ext. charger detect, or it'll affect signal quality at dp. */
323 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
326 int board_usb_phy_mode(int port)
328 return USB_INIT_HOST;
331 int board_ehci_hcd_init(int port)
334 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
336 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
340 /* Set PWR polarity to match power switch's enable polarity */
341 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
342 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
347 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
356 int board_ehci_power(int port, int on)
359 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
364 static int cm_fx6_setup_usb_otg(void) { return 0; }
365 static int cm_fx6_setup_usb_host(void) { return 0; }
368 #ifdef CONFIG_FEC_MXC
369 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
370 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
372 static int mx6_rgmii_rework(struct phy_device *phydev)
376 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
377 * which cause ethernet link down/up issue, so disable SmartEEE
379 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
380 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
381 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
382 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
384 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
386 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
387 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
388 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
389 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
391 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
394 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
396 /* introduce tx clock delay */
397 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
398 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
400 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
405 int board_phy_config(struct phy_device *phydev)
407 mx6_rgmii_rework(phydev);
409 if (phydev->drv->config)
410 return phydev->drv->config(phydev);
415 static iomux_v3_cfg_t const enet_pads[] = {
416 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
417 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
418 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
419 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
420 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
421 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
422 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
423 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
424 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
425 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
426 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
427 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
428 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
429 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
430 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
431 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
432 MUX_PAD_CTRL(ENET_PAD_CTRL)),
433 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
434 MUX_PAD_CTRL(ENET_PAD_CTRL)),
435 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
436 MUX_PAD_CTRL(ENET_PAD_CTRL)),
439 static int handle_mac_address(char *env_var, uint eeprom_bus)
441 unsigned char enetaddr[6];
444 rc = eth_env_get_enetaddr(env_var, enetaddr);
448 rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
452 if (!is_valid_ethaddr(enetaddr))
455 return eth_env_set_enetaddr(env_var, enetaddr);
458 #define SB_FX6_I2C_EEPROM_BUS 0
459 #define NO_MAC_ADDR "No MAC address found for %s\n"
460 int board_eth_init(bd_t *bis)
464 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
465 printf(NO_MAC_ADDR, "primary NIC");
467 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
468 printf(NO_MAC_ADDR, "secondary NIC");
470 SETUP_IOMUX_PADS(enet_pads);
472 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
474 printf("Etnernet NRST gpio request failed: %d\n", err);
475 gpio_direction_output(CM_FX6_ENET_NRST, 0);
477 gpio_set_value(CM_FX6_ENET_NRST, 1);
479 return cpu_eth_init(bis);
483 #ifdef CONFIG_NAND_MXS
484 static iomux_v3_cfg_t const nand_pads[] = {
485 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
486 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
487 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
488 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
489 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
490 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
491 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
492 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
493 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
494 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
495 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
496 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
497 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
498 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
501 static void cm_fx6_setup_gpmi_nand(void)
503 SETUP_IOMUX_PADS(nand_pads);
504 /* Enable clock roots */
505 enable_usdhc_clk(1, 3);
506 enable_usdhc_clk(1, 4);
508 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
509 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
510 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
513 static void cm_fx6_setup_gpmi_nand(void) {}
516 #ifdef CONFIG_MXC_SPI
517 int cm_fx6_setup_ecspi(void)
519 cm_fx6_set_ecspi_iomux();
520 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
523 int cm_fx6_setup_ecspi(void) { return 0; }
526 #ifdef CONFIG_OF_BOARD_SETUP
527 #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/"
529 static const struct node_info nodes[] = {
531 * Both entries target the same flash chip. The st,m25p compatible
532 * is used in the vendor device trees, while upstream uses (the
533 * documented) jedec,spi-nor compatible.
535 { "st,m25p", MTD_DEV_TYPE_NOR, },
536 { "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
539 int ft_board_setup(void *blob, bd_t *bd)
544 char baseboard_name[16];
547 fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
550 if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
551 fdt_find_and_setprop(blob,
552 "/soc/aips-bus@02100000/ethernet@02188000",
553 "local-mac-address", enetaddr, 6, 1);
556 if (eth_env_get_enetaddr("eth1addr", enetaddr)) {
557 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
561 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
563 baseboard_rev = cl_eeprom_get_board_rev(0);
564 err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
565 if (err || baseboard_rev == 0)
566 return 0; /* Assume not an early revision SB-FX6m baseboard */
568 if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
569 nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
570 fdt_delprop(blob, nodeoffset, "cd-gpios");
571 fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
573 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
585 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
586 cm_fx6_setup_gpmi_nand();
588 ret = cm_fx6_setup_ecspi();
590 printf("Warning: ECSPI setup failed: %d\n", ret);
592 ret = cm_fx6_setup_usb_otg();
594 printf("Warning: USB OTG setup failed: %d\n", ret);
596 ret = cm_fx6_setup_usb_host();
598 printf("Warning: USB host setup failed: %d\n", ret);
601 * cm-fx6 may have iSSD not assembled and in this case it has
602 * bypasses for a (m)SATA socket on the baseboard. The socketed
603 * device is not controlled by those GPIOs. So just print a warning
604 * if the setup fails.
606 ret = cm_fx6_setup_issd();
608 printf("Warning: iSSD setup failed: %d\n", ret);
610 /* Warn on failure but do not abort boot */
611 ret = cm_fx6_setup_i2c();
613 printf("Warning: I2C setup failed: %d\n", ret);
615 cm_fx6_setup_display();
617 /* This should be done in the MMC driver when MX6 has a clock driver */
618 #ifdef CONFIG_FSL_ESDHC_IMX
619 if (IS_ENABLED(CONFIG_BLK)) {
622 cm_fx6_set_usdhc_iomux();
623 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
624 enable_usdhc_clk(1, i);
631 int board_late_init(void)
633 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
634 char baseboard_name[16];
638 env_set("board_rev", "MX6Q");
640 env_set("board_rev", "MX6DL");
642 err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
646 if (!strncmp("SB-FX6m", baseboard_name, 7))
647 env_set("board_name", "Utilite");
654 puts("Board: CM-FX6\n");
658 int misc_init_r(void)
665 int dram_init_banksize(void)
667 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
668 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
670 switch (gd->ram_size) {
671 case 0x10000000: /* DDR_16BIT_256MB */
672 gd->bd->bi_dram[0].size = 0x10000000;
673 gd->bd->bi_dram[1].size = 0;
675 case 0x20000000: /* DDR_32BIT_512MB */
676 gd->bd->bi_dram[0].size = 0x20000000;
677 gd->bd->bi_dram[1].size = 0;
680 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
681 gd->bd->bi_dram[0].size = 0x20000000;
682 gd->bd->bi_dram[1].size = 0x20000000;
683 } else { /* DDR_64BIT_1GB */
684 gd->bd->bi_dram[0].size = 0x40000000;
685 gd->bd->bi_dram[1].size = 0;
688 case 0x80000000: /* DDR_64BIT_2GB */
689 gd->bd->bi_dram[0].size = 0x40000000;
690 gd->bd->bi_dram[1].size = 0x40000000;
692 case 0xEFF00000: /* DDR_64BIT_4GB */
693 gd->bd->bi_dram[0].size = 0x70000000;
694 gd->bd->bi_dram[1].size = 0x7FF00000;
703 gd->ram_size = imx_ddr_size();
704 switch (gd->ram_size) {
711 gd->ram_size -= 0x100000;
714 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
721 u32 get_board_rev(void)
723 return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
726 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
727 .reg = (struct mxc_uart *)UART4_BASE,
730 U_BOOT_DEVICE(cm_fx6_serial) = {
731 .name = "serial_mxc",
732 .platdata = &cm_fx6_mxc_serial_plat,
735 #if CONFIG_IS_ENABLED(AHCI)
736 static int sata_imx_probe(struct udevice *dev)
740 /* Make sure this gpio has logical 0 value */
741 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
743 cm_fx6_sata_power(1);
745 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
748 printf("SATA setup failed: %d\n", err);
754 err = dwc_ahsata_probe(dev);
758 /* There is no device on the SATA port */
759 if (sata_dm_port_status(0, 0) == 0)
762 /* There's a device, but link not established. Retry */
763 device_remove(dev, DM_REMOVE_NORMAL);
769 static int sata_imx_remove(struct udevice *dev)
771 cm_fx6_sata_power(0);
777 struct ahci_ops sata_imx_ops = {
778 .port_status = dwc_ahsata_port_status,
779 .reset = dwc_ahsata_bus_reset,
780 .scan = dwc_ahsata_scan,
783 static const struct udevice_id sata_imx_ids[] = {
784 { .compatible = "fsl,imx6q-ahci" },
788 U_BOOT_DRIVER(sata_imx) = {
791 .of_match = sata_imx_ids,
792 .ops = &sata_imx_ops,
793 .probe = sata_imx_probe,
794 .remove = sata_imx_remove, /* reset bus to stop it */