1 // SPDX-License-Identifier: GPL-2.0+
3 * Bluewater Systems Snapper 9260/9G20 modules
5 * (C) Copyright 2011 Bluewater Systems
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon <ryan@bluewatersys.com>
11 #include <atmel_lcd.h>
12 #include <atmel_lcdc.h>
13 #include <atmel_mci.h>
24 #include <asm/mach-types.h>
25 #include <asm/arch/at91sam9g45_matrix.h>
26 #include <asm/arch/at91sam9_smc.h>
27 #include <asm/arch/at91_common.h>
28 #include <asm/arch/at91_emac.h>
29 #include <asm/arch/at91_rstc.h>
30 #include <asm/arch/at91_rtc.h>
31 #include <asm/arch/at91_sck.h>
32 #include <asm/arch/atmel_serial.h>
33 #include <asm/arch/clk.h>
34 #include <asm/arch/gpio.h>
35 #include <dm/uclass-internal.h>
37 #ifdef CONFIG_GURNARD_SPLASH
38 #include "splash_logo.h"
41 DECLARE_GLOBAL_DATA_PTR;
43 /* IO Expander pins */
44 #define IO_EXP_ETH_RESET (0 << 1)
45 #define IO_EXP_ETH_POWER (1 << 1)
48 static void gurnard_macb_hw_init(void)
50 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
52 at91_periph_clk_enable(ATMEL_ID_EMAC);
56 * RXDV (PA12) => MODE0 - PHY also has pull-up
57 * ERX0 (PA13) => MODE1 - PHY also has pull-up
58 * ERX1 (PA15) => MODE2 - PHY also has pull-up
60 writel(pin_to_mask(AT91_PIN_PA15) |
61 pin_to_mask(AT91_PIN_PA12) |
62 pin_to_mask(AT91_PIN_PA13),
71 #ifdef CONFIG_CMD_NAND
72 static int gurnard_nand_hw_init(void)
74 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
75 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
79 /* Enable CS3 as NAND/SmartMedia */
80 setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
82 /* Configure SMC CS3 for NAND/SmartMedia */
83 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
84 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
86 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
87 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
89 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
91 #ifdef CONFIG_SYS_NAND_DBW_16
92 flags = AT91_SMC_MODE_DBW_16;
94 flags = AT91_SMC_MODE_DBW_8;
96 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
97 AT91_SMC_MODE_EXNW_DISABLE |
99 AT91_SMC_MODE_TDF_CYCLE(3),
102 ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
105 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
107 /* Enable NandFlash */
108 ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
111 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
117 #ifdef CONFIG_GURNARD_SPLASH
118 static void lcd_splash(int width, int height)
122 u16 *base_addr = (u16 *)gd->video_bottom;
124 memset(base_addr, 0xff, width * height * 2);
126 * Blit the logo to the center of the screen
128 for (y = 0; y < BMP_LOGO_HEIGHT; y++) {
129 for (x = 0; x < BMP_LOGO_WIDTH; x++) {
131 colour = bmp_logo_palette[bmp_logo_bitmap[
132 y * BMP_LOGO_WIDTH + x]];
133 posx = x + (width - BMP_LOGO_WIDTH) / 2;
135 base_addr[posy * width + posx] = colour;
141 #ifdef CONFIG_DM_VIDEO
142 static void at91sam9g45_lcd_hw_init(void)
144 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
145 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
146 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
147 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
148 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
150 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
151 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
152 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
153 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
154 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
155 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
156 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
157 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
158 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
159 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
160 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
161 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
162 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
163 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
164 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
165 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
166 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
167 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
168 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
169 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
170 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
171 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
172 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
173 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
175 at91_periph_clk_enable(ATMEL_ID_LCDC);
179 #ifdef CONFIG_GURNARD_FPGA
181 * Initialise the memory bus settings so that we can talk to the
184 static int fpga_hw_init(void)
186 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
187 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
190 setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);
192 at91_set_a_periph(2, 4, 0); /* EBIA21 */
193 at91_set_a_periph(2, 5, 0); /* EBIA22 */
194 at91_set_a_periph(2, 6, 0); /* EBIA23 */
195 at91_set_a_periph(2, 7, 0); /* EBIA24 */
196 at91_set_a_periph(2, 12, 0); /* EBIA25 */
197 for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
198 at91_set_a_periph(2, i, 0);
200 /* configure SMC cs0 for FPGA access timing */
201 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
202 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
204 writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
205 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
207 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
209 writel(AT91_SMC_MODE_BAT |
210 AT91_SMC_MODE_EXNW_DISABLE |
211 AT91_SMC_MODE_DBW_32 |
213 AT91_SMC_MODE_TDF_CYCLE(2),
216 /* Do a write to within EBI_CS1 to enable the SDCK */
217 writel(0, ATMEL_BASE_CS1);
223 #ifdef CONFIG_CMD_USB
225 #define USB0_ENABLE_PIN AT91_PIN_PB22
226 #define USB1_ENABLE_PIN AT91_PIN_PB23
228 void gurnard_usb_init(void)
230 at91_set_gpio_output(USB0_ENABLE_PIN, 1);
231 at91_set_gpio_value(USB0_ENABLE_PIN, 0);
232 at91_set_gpio_output(USB1_ENABLE_PIN, 1);
233 at91_set_gpio_value(USB1_ENABLE_PIN, 0);
237 #ifdef CONFIG_GENERIC_ATMEL_MCI
238 int cpu_mmc_init(bd_t *bis)
240 return atmel_mci_init((void *)ATMEL_BASE_MCI0);
244 static void gurnard_enable_console(int enable)
246 at91_set_gpio_output(AT91_PIN_PB14, 1);
247 at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1);
250 void at91sam9g45_slowclock_init(void)
253 * On AT91SAM9G45 revC CPUs, the slow clock can be based on an
254 * internal impreciseRC oscillator or an external 32kHz oscillator.
255 * Switch to the latter.
258 ulong *reg = (ulong *)ATMEL_BASE_SCKCR;
261 if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) {
263 tmp |= AT91SAM9G45_SCKCR_OSC32EN;
265 for (i = 0; i < 1200; i++)
267 tmp |= AT91SAM9G45_SCKCR_OSCSEL_32;
270 tmp &= ~AT91SAM9G45_SCKCR_RCEN;
275 int board_early_init_f(void)
277 at91_seriald_hw_init();
278 gurnard_enable_console(1);
286 #ifdef CONFIG_CMD_NAND
290 at91_periph_clk_enable(ATMEL_ID_PIOA);
291 at91_periph_clk_enable(ATMEL_ID_PIOB);
292 at91_periph_clk_enable(ATMEL_ID_PIOC);
293 at91_periph_clk_enable(ATMEL_ID_PIODE);
295 at91sam9g45_slowclock_init();
298 * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux
299 * boots with spurious IRQs.
301 writel(0xffffffff, AT91_RTC_IDR);
303 /* Make sure that the reset signal is attached properly */
304 setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN);
306 gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
308 /* Address of boot parameters */
309 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
311 #ifdef CONFIG_CMD_NAND
312 ret = gurnard_nand_hw_init();
316 #ifdef CONFIG_ATMEL_SPI
317 at91_spi0_hw_init(1 << 4);
321 gurnard_macb_hw_init();
324 #ifdef CONFIG_GURNARD_FPGA
328 #ifdef CONFIG_CMD_USB
332 #ifdef CONFIG_CMD_MMC
333 at91_set_A_periph(AT91_PIN_PA12, 0);
334 at91_set_gpio_output(AT91_PIN_PA8, 1);
335 at91_set_gpio_value(AT91_PIN_PA8, 0);
339 #ifdef CONFIG_DM_VIDEO
340 at91sam9g45_lcd_hw_init();
341 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
343 /* Select the second timing index for board rev 2 */
344 rev_str = env_get("board_rev");
345 if (rev_str && !strncmp(rev_str, "2", 1)) {
348 uclass_find_first_device(UCLASS_VIDEO, &dev);
350 struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
352 plat->timing_index = 1;
360 int board_late_init(void)
362 u_int8_t env_enetaddr[8];
368 * Set MAC address so we do not need to init Ethernet before Linux
371 env_str = env_get("ethaddr");
373 struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC;
374 /* Parse MAC address */
375 for (i = 0; i < 6; i++) {
376 env_enetaddr[i] = env_str ?
377 simple_strtoul(env_str, &end, 16) : 0;
379 env_str = (*end) ? end+1 : end;
382 /* Set hardware address */
383 writel(env_enetaddr[0] | env_enetaddr[1] << 8 |
384 env_enetaddr[2] << 16 | env_enetaddr[3] << 24,
386 writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h);
388 printf("MAC: %s\n", env_get("ethaddr"));
390 /* Not set in environment */
391 printf("MAC: not set\n");
393 #ifdef CONFIG_GURNARD_SPLASH
394 lcd_splash(480, 272);
400 #ifndef CONFIG_DM_ETH
401 int board_eth_init(bd_t *bis)
403 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0);
409 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
410 CONFIG_SYS_SDRAM_SIZE);
418 static struct atmel_serial_platdata at91sam9260_serial_plat = {
419 .base_addr = ATMEL_BASE_DBGU,
422 U_BOOT_DEVICE(at91sam9260_serial) = {
423 .name = "serial_atmel",
424 .platdata = &at91sam9260_serial_plat,