1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
6 * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
7 * Copyright (C) 2011 Freescale Semiconductor, Inc.
13 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/iomux-mx53.h>
16 #include <asm/mach-imx/mx5_video.h>
21 GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
22 GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
23 GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
24 GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
25 GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
26 GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
27 GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
28 GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
29 GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
30 GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
31 GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
32 GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
33 GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
34 GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
35 GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
38 #define CCAT_BASE_ADDR ((void *)0xf0000000)
39 #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
40 #define CCAT_SIZE 1191788
41 #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
42 static const char CCAT_SIGNATURE[] = "CCAT";
44 static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
45 static const u32 CCAT_MODE_RUN = 0x0033DC8F;
47 DECLARE_GLOBAL_DATA_PTR;
49 u32 get_board_rev(void)
51 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
52 struct fuse_bank *bank = &iim->bank[0];
53 struct fuse_bank0_regs *fuse =
54 (struct fuse_bank0_regs *)bank->fuse_regs;
56 int rev = readl(&fuse->gp[6]);
58 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
63 * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
65 void weim_cs0_settings(u32 mode)
67 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
69 writel(0x0, &weim_regs->cs0gcr1);
70 writel(mode, &weim_regs->cs0gcr1);
71 writel(0x00001002, &weim_regs->cs0gcr2);
73 writel(0x04000000, &weim_regs->cs0rcr1);
74 writel(0x00000000, &weim_regs->cs0rcr2);
76 writel(0x04000000, &weim_regs->cs0wcr1);
77 writel(0x00000000, &weim_regs->cs0wcr2);
80 static void setup_gpio_eim(void)
82 gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
83 gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
84 gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
85 gpio_direction_input(GPIO_C3_STATUS);
86 gpio_direction_input(GPIO_C3_DONE);
87 gpio_direction_output(GPIO_C3_CONFIG, 1);
89 weim_cs0_settings(CCAT_MODE_RUN);
92 static void setup_gpio_sups(void)
94 gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
95 gpio_direction_input(GPIO_SUPS_INT);
97 static const int BLINK_INTERVALL = 50000;
99 while (gpio_get_value(GPIO_SUPS_INT)) {
100 /* signal "CX SUPS power fail" */
101 gpio_set_value(GPIO_LED_PWR_R,
102 (++status / BLINK_INTERVALL) % 2);
105 /* signal "CX power up" */
106 gpio_set_value(GPIO_LED_PWR_R, 1);
109 static void setup_gpio_leds(void)
111 gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
112 gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
113 gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
114 gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
115 gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
116 gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
117 gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
118 gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
119 gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
121 gpio_direction_output(GPIO_LED_SD2_R, 0);
122 gpio_direction_output(GPIO_LED_SD2_B, 0);
123 gpio_direction_output(GPIO_LED_SD2_G, 0);
124 gpio_direction_output(GPIO_LED_SD1_R, 0);
125 gpio_direction_output(GPIO_LED_SD1_B, 0);
126 gpio_direction_output(GPIO_LED_SD1_G, 0);
127 gpio_direction_output(GPIO_LED_PWR_R, 0);
128 gpio_direction_output(GPIO_LED_PWR_B, 0);
129 gpio_direction_output(GPIO_LED_PWR_G, 0);
132 static int power_init(void)
134 /* nothing to do on CX9020 */
138 static void clock_1GHz(void)
141 u32 ref_clk = MXC_HCLK;
143 * After increasing voltage to 1.25V, we can switch
144 * CPU clock to 1GHz and DDR to 400MHz safely
146 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
148 printf("CPU: Switch CPU clock to 1GHZ failed\n");
150 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
151 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
153 printf("CPU: Switch DDR clock to 400MHz failed\n");
156 int board_early_init_f(void)
164 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
166 mxc_set_sata_internal_clock();
178 puts("Board: Beckhoff CX9020\n");
183 static int ccat_config_fn(int assert_config, int flush, int cookie)
185 /* prepare FPGA for programming */
186 weim_cs0_settings(CCAT_MODE_CONFIG);
187 gpio_set_value(GPIO_C3_CONFIG, 0);
189 gpio_set_value(GPIO_C3_CONFIG, 1);
195 static int ccat_status_fn(int cookie)
200 static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
202 const uint8_t *const buffer = buf;
206 for (i = 0; i < buf_len; ++i)
207 writeb(buffer[i], CCAT_BASE_ADDR);
209 writeb(0xff, CCAT_BASE_ADDR);
210 writeb(0xff, CCAT_BASE_ADDR);
215 static int ccat_done_fn(int cookie)
217 /* programming complete? */
218 return gpio_get_value(GPIO_C3_DONE);
221 static int ccat_post_fn(int cookie)
223 /* switch to FPGA run mode */
224 weim_cs0_settings(CCAT_MODE_RUN);
225 invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
227 if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
228 printf("Verifing CCAT firmware failed, signature not found\n");
232 /* signal "CX booting OS" */
233 gpio_set_value(GPIO_LED_PWR_R, 1);
234 gpio_set_value(GPIO_LED_PWR_G, 1);
235 gpio_set_value(GPIO_LED_PWR_B, 0);
239 static Altera_CYC2_Passive_Serial_fns ccat_fns = {
240 .config = ccat_config_fn,
241 .status = ccat_status_fn,
242 .done = ccat_done_fn,
243 .write = ccat_write_fn,
244 .abort = ccat_post_fn,
245 .post = ccat_post_fn,
248 static Altera_desc ccat_fpga = {
249 .family = Altera_CYC2,
250 .iface = passive_serial,
252 .iface_fns = &ccat_fns,
253 .base = CCAT_BASE_ADDR,
256 int board_late_init(void)
262 fpga_add(fpga_altera, &ccat_fpga);