1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sci/sci.h>
15 #include <asm/arch/imx8-pins.h>
16 #include <asm/arch/iomux.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
21 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
22 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
23 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
25 #define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
26 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
27 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
28 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
30 #define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
31 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
32 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
33 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
35 #define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
36 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
37 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
38 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
40 #define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
41 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
42 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
43 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
45 #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
46 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
47 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
48 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
50 #define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
51 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
52 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
53 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
55 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
56 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
57 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
58 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
59 #ifdef CONFIG_FSL_ESDHC
61 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
62 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
64 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
65 {USDHC1_BASE_ADDR, 0, 8},
66 {USDHC2_BASE_ADDR, 0, 4},
67 {USDHC3_BASE_ADDR, 0, 4},
70 static iomux_cfg_t emmc0[] = {
71 SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
72 SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
73 SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
74 SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
75 SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
76 SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
77 SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
78 SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
79 SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
80 SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
81 SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
82 SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
85 static iomux_cfg_t usdhc2_sd[] = {
86 SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
87 SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
88 SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
89 SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
90 SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
91 SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
92 SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
93 SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
94 SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
97 int board_mmc_init(bd_t *bis)
102 * According to the board_mmc_init() the following map is done:
103 * (U-Boot device node) (Physical Port)
108 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
111 ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
112 if (ret != SC_ERR_NONE)
115 imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
117 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
120 ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
121 if (ret != SC_ERR_NONE)
123 ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
124 if (ret != SC_ERR_NONE)
127 imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
129 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
130 gpio_request(USDHC2_CD_GPIO, "sd2_cd");
131 gpio_direction_input(USDHC2_CD_GPIO);
134 printf("Warning: you configured more USDHC controllers"
135 "(%d) than supported by the board\n", i + 1);
138 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
140 printf("Warning: failed to initialize mmc dev %d\n", i);
148 int board_mmc_getcd(struct mmc *mmc)
150 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
153 switch (cfg->esdhc_base) {
154 case USDHC1_BASE_ADDR:
157 case USDHC2_BASE_ADDR:
158 ret = !gpio_get_value(USDHC1_CD_GPIO);
160 case USDHC3_BASE_ADDR:
161 ret = !gpio_get_value(USDHC2_CD_GPIO);
168 #endif /* CONFIG_FSL_ESDHC */
170 void spl_board_init(void)
172 #if defined(CONFIG_SPL_SPI_SUPPORT)
173 if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
174 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
175 puts("Warning: failed to initialize FSPI0\n");
180 puts("Normal Boot\n");
183 void spl_board_prepare_for_boot(void)
185 #if defined(CONFIG_SPL_SPI_SUPPORT)
186 if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
187 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
188 puts("Warning: failed to turn off FSPI0\n");
194 #ifdef CONFIG_SPL_LOAD_FIT
195 int board_fit_config_name_match(const char *name)
197 /* Just empty function now - can't decide what to choose */
198 debug("%s: %s\n", __func__, name);
204 void board_init_f(ulong dummy)
206 /* Clear global data */
207 memset((void *)gd, 0, sizeof(gd_t));
211 board_early_init_f();
215 preloader_console_init();
218 memset(__bss_start, 0, __bss_end - __bss_start);
220 board_init_r(NULL, 0);