arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/acpi.h>
  31 #include <linux/sysdev.h>
  32 #ifdef CONFIG_ACPI
  33 #include <acpi/acpi_bus.h>
  34 #endif
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/proto.h>
  40 #include <asm/mach_apic.h>
  41 #include <asm/acpi.h>
  42 #include <asm/dma.h>
  43 #include <asm/nmi.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 int timer_over_8254 __initdata = 0;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 /*
  62  * # of IRQ routing registers
  63  */
  64 int nr_ioapic_registers[MAX_IO_APICS];
  65
  66 /*
  67  * Rough estimation of how many shared IRQs there are, can
  68  * be changed anytime.
  69  */
  70 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  71 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  72
  73 /*
  74  * This is performance-critical, we want to do it O(1)
  75  *
  76  * the indexing order of this array favors 1:1 mappings
  77  * between pins and IRQs.
  78  */
  79
  80 static struct irq_pin_list {
  81         short apic, pin, next;
  82 } irq_2_pin[PIN_MAP_SIZE];
  83
  84 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  85 #ifdef CONFIG_PCI_MSI
  86 #define vector_to_irq(vector)   \
  87         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  88 #else
  89 #define vector_to_irq(vector)   (vector)
  90 #endif
  91
  92 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  93                                                                         \
  94 {                                                                       \
  95         int pin;                                                        \
  96         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  97                                                                         \
  98         BUG_ON(irq >= NR_IRQS);                                         \
  99         for (;;) {                                                      \
 100                 unsigned int reg;                                       \
 101                 pin = entry->pin;                                       \
 102                 if (pin == -1)                                          \
 103                         break;                                          \
 104                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 105                 reg ACTION;                                             \
 106                 io_apic_modify(entry->apic, reg);                       \
 107                 if (!entry->next)                                       \
 108                         break;                                          \
 109                 entry = irq_2_pin + entry->next;                        \
 110         }                                                               \
 111         FINAL;                                                          \
 112 }
 113
 114 #ifdef CONFIG_SMP
 115 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 116 {
 117         unsigned long flags;
 118         unsigned int dest;
 119         cpumask_t tmp;
 120
 121         cpus_and(tmp, mask, cpu_online_map);
 122         if (cpus_empty(tmp))
 123                 tmp = TARGET_CPUS;
 124
 125         cpus_and(mask, tmp, CPU_MASK_ALL);
 126
 127         dest = cpu_mask_to_apicid(mask);
 128
 129         /*
 130          * Only the high 8 bits are valid.
 131          */
 132         dest = SET_APIC_LOGICAL_ID(dest);
 133
 134         spin_lock_irqsave(&ioapic_lock, flags);
 135         __DO_ACTION(1, = dest, )
 136         set_irq_info(irq, mask);
 137         spin_unlock_irqrestore(&ioapic_lock, flags);
 138 }
 139 #endif
 140
 141 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 142
 143 /*
 144  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 145  * shared ISA-space IRQs, so we have to support them. We are super
 146  * fast in the common case, and fast for shared ISA-space IRQs.
 147  */
 148 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 149 {
 150         static int first_free_entry = NR_IRQS;
 151         struct irq_pin_list *entry = irq_2_pin + irq;
 152
 153         BUG_ON(irq >= NR_IRQS);
 154         while (entry->next)
 155                 entry = irq_2_pin + entry->next;
 156
 157         if (entry->pin != -1) {
 158                 entry->next = first_free_entry;
 159                 entry = irq_2_pin + entry->next;
 160                 if (++first_free_entry >= PIN_MAP_SIZE)
 161                         panic("io_apic.c: ran out of irq_2_pin entries!");
 162         }
 163         entry->apic = apic;
 164         entry->pin = pin;
 165 }
 166
 167
 168 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 169                                                                         \
 170         static void name##_IO_APIC_irq (unsigned int irq)               \
 171         __DO_ACTION(R, ACTION, FINAL)
 172
 173 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 174                                                 /* mask = 1 */
 175 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 176                                                 /* mask = 0 */
 177
 178 static void mask_IO_APIC_irq (unsigned int irq)
 179 {
 180         unsigned long flags;
 181
 182         spin_lock_irqsave(&ioapic_lock, flags);
 183         __mask_IO_APIC_irq(irq);
 184         spin_unlock_irqrestore(&ioapic_lock, flags);
 185 }
 186
 187 static void unmask_IO_APIC_irq (unsigned int irq)
 188 {
 189         unsigned long flags;
 190
 191         spin_lock_irqsave(&ioapic_lock, flags);
 192         __unmask_IO_APIC_irq(irq);
 193         spin_unlock_irqrestore(&ioapic_lock, flags);
 194 }
 195
 196 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 197 {
 198         struct IO_APIC_route_entry entry;
 199         unsigned long flags;
 200
 201         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 202         spin_lock_irqsave(&ioapic_lock, flags);
 203         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 204         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 205         spin_unlock_irqrestore(&ioapic_lock, flags);
 206         if (entry.delivery_mode == dest_SMI)
 207                 return;
 208         /*
 209          * Disable it in the IO-APIC irq-routing table:
 210          */
 211         memset(&entry, 0, sizeof(entry));
 212         entry.mask = 1;
 213         spin_lock_irqsave(&ioapic_lock, flags);
 214         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 215         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 216         spin_unlock_irqrestore(&ioapic_lock, flags);
 217 }
 218
 219 static void clear_IO_APIC (void)
 220 {
 221         int apic, pin;
 222
 223         for (apic = 0; apic < nr_ioapics; apic++)
 224                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 225                         clear_IO_APIC_pin(apic, pin);
 226 }
 227
 228 int skip_ioapic_setup;
 229 int ioapic_force;
 230
 231 /* dummy parsing: see setup.c */
 232
 233 static int __init disable_ioapic_setup(char *str)
 234 {
 235         skip_ioapic_setup = 1;
 236         return 1;
 237 }
 238
 239 static int __init enable_ioapic_setup(char *str)
 240 {
 241         ioapic_force = 1;
 242         skip_ioapic_setup = 0;
 243         return 1;
 244 }
 245
 246 __setup("noapic", disable_ioapic_setup);
 247 __setup("apic", enable_ioapic_setup);
 248
 249 static int __init setup_disable_8254_timer(char *s)
 250 {
 251         timer_over_8254 = -1;
 252         return 1;
 253 }
 254 static int __init setup_enable_8254_timer(char *s)
 255 {
 256         timer_over_8254 = 2;
 257         return 1;
 258 }
 259
 260 __setup("disable_8254_timer", setup_disable_8254_timer);
 261 __setup("enable_8254_timer", setup_enable_8254_timer);
 262
 263 #include <asm/pci-direct.h>
 264 #include <linux/pci_ids.h>
 265 #include <linux/pci.h>
 266
 267
 268 #ifdef CONFIG_ACPI
 269
 270 static int nvidia_hpet_detected __initdata;
 271
 272 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
 273 {
 274         nvidia_hpet_detected = 1;
 275         return 0;
 276 }
 277 #endif
 278
 279 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 280    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 281    Use pci direct infrastructure because this runs before the PCI subsystem.
 282
 283    Can be overwritten with "apic"
 284
 285    And another hack to disable the IOMMU on VIA chipsets.
 286
 287    ... and others. Really should move this somewhere else.
 288
 289    Kludge-O-Rama. */
 290 void __init check_ioapic(void)
 291 {
 292         int num,slot,func;
 293         /* Poor man's PCI discovery */
 294         for (num = 0; num < 32; num++) {
 295                 for (slot = 0; slot < 32; slot++) {
 296                         for (func = 0; func < 8; func++) {
 297                                 u32 class;
 298                                 u32 vendor;
 299                                 u8 type;
 300                                 class = read_pci_config(num,slot,func,
 301                                                         PCI_CLASS_REVISION);
 302                                 if (class == 0xffffffff)
 303                                         break;
 304
 305                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 306                                         continue;
 307
 308                                 vendor = read_pci_config(num, slot, func,
 309                                                          PCI_VENDOR_ID);
 310                                 vendor &= 0xffff;
 311                                 switch (vendor) {
 312                                 case PCI_VENDOR_ID_VIA:
 313 #ifdef CONFIG_IOMMU
 314                                         if ((end_pfn > MAX_DMA32_PFN ||
 315                                              force_iommu) &&
 316                                             !iommu_aperture_allowed) {
 317                                                 printk(KERN_INFO
 318     "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
 319                                                 iommu_aperture_disabled = 1;
 320                                         }
 321 #endif
 322                                         return;
 323                                 case PCI_VENDOR_ID_NVIDIA:
 324 #ifdef CONFIG_ACPI
 325                                         /*
 326                                          * All timer overrides on Nvidia are
 327                                          * wrong unless HPET is enabled.
 328                                          */
 329                                         nvidia_hpet_detected = 0;
 330                                         acpi_table_parse(ACPI_HPET,
 331                                                         nvidia_hpet_check);
 332                                         if (nvidia_hpet_detected == 0) {
 333                                                 acpi_skip_timer_override = 1;
 334                                                 printk(KERN_INFO "Nvidia board "
 335                                                     "detected. Ignoring ACPI "
 336                                                     "timer override.\n");
 337                                         }
 338 #endif
 339                                         /* RED-PEN skip them on mptables too? */
 340                                         return;
 341
 342                                 /* This should be actually default, but
 343                                    for 2.6.16 let's do it for ATI only where
 344                                    it's really needed. */
 345                                 case PCI_VENDOR_ID_ATI:
 346                                         if (timer_over_8254 == 1) {
 347                                                 timer_over_8254 = 0;
 348                                         printk(KERN_INFO
 349                 "ATI board detected. Disabling timer routing over 8254.\n");
 350                                         }
 351                                         return;
 352                                 }
 353
 354
 355                                 /* No multi-function device? */
 356                                 type = read_pci_config_byte(num,slot,func,
 357                                                             PCI_HEADER_TYPE);
 358                                 if (!(type & 0x80))
 359                                         break;
 360                         }
 361                 }
 362         }
 363 }
 364
 365 /*
 366  * Find the IRQ entry number of a certain pin.
 367  */
 368 static int find_irq_entry(int apic, int pin, int type)
 369 {
 370         int i;
 371
 372         for (i = 0; i < mp_irq_entries; i++)
 373                 if (mp_irqs[i].mpc_irqtype == type &&
 374                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 375                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 376                     mp_irqs[i].mpc_dstirq == pin)
 377                         return i;
 378
 379         return -1;
 380 }
 381
 382 /*
 383  * Find the pin to which IRQ[irq] (ISA) is connected
 384  */
 385 static int __init find_isa_irq_pin(int irq, int type)
 386 {
 387         int i;
 388
 389         for (i = 0; i < mp_irq_entries; i++) {
 390                 int lbus = mp_irqs[i].mpc_srcbus;
 391
 392                 if (mp_bus_id_to_type[lbus] == MP_BUS_ISA &&
 393                     (mp_irqs[i].mpc_irqtype == type) &&
 394                     (mp_irqs[i].mpc_srcbusirq == irq))
 395
 396                         return mp_irqs[i].mpc_dstirq;
 397         }
 398         return -1;
 399 }
 400
 401 static int __init find_isa_irq_apic(int irq, int type)
 402 {
 403         int i;
 404
 405         for (i = 0; i < mp_irq_entries; i++) {
 406                 int lbus = mp_irqs[i].mpc_srcbus;
 407
 408                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA) &&
 409                     (mp_irqs[i].mpc_irqtype == type) &&
 410                     (mp_irqs[i].mpc_srcbusirq == irq))
 411                         break;
 412         }
 413         if (i < mp_irq_entries) {
 414                 int apic;
 415                 for(apic = 0; apic < nr_ioapics; apic++) {
 416                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 417                                 return apic;
 418                 }
 419         }
 420
 421         return -1;
 422 }
 423
 424 /*
 425  * Find a specific PCI IRQ entry.
 426  * Not an __init, possibly needed by modules
 427  */
 428 static int pin_2_irq(int idx, int apic, int pin);
 429
 430 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 431 {
 432         int apic, i, best_guess = -1;
 433
 434         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 435                 bus, slot, pin);
 436         if (mp_bus_id_to_pci_bus[bus] == -1) {
 437                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 438                 return -1;
 439         }
 440         for (i = 0; i < mp_irq_entries; i++) {
 441                 int lbus = mp_irqs[i].mpc_srcbus;
 442
 443                 for (apic = 0; apic < nr_ioapics; apic++)
 444                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 445                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 446                                 break;
 447
 448                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 449                     !mp_irqs[i].mpc_irqtype &&
 450                     (bus == lbus) &&
 451                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 452                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 453
 454                         if (!(apic || IO_APIC_IRQ(irq)))
 455                                 continue;
 456
 457                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 458                                 return irq;
 459                         /*
 460                          * Use the first all-but-pin matching entry as a
 461                          * best-guess fuzzy result for broken mptables.
 462                          */
 463                         if (best_guess < 0)
 464                                 best_guess = irq;
 465                 }
 466         }
 467         BUG_ON(best_guess >= NR_IRQS);
 468         return best_guess;
 469 }
 470
 471 /* ISA interrupts are always polarity zero edge triggered,
 472  * when listed as conforming in the MP table. */
 473
 474 #define default_ISA_trigger(idx)        (0)
 475 #define default_ISA_polarity(idx)       (0)
 476
 477 /* PCI interrupts are always polarity one level triggered,
 478  * when listed as conforming in the MP table. */
 479
 480 #define default_PCI_trigger(idx)        (1)
 481 #define default_PCI_polarity(idx)       (1)
 482
 483 static int __init MPBIOS_polarity(int idx)
 484 {
 485         int bus = mp_irqs[idx].mpc_srcbus;
 486         int polarity;
 487
 488         /*
 489          * Determine IRQ line polarity (high active or low active):
 490          */
 491         switch (mp_irqs[idx].mpc_irqflag & 3)
 492         {
 493                 case 0: /* conforms, ie. bus-type dependent polarity */
 494                 {
 495                         switch (mp_bus_id_to_type[bus])
 496                         {
 497                                 case MP_BUS_ISA: /* ISA pin */
 498                                 {
 499                                         polarity = default_ISA_polarity(idx);
 500                                         break;
 501                                 }
 502                                 case MP_BUS_PCI: /* PCI pin */
 503                                 {
 504                                         polarity = default_PCI_polarity(idx);
 505                                         break;
 506                                 }
 507                                 default:
 508                                 {
 509                                         printk(KERN_WARNING "broken BIOS!!\n");
 510                                         polarity = 1;
 511                                         break;
 512                                 }
 513                         }
 514                         break;
 515                 }
 516                 case 1: /* high active */
 517                 {
 518                         polarity = 0;
 519                         break;
 520                 }
 521                 case 2: /* reserved */
 522                 {
 523                         printk(KERN_WARNING "broken BIOS!!\n");
 524                         polarity = 1;
 525                         break;
 526                 }
 527                 case 3: /* low active */
 528                 {
 529                         polarity = 1;
 530                         break;
 531                 }
 532                 default: /* invalid */
 533                 {
 534                         printk(KERN_WARNING "broken BIOS!!\n");
 535                         polarity = 1;
 536                         break;
 537                 }
 538         }
 539         return polarity;
 540 }
 541
 542 static int MPBIOS_trigger(int idx)
 543 {
 544         int bus = mp_irqs[idx].mpc_srcbus;
 545         int trigger;
 546
 547         /*
 548          * Determine IRQ trigger mode (edge or level sensitive):
 549          */
 550         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 551         {
 552                 case 0: /* conforms, ie. bus-type dependent */
 553                 {
 554                         switch (mp_bus_id_to_type[bus])
 555                         {
 556                                 case MP_BUS_ISA: /* ISA pin */
 557                                 {
 558                                         trigger = default_ISA_trigger(idx);
 559                                         break;
 560                                 }
 561                                 case MP_BUS_PCI: /* PCI pin */
 562                                 {
 563                                         trigger = default_PCI_trigger(idx);
 564                                         break;
 565                                 }
 566                                 default:
 567                                 {
 568                                         printk(KERN_WARNING "broken BIOS!!\n");
 569                                         trigger = 1;
 570                                         break;
 571                                 }
 572                         }
 573                         break;
 574                 }
 575                 case 1: /* edge */
 576                 {
 577                         trigger = 0;
 578                         break;
 579                 }
 580                 case 2: /* reserved */
 581                 {
 582                         printk(KERN_WARNING "broken BIOS!!\n");
 583                         trigger = 1;
 584                         break;
 585                 }
 586                 case 3: /* level */
 587                 {
 588                         trigger = 1;
 589                         break;
 590                 }
 591                 default: /* invalid */
 592                 {
 593                         printk(KERN_WARNING "broken BIOS!!\n");
 594                         trigger = 0;
 595                         break;
 596                 }
 597         }
 598         return trigger;
 599 }
 600
 601 static inline int irq_polarity(int idx)
 602 {
 603         return MPBIOS_polarity(idx);
 604 }
 605
 606 static inline int irq_trigger(int idx)
 607 {
 608         return MPBIOS_trigger(idx);
 609 }
 610
 611 static int next_irq = 16;
 612
 613 /*
 614  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 615  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 616  * from ACPI, which can reach 800 in large boxen.
 617  *
 618  * Compact the sparse GSI space into a sequential IRQ series and reuse
 619  * vectors if possible.
 620  */
 621 int gsi_irq_sharing(int gsi)
 622 {
 623         int i, tries, vector;
 624
 625         BUG_ON(gsi >= NR_IRQ_VECTORS);
 626
 627         if (platform_legacy_irq(gsi))
 628                 return gsi;
 629
 630         if (gsi_2_irq[gsi] != 0xFF)
 631                 return (int)gsi_2_irq[gsi];
 632
 633         tries = NR_IRQS;
 634   try_again:
 635         vector = assign_irq_vector(gsi);
 636
 637         /*
 638          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 639          * use of vector and if found, return that IRQ.  However, we never want
 640          * to share legacy IRQs, which usually have a different trigger mode
 641          * than PCI.
 642          */
 643         for (i = 0; i < NR_IRQS; i++)
 644                 if (IO_APIC_VECTOR(i) == vector)
 645                         break;
 646         if (platform_legacy_irq(i)) {
 647                 if (--tries >= 0) {
 648                         IO_APIC_VECTOR(i) = 0;
 649                         goto try_again;
 650                 }
 651                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 652         }
 653         if (i < NR_IRQS) {
 654                 gsi_2_irq[gsi] = i;
 655                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 656                                 gsi, vector, i);
 657                 return i;
 658         }
 659
 660         i = next_irq++;
 661         BUG_ON(i >= NR_IRQS);
 662         gsi_2_irq[gsi] = i;
 663         IO_APIC_VECTOR(i) = vector;
 664         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 665                         gsi, vector, i);
 666         return i;
 667 }
 668
 669 static int pin_2_irq(int idx, int apic, int pin)
 670 {
 671         int irq, i;
 672         int bus = mp_irqs[idx].mpc_srcbus;
 673
 674         /*
 675          * Debugging check, we are in big trouble if this message pops up!
 676          */
 677         if (mp_irqs[idx].mpc_dstirq != pin)
 678                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 679
 680         switch (mp_bus_id_to_type[bus])
 681         {
 682                 case MP_BUS_ISA: /* ISA pin */
 683                 {
 684                         irq = mp_irqs[idx].mpc_srcbusirq;
 685                         break;
 686                 }
 687                 case MP_BUS_PCI: /* PCI pin */
 688                 {
 689                         /*
 690                          * PCI IRQs are mapped in order
 691                          */
 692                         i = irq = 0;
 693                         while (i < apic)
 694                                 irq += nr_ioapic_registers[i++];
 695                         irq += pin;
 696                         irq = gsi_irq_sharing(irq);
 697                         break;
 698                 }
 699                 default:
 700                 {
 701                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 702                         irq = 0;
 703                         break;
 704                 }
 705         }
 706         BUG_ON(irq >= NR_IRQS);
 707         return irq;
 708 }
 709
 710 static inline int IO_APIC_irq_trigger(int irq)
 711 {
 712         int apic, idx, pin;
 713
 714         for (apic = 0; apic < nr_ioapics; apic++) {
 715                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 716                         idx = find_irq_entry(apic,pin,mp_INT);
 717                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 718                                 return irq_trigger(idx);
 719                 }
 720         }
 721         /*
 722          * nonexistent IRQs are edge default
 723          */
 724         return 0;
 725 }
 726
 727 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 728 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 729
 730 int assign_irq_vector(int irq)
 731 {
 732         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 733         unsigned long flags;
 734         int vector;
 735
 736         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 737
 738         spin_lock_irqsave(&vector_lock, flags);
 739
 740         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
 741                 spin_unlock_irqrestore(&vector_lock, flags);
 742                 return IO_APIC_VECTOR(irq);
 743         }
 744 next:
 745         current_vector += 8;
 746         if (current_vector == IA32_SYSCALL_VECTOR)
 747                 goto next;
 748
 749         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 750                 /* If we run out of vectors on large boxen, must share them. */
 751                 offset = (offset + 1) % 8;
 752                 current_vector = FIRST_DEVICE_VECTOR + offset;
 753         }
 754
 755         vector = current_vector;
 756         vector_irq[vector] = irq;
 757         if (irq != AUTO_ASSIGN)
 758                 IO_APIC_VECTOR(irq) = vector;
 759
 760         spin_unlock_irqrestore(&vector_lock, flags);
 761
 762         return vector;
 763 }
 764
 765 extern void (*interrupt[NR_IRQS])(void);
 766 static struct hw_interrupt_type ioapic_level_type;
 767 static struct hw_interrupt_type ioapic_edge_type;
 768
 769 #define IOAPIC_AUTO     -1
 770 #define IOAPIC_EDGE     0
 771 #define IOAPIC_LEVEL    1
 772
 773 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 774 {
 775         unsigned idx;
 776
 777         idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
 778
 779         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 780                         trigger == IOAPIC_LEVEL)
 781                 irq_desc[idx].chip = &ioapic_level_type;
 782         else
 783                 irq_desc[idx].chip = &ioapic_edge_type;
 784         set_intr_gate(vector, interrupt[idx]);
 785 }
 786
 787 static void __init setup_IO_APIC_irqs(void)
 788 {
 789         struct IO_APIC_route_entry entry;
 790         int apic, pin, idx, irq, first_notcon = 1, vector;
 791         unsigned long flags;
 792
 793         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 794
 795         for (apic = 0; apic < nr_ioapics; apic++) {
 796         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 797
 798                 /*
 799                  * add it to the IO-APIC irq-routing table:
 800                  */
 801                 memset(&entry,0,sizeof(entry));
 802
 803                 entry.delivery_mode = INT_DELIVERY_MODE;
 804                 entry.dest_mode = INT_DEST_MODE;
 805                 entry.mask = 0;                         /* enable IRQ */
 806                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 807
 808                 idx = find_irq_entry(apic,pin,mp_INT);
 809                 if (idx == -1) {
 810                         if (first_notcon) {
 811                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 812                                 first_notcon = 0;
 813                         } else
 814                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 815                         continue;
 816                 }
 817
 818                 entry.trigger = irq_trigger(idx);
 819                 entry.polarity = irq_polarity(idx);
 820
 821                 if (irq_trigger(idx)) {
 822                         entry.trigger = 1;
 823                         entry.mask = 1;
 824                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 825                 }
 826
 827                 irq = pin_2_irq(idx, apic, pin);
 828                 add_pin_to_irq(irq, apic, pin);
 829
 830                 if (!apic && !IO_APIC_IRQ(irq))
 831                         continue;
 832
 833                 if (IO_APIC_IRQ(irq)) {
 834                         vector = assign_irq_vector(irq);
 835                         entry.vector = vector;
 836
 837                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 838                         if (!apic && (irq < 16))
 839                                 disable_8259A_irq(irq);
 840                 }
 841                 spin_lock_irqsave(&ioapic_lock, flags);
 842                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 843                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 844                 set_native_irq_info(irq, TARGET_CPUS);
 845                 spin_unlock_irqrestore(&ioapic_lock, flags);
 846         }
 847         }
 848
 849         if (!first_notcon)
 850                 apic_printk(APIC_VERBOSE," not connected.\n");
 851 }
 852
 853 /*
 854  * Set up the 8259A-master output pin as broadcast to all
 855  * CPUs.
 856  */
 857 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 858 {
 859         struct IO_APIC_route_entry entry;
 860         unsigned long flags;
 861
 862         memset(&entry,0,sizeof(entry));
 863
 864         disable_8259A_irq(0);
 865
 866         /* mask LVT0 */
 867         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 868
 869         /*
 870          * We use logical delivery to get the timer IRQ
 871          * to the first CPU.
 872          */
 873         entry.dest_mode = INT_DEST_MODE;
 874         entry.mask = 0;                                 /* unmask IRQ now */
 875         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 876         entry.delivery_mode = INT_DELIVERY_MODE;
 877         entry.polarity = 0;
 878         entry.trigger = 0;
 879         entry.vector = vector;
 880
 881         /*
 882          * The timer IRQ doesn't have to know that behind the
 883          * scene we have a 8259A-master in AEOI mode ...
 884          */
 885         irq_desc[0].chip = &ioapic_edge_type;
 886
 887         /*
 888          * Add it to the IO-APIC irq-routing table:
 889          */
 890         spin_lock_irqsave(&ioapic_lock, flags);
 891         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 892         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 893         spin_unlock_irqrestore(&ioapic_lock, flags);
 894
 895         enable_8259A_irq(0);
 896 }
 897
 898 void __init UNEXPECTED_IO_APIC(void)
 899 {
 900 }
 901
 902 void __apicdebuginit print_IO_APIC(void)
 903 {
 904         int apic, i;
 905         union IO_APIC_reg_00 reg_00;
 906         union IO_APIC_reg_01 reg_01;
 907         union IO_APIC_reg_02 reg_02;
 908         unsigned long flags;
 909
 910         if (apic_verbosity == APIC_QUIET)
 911                 return;
 912
 913         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 914         for (i = 0; i < nr_ioapics; i++)
 915                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 916                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 917
 918         /*
 919          * We are a bit conservative about what we expect.  We have to
 920          * know about every hardware change ASAP.
 921          */
 922         printk(KERN_INFO "testing the IO APIC.......................\n");
 923
 924         for (apic = 0; apic < nr_ioapics; apic++) {
 925
 926         spin_lock_irqsave(&ioapic_lock, flags);
 927         reg_00.raw = io_apic_read(apic, 0);
 928         reg_01.raw = io_apic_read(apic, 1);
 929         if (reg_01.bits.version >= 0x10)
 930                 reg_02.raw = io_apic_read(apic, 2);
 931         spin_unlock_irqrestore(&ioapic_lock, flags);
 932
 933         printk("\n");
 934         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 935         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 936         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 937         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 938                 UNEXPECTED_IO_APIC();
 939
 940         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 941         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 942         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 943                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 944                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 945                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 946                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 947                 (reg_01.bits.entries != 0x2E) &&
 948                 (reg_01.bits.entries != 0x3F) &&
 949                 (reg_01.bits.entries != 0x03)
 950         )
 951                 UNEXPECTED_IO_APIC();
 952
 953         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 954         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 955         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 956                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 957                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 958                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 959                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 960                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 961         )
 962                 UNEXPECTED_IO_APIC();
 963         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 964                 UNEXPECTED_IO_APIC();
 965
 966         if (reg_01.bits.version >= 0x10) {
 967                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 968                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 969                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 970                         UNEXPECTED_IO_APIC();
 971         }
 972
 973         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 974
 975         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 976                           " Stat Dest Deli Vect:   \n");
 977
 978         for (i = 0; i <= reg_01.bits.entries; i++) {
 979                 struct IO_APIC_route_entry entry;
 980
 981                 spin_lock_irqsave(&ioapic_lock, flags);
 982                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 983                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 984                 spin_unlock_irqrestore(&ioapic_lock, flags);
 985
 986                 printk(KERN_DEBUG " %02x %03X %02X  ",
 987                         i,
 988                         entry.dest.logical.logical_dest,
 989                         entry.dest.physical.physical_dest
 990                 );
 991
 992                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 993                         entry.mask,
 994                         entry.trigger,
 995                         entry.irr,
 996                         entry.polarity,
 997                         entry.delivery_status,
 998                         entry.dest_mode,
 999                         entry.delivery_mode,
1000                         entry.vector
1001                 );
1002         }
1003         }
1004         if (use_pci_vector())
1005                 printk(KERN_INFO "Using vector-based indexing\n");
1006         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1007         for (i = 0; i < NR_IRQS; i++) {
1008                 struct irq_pin_list *entry = irq_2_pin + i;
1009                 if (entry->pin < 0)
1010                         continue;
1011                 if (use_pci_vector() && !platform_legacy_irq(i))
1012                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1013                 else
1014                         printk(KERN_DEBUG "IRQ%d ", i);
1015                 for (;;) {
1016                         printk("-> %d:%d", entry->apic, entry->pin);
1017                         if (!entry->next)
1018                                 break;
1019                         entry = irq_2_pin + entry->next;
1020                 }
1021                 printk("\n");
1022         }
1023
1024         printk(KERN_INFO ".................................... done.\n");
1025
1026         return;
1027 }
1028
1029 #if 0
1030
1031 static __apicdebuginit void print_APIC_bitfield (int base)
1032 {
1033         unsigned int v;
1034         int i, j;
1035
1036         if (apic_verbosity == APIC_QUIET)
1037                 return;
1038
1039         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1040         for (i = 0; i < 8; i++) {
1041                 v = apic_read(base + i*0x10);
1042                 for (j = 0; j < 32; j++) {
1043                         if (v & (1<<j))
1044                                 printk("1");
1045                         else
1046                                 printk("0");
1047                 }
1048                 printk("\n");
1049         }
1050 }
1051
1052 void __apicdebuginit print_local_APIC(void * dummy)
1053 {
1054         unsigned int v, ver, maxlvt;
1055
1056         if (apic_verbosity == APIC_QUIET)
1057                 return;
1058
1059         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1060                 smp_processor_id(), hard_smp_processor_id());
1061         v = apic_read(APIC_ID);
1062         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1063         v = apic_read(APIC_LVR);
1064         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1065         ver = GET_APIC_VERSION(v);
1066         maxlvt = get_maxlvt();
1067
1068         v = apic_read(APIC_TASKPRI);
1069         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1070
1071         v = apic_read(APIC_ARBPRI);
1072         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1073                 v & APIC_ARBPRI_MASK);
1074         v = apic_read(APIC_PROCPRI);
1075         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1076
1077         v = apic_read(APIC_EOI);
1078         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1079         v = apic_read(APIC_RRR);
1080         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1081         v = apic_read(APIC_LDR);
1082         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1083         v = apic_read(APIC_DFR);
1084         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1085         v = apic_read(APIC_SPIV);
1086         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1087
1088         printk(KERN_DEBUG "... APIC ISR field:\n");
1089         print_APIC_bitfield(APIC_ISR);
1090         printk(KERN_DEBUG "... APIC TMR field:\n");
1091         print_APIC_bitfield(APIC_TMR);
1092         printk(KERN_DEBUG "... APIC IRR field:\n");
1093         print_APIC_bitfield(APIC_IRR);
1094
1095         v = apic_read(APIC_ESR);
1096         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1097
1098         v = apic_read(APIC_ICR);
1099         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1100         v = apic_read(APIC_ICR2);
1101         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1102
1103         v = apic_read(APIC_LVTT);
1104         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1105
1106         if (maxlvt > 3) {                       /* PC is LVT#4. */
1107                 v = apic_read(APIC_LVTPC);
1108                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1109         }
1110         v = apic_read(APIC_LVT0);
1111         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1112         v = apic_read(APIC_LVT1);
1113         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1114
1115         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1116                 v = apic_read(APIC_LVTERR);
1117                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1118         }
1119
1120         v = apic_read(APIC_TMICT);
1121         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1122         v = apic_read(APIC_TMCCT);
1123         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1124         v = apic_read(APIC_TDCR);
1125         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1126         printk("\n");
1127 }
1128
1129 void print_all_local_APICs (void)
1130 {
1131         on_each_cpu(print_local_APIC, NULL, 1, 1);
1132 }
1133
1134 void __apicdebuginit print_PIC(void)
1135 {
1136         unsigned int v;
1137         unsigned long flags;
1138
1139         if (apic_verbosity == APIC_QUIET)
1140                 return;
1141
1142         printk(KERN_DEBUG "\nprinting PIC contents\n");
1143
1144         spin_lock_irqsave(&i8259A_lock, flags);
1145
1146         v = inb(0xa1) << 8 | inb(0x21);
1147         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1148
1149         v = inb(0xa0) << 8 | inb(0x20);
1150         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1151
1152         outb(0x0b,0xa0);
1153         outb(0x0b,0x20);
1154         v = inb(0xa0) << 8 | inb(0x20);
1155         outb(0x0a,0xa0);
1156         outb(0x0a,0x20);
1157
1158         spin_unlock_irqrestore(&i8259A_lock, flags);
1159
1160         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1161
1162         v = inb(0x4d1) << 8 | inb(0x4d0);
1163         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1164 }
1165
1166 #endif  /*  0  */
1167
1168 static void __init enable_IO_APIC(void)
1169 {
1170         union IO_APIC_reg_01 reg_01;
1171         int i8259_apic, i8259_pin;
1172         int i, apic;
1173         unsigned long flags;
1174
1175         for (i = 0; i < PIN_MAP_SIZE; i++) {
1176                 irq_2_pin[i].pin = -1;
1177                 irq_2_pin[i].next = 0;
1178         }
1179
1180         /*
1181          * The number of IO-APIC IRQ registers (== #pins):
1182          */
1183         for (apic = 0; apic < nr_ioapics; apic++) {
1184                 spin_lock_irqsave(&ioapic_lock, flags);
1185                 reg_01.raw = io_apic_read(apic, 1);
1186                 spin_unlock_irqrestore(&ioapic_lock, flags);
1187                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1188         }
1189         for(apic = 0; apic < nr_ioapics; apic++) {
1190                 int pin;
1191                 /* See if any of the pins is in ExtINT mode */
1192                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1193                         struct IO_APIC_route_entry entry;
1194                         spin_lock_irqsave(&ioapic_lock, flags);
1195                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1196                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1197                         spin_unlock_irqrestore(&ioapic_lock, flags);
1198
1199
1200                         /* If the interrupt line is enabled and in ExtInt mode
1201                          * I have found the pin where the i8259 is connected.
1202                          */
1203                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1204                                 ioapic_i8259.apic = apic;
1205                                 ioapic_i8259.pin  = pin;
1206                                 goto found_i8259;
1207                         }
1208                 }
1209         }
1210  found_i8259:
1211         /* Look to see what if the MP table has reported the ExtINT */
1212         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1213         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1214         /* Trust the MP table if nothing is setup in the hardware */
1215         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1216                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1217                 ioapic_i8259.pin  = i8259_pin;
1218                 ioapic_i8259.apic = i8259_apic;
1219         }
1220         /* Complain if the MP table and the hardware disagree */
1221         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1222                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1223         {
1224                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1225         }
1226
1227         /*
1228          * Do not trust the IO-APIC being empty at bootup
1229          */
1230         clear_IO_APIC();
1231 }
1232
1233 /*
1234  * Not an __init, needed by the reboot code
1235  */
1236 void disable_IO_APIC(void)
1237 {
1238         /*
1239          * Clear the IO-APIC before rebooting:
1240          */
1241         clear_IO_APIC();
1242
1243         /*
1244          * If the i8259 is routed through an IOAPIC
1245          * Put that IOAPIC in virtual wire mode
1246          * so legacy interrupts can be delivered.
1247          */
1248         if (ioapic_i8259.pin != -1) {
1249                 struct IO_APIC_route_entry entry;
1250                 unsigned long flags;
1251
1252                 memset(&entry, 0, sizeof(entry));
1253                 entry.mask            = 0; /* Enabled */
1254                 entry.trigger         = 0; /* Edge */
1255                 entry.irr             = 0;
1256                 entry.polarity        = 0; /* High */
1257                 entry.delivery_status = 0;
1258                 entry.dest_mode       = 0; /* Physical */
1259                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1260                 entry.vector          = 0;
1261                 entry.dest.physical.physical_dest =
1262                                         GET_APIC_ID(apic_read(APIC_ID));
1263
1264                 /*
1265                  * Add it to the IO-APIC irq-routing table:
1266                  */
1267                 spin_lock_irqsave(&ioapic_lock, flags);
1268                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1269                         *(((int *)&entry)+1));
1270                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1271                         *(((int *)&entry)+0));
1272                 spin_unlock_irqrestore(&ioapic_lock, flags);
1273         }
1274
1275         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1276 }
1277
1278 /*
1279  * function to set the IO-APIC physical IDs based on the
1280  * values stored in the MPC table.
1281  *
1282  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1283  */
1284
1285 static void __init setup_ioapic_ids_from_mpc (void)
1286 {
1287         union IO_APIC_reg_00 reg_00;
1288         int apic;
1289         int i;
1290         unsigned char old_id;
1291         unsigned long flags;
1292
1293         /*
1294          * Set the IOAPIC ID to the value stored in the MPC table.
1295          */
1296         for (apic = 0; apic < nr_ioapics; apic++) {
1297
1298                 /* Read the register 0 value */
1299                 spin_lock_irqsave(&ioapic_lock, flags);
1300                 reg_00.raw = io_apic_read(apic, 0);
1301                 spin_unlock_irqrestore(&ioapic_lock, flags);
1302
1303                 old_id = mp_ioapics[apic].mpc_apicid;
1304
1305
1306                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1307
1308
1309                 /*
1310                  * We need to adjust the IRQ routing table
1311                  * if the ID changed.
1312                  */
1313                 if (old_id != mp_ioapics[apic].mpc_apicid)
1314                         for (i = 0; i < mp_irq_entries; i++)
1315                                 if (mp_irqs[i].mpc_dstapic == old_id)
1316                                         mp_irqs[i].mpc_dstapic
1317                                                 = mp_ioapics[apic].mpc_apicid;
1318
1319                 /*
1320                  * Read the right value from the MPC table and
1321                  * write it into the ID register.
1322                  */
1323                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1324                                 mp_ioapics[apic].mpc_apicid);
1325
1326                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1327                 spin_lock_irqsave(&ioapic_lock, flags);
1328                 io_apic_write(apic, 0, reg_00.raw);
1329                 spin_unlock_irqrestore(&ioapic_lock, flags);
1330
1331                 /*
1332                  * Sanity check
1333                  */
1334                 spin_lock_irqsave(&ioapic_lock, flags);
1335                 reg_00.raw = io_apic_read(apic, 0);
1336                 spin_unlock_irqrestore(&ioapic_lock, flags);
1337                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1338                         printk("could not set ID!\n");
1339                 else
1340                         apic_printk(APIC_VERBOSE," ok.\n");
1341         }
1342 }
1343
1344 /*
1345  * There is a nasty bug in some older SMP boards, their mptable lies
1346  * about the timer IRQ. We do the following to work around the situation:
1347  *
1348  *      - timer IRQ defaults to IO-APIC IRQ
1349  *      - if this function detects that timer IRQs are defunct, then we fall
1350  *        back to ISA timer IRQs
1351  */
1352 static int __init timer_irq_works(void)
1353 {
1354         unsigned long t1 = jiffies;
1355
1356         local_irq_enable();
1357         /* Let ten ticks pass... */
1358         mdelay((10 * 1000) / HZ);
1359
1360         /*
1361          * Expect a few ticks at least, to be sure some possible
1362          * glue logic does not lock up after one or two first
1363          * ticks in a non-ExtINT mode.  Also the local APIC
1364          * might have cached one ExtINT interrupt.  Finally, at
1365          * least one tick may be lost due to delays.
1366          */
1367
1368         /* jiffies wrap? */
1369         if (jiffies - t1 > 4)
1370                 return 1;
1371         return 0;
1372 }
1373
1374 /*
1375  * In the SMP+IOAPIC case it might happen that there are an unspecified
1376  * number of pending IRQ events unhandled. These cases are very rare,
1377  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1378  * better to do it this way as thus we do not have to be aware of
1379  * 'pending' interrupts in the IRQ path, except at this point.
1380  */
1381 /*
1382  * Edge triggered needs to resend any interrupt
1383  * that was delayed but this is now handled in the device
1384  * independent code.
1385  */
1386
1387 /*
1388  * Starting up a edge-triggered IO-APIC interrupt is
1389  * nasty - we need to make sure that we get the edge.
1390  * If it is already asserted for some reason, we need
1391  * return 1 to indicate that is was pending.
1392  *
1393  * This is not complete - we should be able to fake
1394  * an edge even if it isn't on the 8259A...
1395  */
1396
1397 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1398 {
1399         int was_pending = 0;
1400         unsigned long flags;
1401
1402         spin_lock_irqsave(&ioapic_lock, flags);
1403         if (irq < 16) {
1404                 disable_8259A_irq(irq);
1405                 if (i8259A_irq_pending(irq))
1406                         was_pending = 1;
1407         }
1408         __unmask_IO_APIC_irq(irq);
1409         spin_unlock_irqrestore(&ioapic_lock, flags);
1410
1411         return was_pending;
1412 }
1413
1414 /*
1415  * Once we have recorded IRQ_PENDING already, we can mask the
1416  * interrupt for real. This prevents IRQ storms from unhandled
1417  * devices.
1418  */
1419 static void ack_edge_ioapic_irq(unsigned int irq)
1420 {
1421         move_irq(irq);
1422         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1423                                         == (IRQ_PENDING | IRQ_DISABLED))
1424                 mask_IO_APIC_irq(irq);
1425         ack_APIC_irq();
1426 }
1427
1428 /*
1429  * Level triggered interrupts can just be masked,
1430  * and shutting down and starting up the interrupt
1431  * is the same as enabling and disabling them -- except
1432  * with a startup need to return a "was pending" value.
1433  *
1434  * Level triggered interrupts are special because we
1435  * do not touch any IO-APIC register while handling
1436  * them. We ack the APIC in the end-IRQ handler, not
1437  * in the start-IRQ-handler. Protection against reentrance
1438  * from the same interrupt is still provided, both by the
1439  * generic IRQ layer and by the fact that an unacked local
1440  * APIC does not accept IRQs.
1441  */
1442 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1443 {
1444         unmask_IO_APIC_irq(irq);
1445
1446         return 0; /* don't check for pending */
1447 }
1448
1449 static void end_level_ioapic_irq (unsigned int irq)
1450 {
1451         move_irq(irq);
1452         ack_APIC_irq();
1453 }
1454
1455 #ifdef CONFIG_PCI_MSI
1456 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1457 {
1458         int irq = vector_to_irq(vector);
1459
1460         return startup_edge_ioapic_irq(irq);
1461 }
1462
1463 static void ack_edge_ioapic_vector(unsigned int vector)
1464 {
1465         int irq = vector_to_irq(vector);
1466
1467         move_native_irq(vector);
1468         ack_edge_ioapic_irq(irq);
1469 }
1470
1471 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1472 {
1473         int irq = vector_to_irq(vector);
1474
1475         return startup_level_ioapic_irq (irq);
1476 }
1477
1478 static void end_level_ioapic_vector (unsigned int vector)
1479 {
1480         int irq = vector_to_irq(vector);
1481
1482         move_native_irq(vector);
1483         end_level_ioapic_irq(irq);
1484 }
1485
1486 static void mask_IO_APIC_vector (unsigned int vector)
1487 {
1488         int irq = vector_to_irq(vector);
1489
1490         mask_IO_APIC_irq(irq);
1491 }
1492
1493 static void unmask_IO_APIC_vector (unsigned int vector)
1494 {
1495         int irq = vector_to_irq(vector);
1496
1497         unmask_IO_APIC_irq(irq);
1498 }
1499
1500 #ifdef CONFIG_SMP
1501 static void set_ioapic_affinity_vector (unsigned int vector,
1502                                         cpumask_t cpu_mask)
1503 {
1504         int irq = vector_to_irq(vector);
1505
1506         set_native_irq_info(vector, cpu_mask);
1507         set_ioapic_affinity_irq(irq, cpu_mask);
1508 }
1509 #endif // CONFIG_SMP
1510 #endif // CONFIG_PCI_MSI
1511
1512 static int ioapic_retrigger(unsigned int irq)
1513 {
1514         send_IPI_self(IO_APIC_VECTOR(irq));
1515
1516         return 1;
1517 }
1518
1519 /*
1520  * Level and edge triggered IO-APIC interrupts need different handling,
1521  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1522  * handled with the level-triggered descriptor, but that one has slightly
1523  * more overhead. Level-triggered interrupts cannot be handled with the
1524  * edge-triggered handler, without risking IRQ storms and other ugly
1525  * races.
1526  */
1527
1528 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1529         .typename = "IO-APIC-edge",
1530         .startup        = startup_edge_ioapic,
1531         .shutdown       = shutdown_edge_ioapic,
1532         .enable         = enable_edge_ioapic,
1533         .disable        = disable_edge_ioapic,
1534         .ack            = ack_edge_ioapic,
1535         .end            = end_edge_ioapic,
1536 #ifdef CONFIG_SMP
1537         .set_affinity = set_ioapic_affinity,
1538 #endif
1539         .retrigger      = ioapic_retrigger,
1540 };
1541
1542 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1543         .typename = "IO-APIC-level",
1544         .startup        = startup_level_ioapic,
1545         .shutdown       = shutdown_level_ioapic,
1546         .enable         = enable_level_ioapic,
1547         .disable        = disable_level_ioapic,
1548         .ack            = mask_and_ack_level_ioapic,
1549         .end            = end_level_ioapic,
1550 #ifdef CONFIG_SMP
1551         .set_affinity = set_ioapic_affinity,
1552 #endif
1553         .retrigger      = ioapic_retrigger,
1554 };
1555
1556 static inline void init_IO_APIC_traps(void)
1557 {
1558         int irq;
1559
1560         /*
1561          * NOTE! The local APIC isn't very good at handling
1562          * multiple interrupts at the same interrupt level.
1563          * As the interrupt level is determined by taking the
1564          * vector number and shifting that right by 4, we
1565          * want to spread these out a bit so that they don't
1566          * all fall in the same interrupt level.
1567          *
1568          * Also, we've got to be careful not to trash gate
1569          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1570          */
1571         for (irq = 0; irq < NR_IRQS ; irq++) {
1572                 int tmp = irq;
1573                 if (use_pci_vector()) {
1574                         if (!platform_legacy_irq(tmp))
1575                                 if ((tmp = vector_to_irq(tmp)) == -1)
1576                                         continue;
1577                 }
1578                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1579                         /*
1580                          * Hmm.. We don't have an entry for this,
1581                          * so default to an old-fashioned 8259
1582                          * interrupt if we can..
1583                          */
1584                         if (irq < 16)
1585                                 make_8259A_irq(irq);
1586                         else
1587                                 /* Strange. Oh, well.. */
1588                                 irq_desc[irq].chip = &no_irq_type;
1589                 }
1590         }
1591 }
1592
1593 static void enable_lapic_irq (unsigned int irq)
1594 {
1595         unsigned long v;
1596
1597         v = apic_read(APIC_LVT0);
1598         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1599 }
1600
1601 static void disable_lapic_irq (unsigned int irq)
1602 {
1603         unsigned long v;
1604
1605         v = apic_read(APIC_LVT0);
1606         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1607 }
1608
1609 static void ack_lapic_irq (unsigned int irq)
1610 {
1611         ack_APIC_irq();
1612 }
1613
1614 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1615
1616 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1617         .typename = "local-APIC-edge",
1618         .startup = NULL, /* startup_irq() not used for IRQ0 */
1619         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1620         .enable = enable_lapic_irq,
1621         .disable = disable_lapic_irq,
1622         .ack = ack_lapic_irq,
1623         .end = end_lapic_irq,
1624 };
1625
1626 static void setup_nmi (void)
1627 {
1628         /*
1629          * Dirty trick to enable the NMI watchdog ...
1630          * We put the 8259A master into AEOI mode and
1631          * unmask on all local APICs LVT0 as NMI.
1632          *
1633          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1634          * is from Maciej W. Rozycki - so we do not have to EOI from
1635          * the NMI handler or the timer interrupt.
1636          */
1637         printk(KERN_INFO "activating NMI Watchdog ...");
1638
1639         enable_NMI_through_LVT0(NULL);
1640
1641         printk(" done.\n");
1642 }
1643
1644 /*
1645  * This looks a bit hackish but it's about the only one way of sending
1646  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1647  * not support the ExtINT mode, unfortunately.  We need to send these
1648  * cycles as some i82489DX-based boards have glue logic that keeps the
1649  * 8259A interrupt line asserted until INTA.  --macro
1650  */
1651 static inline void unlock_ExtINT_logic(void)
1652 {
1653         int apic, pin, i;
1654         struct IO_APIC_route_entry entry0, entry1;
1655         unsigned char save_control, save_freq_select;
1656         unsigned long flags;
1657
1658         pin  = find_isa_irq_pin(8, mp_INT);
1659         apic = find_isa_irq_apic(8, mp_INT);
1660         if (pin == -1)
1661                 return;
1662
1663         spin_lock_irqsave(&ioapic_lock, flags);
1664         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1665         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1666         spin_unlock_irqrestore(&ioapic_lock, flags);
1667         clear_IO_APIC_pin(apic, pin);
1668
1669         memset(&entry1, 0, sizeof(entry1));
1670
1671         entry1.dest_mode = 0;                   /* physical delivery */
1672         entry1.mask = 0;                        /* unmask IRQ now */
1673         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1674         entry1.delivery_mode = dest_ExtINT;
1675         entry1.polarity = entry0.polarity;
1676         entry1.trigger = 0;
1677         entry1.vector = 0;
1678
1679         spin_lock_irqsave(&ioapic_lock, flags);
1680         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1681         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1682         spin_unlock_irqrestore(&ioapic_lock, flags);
1683
1684         save_control = CMOS_READ(RTC_CONTROL);
1685         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1686         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1687                    RTC_FREQ_SELECT);
1688         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1689
1690         i = 100;
1691         while (i-- > 0) {
1692                 mdelay(10);
1693                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1694                         i -= 10;
1695         }
1696
1697         CMOS_WRITE(save_control, RTC_CONTROL);
1698         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1699         clear_IO_APIC_pin(apic, pin);
1700
1701         spin_lock_irqsave(&ioapic_lock, flags);
1702         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1703         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1704         spin_unlock_irqrestore(&ioapic_lock, flags);
1705 }
1706
1707 int timer_uses_ioapic_pin_0;
1708
1709 /*
1710  * This code may look a bit paranoid, but it's supposed to cooperate with
1711  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1712  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1713  * fanatically on his truly buggy board.
1714  *
1715  * FIXME: really need to revamp this for modern platforms only.
1716  */
1717 static inline void check_timer(void)
1718 {
1719         int apic1, pin1, apic2, pin2;
1720         int vector;
1721
1722         /*
1723          * get/set the timer IRQ vector:
1724          */
1725         disable_8259A_irq(0);
1726         vector = assign_irq_vector(0);
1727         set_intr_gate(vector, interrupt[0]);
1728
1729         /*
1730          * Subtle, code in do_timer_interrupt() expects an AEOI
1731          * mode for the 8259A whenever interrupts are routed
1732          * through I/O APICs.  Also IRQ0 has to be enabled in
1733          * the 8259A which implies the virtual wire has to be
1734          * disabled in the local APIC.
1735          */
1736         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1737         init_8259A(1);
1738         if (timer_over_8254 > 0)
1739                 enable_8259A_irq(0);
1740
1741         pin1  = find_isa_irq_pin(0, mp_INT);
1742         apic1 = find_isa_irq_apic(0, mp_INT);
1743         pin2  = ioapic_i8259.pin;
1744         apic2 = ioapic_i8259.apic;
1745
1746         if (pin1 == 0)
1747                 timer_uses_ioapic_pin_0 = 1;
1748
1749         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1750                 vector, apic1, pin1, apic2, pin2);
1751
1752         if (pin1 != -1) {
1753                 /*
1754                  * Ok, does IRQ0 through the IOAPIC work?
1755                  */
1756                 unmask_IO_APIC_irq(0);
1757                 if (!no_timer_check && timer_irq_works()) {
1758                         nmi_watchdog_default();
1759                         if (nmi_watchdog == NMI_IO_APIC) {
1760                                 disable_8259A_irq(0);
1761                                 setup_nmi();
1762                                 enable_8259A_irq(0);
1763                         }
1764                         if (disable_timer_pin_1 > 0)
1765                                 clear_IO_APIC_pin(0, pin1);
1766                         return;
1767                 }
1768                 clear_IO_APIC_pin(apic1, pin1);
1769                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1770                                 "connected to IO-APIC\n");
1771         }
1772
1773         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1774                                 "through the 8259A ... ");
1775         if (pin2 != -1) {
1776                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1777                         apic2, pin2);
1778                 /*
1779                  * legacy devices should be connected to IO APIC #0
1780                  */
1781                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1782                 if (timer_irq_works()) {
1783                         apic_printk(APIC_VERBOSE," works.\n");
1784                         nmi_watchdog_default();
1785                         if (nmi_watchdog == NMI_IO_APIC) {
1786                                 setup_nmi();
1787                         }
1788                         return;
1789                 }
1790                 /*
1791                  * Cleanup, just in case ...
1792                  */
1793                 clear_IO_APIC_pin(apic2, pin2);
1794         }
1795         apic_printk(APIC_VERBOSE," failed.\n");
1796
1797         if (nmi_watchdog == NMI_IO_APIC) {
1798                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1799                 nmi_watchdog = 0;
1800         }
1801
1802         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1803
1804         disable_8259A_irq(0);
1805         irq_desc[0].chip = &lapic_irq_type;
1806         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1807         enable_8259A_irq(0);
1808
1809         if (timer_irq_works()) {
1810                 apic_printk(APIC_VERBOSE," works.\n");
1811                 return;
1812         }
1813         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1814         apic_printk(APIC_VERBOSE," failed.\n");
1815
1816         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1817
1818         init_8259A(0);
1819         make_8259A_irq(0);
1820         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1821
1822         unlock_ExtINT_logic();
1823
1824         if (timer_irq_works()) {
1825                 apic_printk(APIC_VERBOSE," works.\n");
1826                 return;
1827         }
1828         apic_printk(APIC_VERBOSE," failed :(.\n");
1829         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1830 }
1831
1832 static int __init notimercheck(char *s)
1833 {
1834         no_timer_check = 1;
1835         return 1;
1836 }
1837 __setup("no_timer_check", notimercheck);
1838
1839 /*
1840  *
1841  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1842  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1843  *   Linux doesn't really care, as it's not actually used
1844  *   for any interrupt handling anyway.
1845  */
1846 #define PIC_IRQS        (1<<2)
1847
1848 void __init setup_IO_APIC(void)
1849 {
1850         enable_IO_APIC();
1851
1852         if (acpi_ioapic)
1853                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1854         else
1855                 io_apic_irqs = ~PIC_IRQS;
1856
1857         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1858
1859         /*
1860          * Set up the IO-APIC IRQ routing table.
1861          */
1862         if (!acpi_ioapic)
1863                 setup_ioapic_ids_from_mpc();
1864         sync_Arb_IDs();
1865         setup_IO_APIC_irqs();
1866         init_IO_APIC_traps();
1867         check_timer();
1868         if (!acpi_ioapic)
1869                 print_IO_APIC();
1870 }
1871
1872 struct sysfs_ioapic_data {
1873         struct sys_device dev;
1874         struct IO_APIC_route_entry entry[0];
1875 };
1876 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1877
1878 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1879 {
1880         struct IO_APIC_route_entry *entry;
1881         struct sysfs_ioapic_data *data;
1882         unsigned long flags;
1883         int i;
1884
1885         data = container_of(dev, struct sysfs_ioapic_data, dev);
1886         entry = data->entry;
1887         spin_lock_irqsave(&ioapic_lock, flags);
1888         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1889                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1890                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1891         }
1892         spin_unlock_irqrestore(&ioapic_lock, flags);
1893
1894         return 0;
1895 }
1896
1897 static int ioapic_resume(struct sys_device *dev)
1898 {
1899         struct IO_APIC_route_entry *entry;
1900         struct sysfs_ioapic_data *data;
1901         unsigned long flags;
1902         union IO_APIC_reg_00 reg_00;
1903         int i;
1904
1905         data = container_of(dev, struct sysfs_ioapic_data, dev);
1906         entry = data->entry;
1907
1908         spin_lock_irqsave(&ioapic_lock, flags);
1909         reg_00.raw = io_apic_read(dev->id, 0);
1910         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1911                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1912                 io_apic_write(dev->id, 0, reg_00.raw);
1913         }
1914         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1915                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1916                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1917         }
1918         spin_unlock_irqrestore(&ioapic_lock, flags);
1919
1920         return 0;
1921 }
1922
1923 static struct sysdev_class ioapic_sysdev_class = {
1924         set_kset_name("ioapic"),
1925         .suspend = ioapic_suspend,
1926         .resume = ioapic_resume,
1927 };
1928
1929 static int __init ioapic_init_sysfs(void)
1930 {
1931         struct sys_device * dev;
1932         int i, size, error = 0;
1933
1934         error = sysdev_class_register(&ioapic_sysdev_class);
1935         if (error)
1936                 return error;
1937
1938         for (i = 0; i < nr_ioapics; i++ ) {
1939                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1940                         * sizeof(struct IO_APIC_route_entry);
1941                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1942                 if (!mp_ioapic_data[i]) {
1943                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1944                         continue;
1945                 }
1946                 memset(mp_ioapic_data[i], 0, size);
1947                 dev = &mp_ioapic_data[i]->dev;
1948                 dev->id = i;
1949                 dev->cls = &ioapic_sysdev_class;
1950                 error = sysdev_register(dev);
1951                 if (error) {
1952                         kfree(mp_ioapic_data[i]);
1953                         mp_ioapic_data[i] = NULL;
1954                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1955                         continue;
1956                 }
1957         }
1958
1959         return 0;
1960 }
1961
1962 device_initcall(ioapic_init_sysfs);
1963
1964 /* --------------------------------------------------------------------------
1965                           ACPI-based IOAPIC Configuration
1966    -------------------------------------------------------------------------- */
1967
1968 #ifdef CONFIG_ACPI
1969
1970 #define IO_APIC_MAX_ID          0xFE
1971
1972 int __init io_apic_get_version (int ioapic)
1973 {
1974         union IO_APIC_reg_01    reg_01;
1975         unsigned long flags;
1976
1977         spin_lock_irqsave(&ioapic_lock, flags);
1978         reg_01.raw = io_apic_read(ioapic, 1);
1979         spin_unlock_irqrestore(&ioapic_lock, flags);
1980
1981         return reg_01.bits.version;
1982 }
1983
1984
1985 int __init io_apic_get_redir_entries (int ioapic)
1986 {
1987         union IO_APIC_reg_01    reg_01;
1988         unsigned long flags;
1989
1990         spin_lock_irqsave(&ioapic_lock, flags);
1991         reg_01.raw = io_apic_read(ioapic, 1);
1992         spin_unlock_irqrestore(&ioapic_lock, flags);
1993
1994         return reg_01.bits.entries;
1995 }
1996
1997
1998 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1999 {
2000         struct IO_APIC_route_entry entry;
2001         unsigned long flags;
2002
2003         if (!IO_APIC_IRQ(irq)) {
2004                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2005                         ioapic);
2006                 return -EINVAL;
2007         }
2008
2009         /*
2010          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2011          * Note that we mask (disable) IRQs now -- these get enabled when the
2012          * corresponding device driver registers for this IRQ.
2013          */
2014
2015         memset(&entry,0,sizeof(entry));
2016
2017         entry.delivery_mode = INT_DELIVERY_MODE;
2018         entry.dest_mode = INT_DEST_MODE;
2019         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2020         entry.trigger = triggering;
2021         entry.polarity = polarity;
2022         entry.mask = 1;                                  /* Disabled (masked) */
2023
2024         irq = gsi_irq_sharing(irq);
2025         /*
2026          * IRQs < 16 are already in the irq_2_pin[] map
2027          */
2028         if (irq >= 16)
2029                 add_pin_to_irq(irq, ioapic, pin);
2030
2031         entry.vector = assign_irq_vector(irq);
2032
2033         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2034                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2035                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2036                triggering, polarity);
2037
2038         ioapic_register_intr(irq, entry.vector, triggering);
2039
2040         if (!ioapic && (irq < 16))
2041                 disable_8259A_irq(irq);
2042
2043         spin_lock_irqsave(&ioapic_lock, flags);
2044         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2045         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2046         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
2047         spin_unlock_irqrestore(&ioapic_lock, flags);
2048
2049         return 0;
2050 }
2051
2052 #endif /* CONFIG_ACPI */
2053
2054
2055 /*
2056  * This function currently is only a helper for the i386 smp boot process where
2057  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2058  * so mask in all cases should simply be TARGET_CPUS
2059  */
2060 #ifdef CONFIG_SMP
2061 void __init setup_ioapic_dest(void)
2062 {
2063         int pin, ioapic, irq, irq_entry;
2064
2065         if (skip_ioapic_setup == 1)
2066                 return;
2067
2068         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2069                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2070                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2071                         if (irq_entry == -1)
2072                                 continue;
2073                         irq = pin_2_irq(irq_entry, ioapic, pin);
2074                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2075                 }
2076
2077         }
2078 }
2079 #endif