arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/pci.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/msi.h>
  34 #include <linux/htirq.h>
  35 #ifdef CONFIG_ACPI
  36 #include <acpi/acpi_bus.h>
  37 #endif
  38
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/proto.h>
  43 #include <asm/mach_apic.h>
  44 #include <asm/acpi.h>
  45 #include <asm/dma.h>
  46 #include <asm/nmi.h>
  47 #include <asm/msidef.h>
  48 #include <asm/hypertransport.h>
  49
  50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
  51
  52 #define __apicdebuginit  __init
  53
  54 int sis_apic_bug; /* not actually supported, dummy for compile */
  55
  56 static int no_timer_check;
  57
  58 static int disable_timer_pin_1 __initdata;
  59
  60 int timer_over_8254 __initdata = 1;
  61
  62 /* Where if anywhere is the i8259 connect in external int mode */
  63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  64
  65 static DEFINE_SPINLOCK(ioapic_lock);
  66 DEFINE_SPINLOCK(vector_lock);
  67
  68 /*
  69  * # of IRQ routing registers
  70  */
  71 int nr_ioapic_registers[MAX_IO_APICS];
  72
  73 /*
  74  * Rough estimation of how many shared IRQs there are, can
  75  * be changed anytime.
  76  */
  77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  79
  80 /*
  81  * This is performance-critical, we want to do it O(1)
  82  *
  83  * the indexing order of this array favors 1:1 mappings
  84  * between pins and IRQs.
  85  */
  86
  87 static struct irq_pin_list {
  88         short apic, pin, next;
  89 } irq_2_pin[PIN_MAP_SIZE];
  90
  91 struct io_apic {
  92         unsigned int index;
  93         unsigned int unused[3];
  94         unsigned int data;
  95 };
  96
  97 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
  98 {
  99         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 100                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 101 }
 102
 103 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 104 {
 105         struct io_apic __iomem *io_apic = io_apic_base(apic);
 106         writel(reg, &io_apic->index);
 107         return readl(&io_apic->data);
 108 }
 109
 110 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 111 {
 112         struct io_apic __iomem *io_apic = io_apic_base(apic);
 113         writel(reg, &io_apic->index);
 114         writel(value, &io_apic->data);
 115 }
 116
 117 /*
 118  * Re-write a value: to be used for read-modify-write
 119  * cycles where the read already set up the index register.
 120  */
 121 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 122 {
 123         struct io_apic __iomem *io_apic = io_apic_base(apic);
 124         writel(value, &io_apic->data);
 125 }
 126
 127 /*
 128  * Synchronize the IO-APIC and the CPU by doing
 129  * a dummy read from the IO-APIC
 130  */
 131 static inline void io_apic_sync(unsigned int apic)
 132 {
 133         struct io_apic __iomem *io_apic = io_apic_base(apic);
 134         readl(&io_apic->data);
 135 }
 136
 137 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 138                                                                         \
 139 {                                                                       \
 140         int pin;                                                        \
 141         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 142                                                                         \
 143         BUG_ON(irq >= NR_IRQS);                                         \
 144         for (;;) {                                                      \
 145                 unsigned int reg;                                       \
 146                 pin = entry->pin;                                       \
 147                 if (pin == -1)                                          \
 148                         break;                                          \
 149                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 150                 reg ACTION;                                             \
 151                 io_apic_modify(entry->apic, reg);                       \
 152                 if (!entry->next)                                       \
 153                         break;                                          \
 154                 entry = irq_2_pin + entry->next;                        \
 155         }                                                               \
 156         FINAL;                                                          \
 157 }
 158
 159 union entry_union {
 160         struct { u32 w1, w2; };
 161         struct IO_APIC_route_entry entry;
 162 };
 163
 164 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 165 {
 166         union entry_union eu;
 167         unsigned long flags;
 168         spin_lock_irqsave(&ioapic_lock, flags);
 169         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 170         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 171         spin_unlock_irqrestore(&ioapic_lock, flags);
 172         return eu.entry;
 173 }
 174
 175 /*
 176  * When we write a new IO APIC routing entry, we need to write the high
 177  * word first! If the mask bit in the low word is clear, we will enable
 178  * the interrupt, and we need to make sure the entry is fully populated
 179  * before that happens.
 180  */
 181 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 182 {
 183         unsigned long flags;
 184         union entry_union eu;
 185         eu.entry = e;
 186         spin_lock_irqsave(&ioapic_lock, flags);
 187         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 188         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 189         spin_unlock_irqrestore(&ioapic_lock, flags);
 190 }
 191
 192 /*
 193  * When we mask an IO APIC routing entry, we need to write the low
 194  * word first, in order to set the mask bit before we change the
 195  * high bits!
 196  */
 197 static void ioapic_mask_entry(int apic, int pin)
 198 {
 199         unsigned long flags;
 200         union entry_union eu = { .entry.mask = 1 };
 201
 202         spin_lock_irqsave(&ioapic_lock, flags);
 203         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 204         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 205         spin_unlock_irqrestore(&ioapic_lock, flags);
 206 }
 207
 208 #ifdef CONFIG_SMP
 209 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
 210 {
 211         int apic, pin;
 212         struct irq_pin_list *entry = irq_2_pin + irq;
 213
 214         BUG_ON(irq >= NR_IRQS);
 215         for (;;) {
 216                 unsigned int reg;
 217                 apic = entry->apic;
 218                 pin = entry->pin;
 219                 if (pin == -1)
 220                         break;
 221                 io_apic_write(apic, 0x11 + pin*2, dest);
 222                 reg = io_apic_read(apic, 0x10 + pin*2);
 223                 reg &= ~0x000000ff;
 224                 reg |= vector;
 225                 io_apic_modify(apic, reg);
 226                 if (!entry->next)
 227                         break;
 228                 entry = irq_2_pin + entry->next;
 229         }
 230 }
 231
 232 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 233 {
 234         unsigned long flags;
 235         unsigned int dest;
 236         cpumask_t tmp;
 237         int vector;
 238
 239         cpus_and(tmp, mask, cpu_online_map);
 240         if (cpus_empty(tmp))
 241                 tmp = TARGET_CPUS;
 242
 243         cpus_and(mask, tmp, CPU_MASK_ALL);
 244
 245         vector = assign_irq_vector(irq, mask, &tmp);
 246         if (vector < 0)
 247                 return;
 248
 249         dest = cpu_mask_to_apicid(tmp);
 250
 251         /*
 252          * Only the high 8 bits are valid.
 253          */
 254         dest = SET_APIC_LOGICAL_ID(dest);
 255
 256         spin_lock_irqsave(&ioapic_lock, flags);
 257         __target_IO_APIC_irq(irq, dest, vector);
 258         set_native_irq_info(irq, mask);
 259         spin_unlock_irqrestore(&ioapic_lock, flags);
 260 }
 261 #endif
 262
 263 /*
 264  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 265  * shared ISA-space IRQs, so we have to support them. We are super
 266  * fast in the common case, and fast for shared ISA-space IRQs.
 267  */
 268 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 269 {
 270         static int first_free_entry = NR_IRQS;
 271         struct irq_pin_list *entry = irq_2_pin + irq;
 272
 273         BUG_ON(irq >= NR_IRQS);
 274         while (entry->next)
 275                 entry = irq_2_pin + entry->next;
 276
 277         if (entry->pin != -1) {
 278                 entry->next = first_free_entry;
 279                 entry = irq_2_pin + entry->next;
 280                 if (++first_free_entry >= PIN_MAP_SIZE)
 281                         panic("io_apic.c: ran out of irq_2_pin entries!");
 282         }
 283         entry->apic = apic;
 284         entry->pin = pin;
 285 }
 286
 287
 288 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 289                                                                         \
 290         static void name##_IO_APIC_irq (unsigned int irq)               \
 291         __DO_ACTION(R, ACTION, FINAL)
 292
 293 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 294                                                 /* mask = 1 */
 295 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 296                                                 /* mask = 0 */
 297
 298 static void mask_IO_APIC_irq (unsigned int irq)
 299 {
 300         unsigned long flags;
 301
 302         spin_lock_irqsave(&ioapic_lock, flags);
 303         __mask_IO_APIC_irq(irq);
 304         spin_unlock_irqrestore(&ioapic_lock, flags);
 305 }
 306
 307 static void unmask_IO_APIC_irq (unsigned int irq)
 308 {
 309         unsigned long flags;
 310
 311         spin_lock_irqsave(&ioapic_lock, flags);
 312         __unmask_IO_APIC_irq(irq);
 313         spin_unlock_irqrestore(&ioapic_lock, flags);
 314 }
 315
 316 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 317 {
 318         struct IO_APIC_route_entry entry;
 319
 320         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 321         entry = ioapic_read_entry(apic, pin);
 322         if (entry.delivery_mode == dest_SMI)
 323                 return;
 324         /*
 325          * Disable it in the IO-APIC irq-routing table:
 326          */
 327         ioapic_mask_entry(apic, pin);
 328 }
 329
 330 static void clear_IO_APIC (void)
 331 {
 332         int apic, pin;
 333
 334         for (apic = 0; apic < nr_ioapics; apic++)
 335                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 336                         clear_IO_APIC_pin(apic, pin);
 337 }
 338
 339 int skip_ioapic_setup;
 340 int ioapic_force;
 341
 342 /* dummy parsing: see setup.c */
 343
 344 static int __init disable_ioapic_setup(char *str)
 345 {
 346         skip_ioapic_setup = 1;
 347         return 0;
 348 }
 349 early_param("noapic", disable_ioapic_setup);
 350
 351 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
 352 static int __init disable_timer_pin_setup(char *arg)
 353 {
 354         disable_timer_pin_1 = 1;
 355         return 1;
 356 }
 357 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 358
 359 static int __init setup_disable_8254_timer(char *s)
 360 {
 361         timer_over_8254 = -1;
 362         return 1;
 363 }
 364 static int __init setup_enable_8254_timer(char *s)
 365 {
 366         timer_over_8254 = 2;
 367         return 1;
 368 }
 369
 370 __setup("disable_8254_timer", setup_disable_8254_timer);
 371 __setup("enable_8254_timer", setup_enable_8254_timer);
 372
 373
 374 /*
 375  * Find the IRQ entry number of a certain pin.
 376  */
 377 static int find_irq_entry(int apic, int pin, int type)
 378 {
 379         int i;
 380
 381         for (i = 0; i < mp_irq_entries; i++)
 382                 if (mp_irqs[i].mpc_irqtype == type &&
 383                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 384                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 385                     mp_irqs[i].mpc_dstirq == pin)
 386                         return i;
 387
 388         return -1;
 389 }
 390
 391 /*
 392  * Find the pin to which IRQ[irq] (ISA) is connected
 393  */
 394 static int __init find_isa_irq_pin(int irq, int type)
 395 {
 396         int i;
 397
 398         for (i = 0; i < mp_irq_entries; i++) {
 399                 int lbus = mp_irqs[i].mpc_srcbus;
 400
 401                 if (test_bit(lbus, mp_bus_not_pci) &&
 402                     (mp_irqs[i].mpc_irqtype == type) &&
 403                     (mp_irqs[i].mpc_srcbusirq == irq))
 404
 405                         return mp_irqs[i].mpc_dstirq;
 406         }
 407         return -1;
 408 }
 409
 410 static int __init find_isa_irq_apic(int irq, int type)
 411 {
 412         int i;
 413
 414         for (i = 0; i < mp_irq_entries; i++) {
 415                 int lbus = mp_irqs[i].mpc_srcbus;
 416
 417                 if (test_bit(lbus, mp_bus_not_pci) &&
 418                     (mp_irqs[i].mpc_irqtype == type) &&
 419                     (mp_irqs[i].mpc_srcbusirq == irq))
 420                         break;
 421         }
 422         if (i < mp_irq_entries) {
 423                 int apic;
 424                 for(apic = 0; apic < nr_ioapics; apic++) {
 425                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 426                                 return apic;
 427                 }
 428         }
 429
 430         return -1;
 431 }
 432
 433 /*
 434  * Find a specific PCI IRQ entry.
 435  * Not an __init, possibly needed by modules
 436  */
 437 static int pin_2_irq(int idx, int apic, int pin);
 438
 439 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 440 {
 441         int apic, i, best_guess = -1;
 442
 443         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 444                 bus, slot, pin);
 445         if (mp_bus_id_to_pci_bus[bus] == -1) {
 446                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 447                 return -1;
 448         }
 449         for (i = 0; i < mp_irq_entries; i++) {
 450                 int lbus = mp_irqs[i].mpc_srcbus;
 451
 452                 for (apic = 0; apic < nr_ioapics; apic++)
 453                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 454                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 455                                 break;
 456
 457                 if (!test_bit(lbus, mp_bus_not_pci) &&
 458                     !mp_irqs[i].mpc_irqtype &&
 459                     (bus == lbus) &&
 460                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 461                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 462
 463                         if (!(apic || IO_APIC_IRQ(irq)))
 464                                 continue;
 465
 466                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 467                                 return irq;
 468                         /*
 469                          * Use the first all-but-pin matching entry as a
 470                          * best-guess fuzzy result for broken mptables.
 471                          */
 472                         if (best_guess < 0)
 473                                 best_guess = irq;
 474                 }
 475         }
 476         BUG_ON(best_guess >= NR_IRQS);
 477         return best_guess;
 478 }
 479
 480 /* ISA interrupts are always polarity zero edge triggered,
 481  * when listed as conforming in the MP table. */
 482
 483 #define default_ISA_trigger(idx)        (0)
 484 #define default_ISA_polarity(idx)       (0)
 485
 486 /* PCI interrupts are always polarity one level triggered,
 487  * when listed as conforming in the MP table. */
 488
 489 #define default_PCI_trigger(idx)        (1)
 490 #define default_PCI_polarity(idx)       (1)
 491
 492 static int __init MPBIOS_polarity(int idx)
 493 {
 494         int bus = mp_irqs[idx].mpc_srcbus;
 495         int polarity;
 496
 497         /*
 498          * Determine IRQ line polarity (high active or low active):
 499          */
 500         switch (mp_irqs[idx].mpc_irqflag & 3)
 501         {
 502                 case 0: /* conforms, ie. bus-type dependent polarity */
 503                         if (test_bit(bus, mp_bus_not_pci))
 504                                 polarity = default_ISA_polarity(idx);
 505                         else
 506                                 polarity = default_PCI_polarity(idx);
 507                         break;
 508                 case 1: /* high active */
 509                 {
 510                         polarity = 0;
 511                         break;
 512                 }
 513                 case 2: /* reserved */
 514                 {
 515                         printk(KERN_WARNING "broken BIOS!!\n");
 516                         polarity = 1;
 517                         break;
 518                 }
 519                 case 3: /* low active */
 520                 {
 521                         polarity = 1;
 522                         break;
 523                 }
 524                 default: /* invalid */
 525                 {
 526                         printk(KERN_WARNING "broken BIOS!!\n");
 527                         polarity = 1;
 528                         break;
 529                 }
 530         }
 531         return polarity;
 532 }
 533
 534 static int MPBIOS_trigger(int idx)
 535 {
 536         int bus = mp_irqs[idx].mpc_srcbus;
 537         int trigger;
 538
 539         /*
 540          * Determine IRQ trigger mode (edge or level sensitive):
 541          */
 542         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 543         {
 544                 case 0: /* conforms, ie. bus-type dependent */
 545                         if (test_bit(bus, mp_bus_not_pci))
 546                                 trigger = default_ISA_trigger(idx);
 547                         else
 548                                 trigger = default_PCI_trigger(idx);
 549                         break;
 550                 case 1: /* edge */
 551                 {
 552                         trigger = 0;
 553                         break;
 554                 }
 555                 case 2: /* reserved */
 556                 {
 557                         printk(KERN_WARNING "broken BIOS!!\n");
 558                         trigger = 1;
 559                         break;
 560                 }
 561                 case 3: /* level */
 562                 {
 563                         trigger = 1;
 564                         break;
 565                 }
 566                 default: /* invalid */
 567                 {
 568                         printk(KERN_WARNING "broken BIOS!!\n");
 569                         trigger = 0;
 570                         break;
 571                 }
 572         }
 573         return trigger;
 574 }
 575
 576 static inline int irq_polarity(int idx)
 577 {
 578         return MPBIOS_polarity(idx);
 579 }
 580
 581 static inline int irq_trigger(int idx)
 582 {
 583         return MPBIOS_trigger(idx);
 584 }
 585
 586 static int pin_2_irq(int idx, int apic, int pin)
 587 {
 588         int irq, i;
 589         int bus = mp_irqs[idx].mpc_srcbus;
 590
 591         /*
 592          * Debugging check, we are in big trouble if this message pops up!
 593          */
 594         if (mp_irqs[idx].mpc_dstirq != pin)
 595                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 596
 597         if (test_bit(bus, mp_bus_not_pci)) {
 598                 irq = mp_irqs[idx].mpc_srcbusirq;
 599         } else {
 600                 /*
 601                  * PCI IRQs are mapped in order
 602                  */
 603                 i = irq = 0;
 604                 while (i < apic)
 605                         irq += nr_ioapic_registers[i++];
 606                 irq += pin;
 607         }
 608         BUG_ON(irq >= NR_IRQS);
 609         return irq;
 610 }
 611
 612 static inline int IO_APIC_irq_trigger(int irq)
 613 {
 614         int apic, idx, pin;
 615
 616         for (apic = 0; apic < nr_ioapics; apic++) {
 617                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 618                         idx = find_irq_entry(apic,pin,mp_INT);
 619                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 620                                 return irq_trigger(idx);
 621                 }
 622         }
 623         /*
 624          * nonexistent IRQs are edge default
 625          */
 626         return 0;
 627 }
 628
 629 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 630 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
 631         [0] = FIRST_EXTERNAL_VECTOR + 0,
 632         [1] = FIRST_EXTERNAL_VECTOR + 1,
 633         [2] = FIRST_EXTERNAL_VECTOR + 2,
 634         [3] = FIRST_EXTERNAL_VECTOR + 3,
 635         [4] = FIRST_EXTERNAL_VECTOR + 4,
 636         [5] = FIRST_EXTERNAL_VECTOR + 5,
 637         [6] = FIRST_EXTERNAL_VECTOR + 6,
 638         [7] = FIRST_EXTERNAL_VECTOR + 7,
 639         [8] = FIRST_EXTERNAL_VECTOR + 8,
 640         [9] = FIRST_EXTERNAL_VECTOR + 9,
 641         [10] = FIRST_EXTERNAL_VECTOR + 10,
 642         [11] = FIRST_EXTERNAL_VECTOR + 11,
 643         [12] = FIRST_EXTERNAL_VECTOR + 12,
 644         [13] = FIRST_EXTERNAL_VECTOR + 13,
 645         [14] = FIRST_EXTERNAL_VECTOR + 14,
 646         [15] = FIRST_EXTERNAL_VECTOR + 15,
 647 };
 648
 649 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
 650         [0] = CPU_MASK_ALL,
 651         [1] = CPU_MASK_ALL,
 652         [2] = CPU_MASK_ALL,
 653         [3] = CPU_MASK_ALL,
 654         [4] = CPU_MASK_ALL,
 655         [5] = CPU_MASK_ALL,
 656         [6] = CPU_MASK_ALL,
 657         [7] = CPU_MASK_ALL,
 658         [8] = CPU_MASK_ALL,
 659         [9] = CPU_MASK_ALL,
 660         [10] = CPU_MASK_ALL,
 661         [11] = CPU_MASK_ALL,
 662         [12] = CPU_MASK_ALL,
 663         [13] = CPU_MASK_ALL,
 664         [14] = CPU_MASK_ALL,
 665         [15] = CPU_MASK_ALL,
 666 };
 667
 668 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 669 {
 670         /*
 671          * NOTE! The local APIC isn't very good at handling
 672          * multiple interrupts at the same interrupt level.
 673          * As the interrupt level is determined by taking the
 674          * vector number and shifting that right by 4, we
 675          * want to spread these out a bit so that they don't
 676          * all fall in the same interrupt level.
 677          *
 678          * Also, we've got to be careful not to trash gate
 679          * 0x80, because int 0x80 is hm, kind of importantish. ;)
 680          */
 681         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
 682         int old_vector = -1;
 683         int cpu;
 684
 685         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
 686
 687         /* Only try and allocate irqs on cpus that are present */
 688         cpus_and(mask, mask, cpu_online_map);
 689
 690         if (irq_vector[irq] > 0)
 691                 old_vector = irq_vector[irq];
 692         if (old_vector > 0) {
 693                 cpus_and(*result, irq_domain[irq], mask);
 694                 if (!cpus_empty(*result))
 695                         return old_vector;
 696         }
 697
 698         for_each_cpu_mask(cpu, mask) {
 699                 cpumask_t domain, new_mask;
 700                 int new_cpu;
 701                 int vector, offset;
 702
 703                 domain = vector_allocation_domain(cpu);
 704                 cpus_and(new_mask, domain, cpu_online_map);
 705
 706                 vector = current_vector;
 707                 offset = current_offset;
 708 next:
 709                 vector += 8;
 710                 if (vector >= FIRST_SYSTEM_VECTOR) {
 711                         /* If we run out of vectors on large boxen, must share them. */
 712                         offset = (offset + 1) % 8;
 713                         vector = FIRST_DEVICE_VECTOR + offset;
 714                 }
 715                 if (unlikely(current_vector == vector))
 716                         continue;
 717                 if (vector == IA32_SYSCALL_VECTOR)
 718                         goto next;
 719                 for_each_cpu_mask(new_cpu, new_mask)
 720                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
 721                                 goto next;
 722                 /* Found one! */
 723                 current_vector = vector;
 724                 current_offset = offset;
 725                 if (old_vector >= 0) {
 726                         cpumask_t old_mask;
 727                         int old_cpu;
 728                         cpus_and(old_mask, irq_domain[irq], cpu_online_map);
 729                         for_each_cpu_mask(old_cpu, old_mask)
 730                                 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
 731                 }
 732                 for_each_cpu_mask(new_cpu, new_mask)
 733                         per_cpu(vector_irq, new_cpu)[vector] = irq;
 734                 irq_vector[irq] = vector;
 735                 irq_domain[irq] = domain;
 736                 cpus_and(*result, domain, mask);
 737                 return vector;
 738         }
 739         return -ENOSPC;
 740 }
 741
 742 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 743 {
 744         int vector;
 745         unsigned long flags;
 746
 747         spin_lock_irqsave(&vector_lock, flags);
 748         vector = __assign_irq_vector(irq, mask, result);
 749         spin_unlock_irqrestore(&vector_lock, flags);
 750         return vector;
 751 }
 752
 753 void __setup_vector_irq(int cpu)
 754 {
 755         /* Initialize vector_irq on a new cpu */
 756         /* This function must be called with vector_lock held */
 757         unsigned long flags;
 758         int irq, vector;
 759
 760
 761         /* Mark the inuse vectors */
 762         for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
 763                 if (!cpu_isset(cpu, irq_domain[irq]))
 764                         continue;
 765                 vector = irq_vector[irq];
 766                 per_cpu(vector_irq, cpu)[vector] = irq;
 767         }
 768         /* Mark the free vectors */
 769         for (vector = 0; vector < NR_VECTORS; ++vector) {
 770                 irq = per_cpu(vector_irq, cpu)[vector];
 771                 if (irq < 0)
 772                         continue;
 773                 if (!cpu_isset(cpu, irq_domain[irq]))
 774                         per_cpu(vector_irq, cpu)[vector] = -1;
 775         }
 776 }
 777
 778
 779 extern void (*interrupt[NR_IRQS])(void);
 780
 781 static struct irq_chip ioapic_chip;
 782
 783 #define IOAPIC_AUTO     -1
 784 #define IOAPIC_EDGE     0
 785 #define IOAPIC_LEVEL    1
 786
 787 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 788 {
 789         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 790                         trigger == IOAPIC_LEVEL)
 791                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 792                                               handle_fasteoi_irq, "fasteoi");
 793         else {
 794                 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
 795                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 796                                               handle_edge_irq, "edge");
 797         }
 798 }
 799
 800 static void __init setup_IO_APIC_irqs(void)
 801 {
 802         struct IO_APIC_route_entry entry;
 803         int apic, pin, idx, irq, first_notcon = 1, vector;
 804         unsigned long flags;
 805
 806         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 807
 808         for (apic = 0; apic < nr_ioapics; apic++) {
 809         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 810
 811                 /*
 812                  * add it to the IO-APIC irq-routing table:
 813                  */
 814                 memset(&entry,0,sizeof(entry));
 815
 816                 entry.delivery_mode = INT_DELIVERY_MODE;
 817                 entry.dest_mode = INT_DEST_MODE;
 818                 entry.mask = 0;                         /* enable IRQ */
 819                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 820
 821                 idx = find_irq_entry(apic,pin,mp_INT);
 822                 if (idx == -1) {
 823                         if (first_notcon) {
 824                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 825                                 first_notcon = 0;
 826                         } else
 827                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 828                         continue;
 829                 }
 830
 831                 entry.trigger = irq_trigger(idx);
 832                 entry.polarity = irq_polarity(idx);
 833
 834                 if (irq_trigger(idx)) {
 835                         entry.trigger = 1;
 836                         entry.mask = 1;
 837                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 838                 }
 839
 840                 irq = pin_2_irq(idx, apic, pin);
 841                 add_pin_to_irq(irq, apic, pin);
 842
 843                 if (!apic && !IO_APIC_IRQ(irq))
 844                         continue;
 845
 846                 if (IO_APIC_IRQ(irq)) {
 847                         cpumask_t mask;
 848                         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
 849                         if (vector < 0)
 850                                 continue;
 851
 852                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
 853                         entry.vector = vector;
 854
 855                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 856                         if (!apic && (irq < 16))
 857                                 disable_8259A_irq(irq);
 858                 }
 859                 ioapic_write_entry(apic, pin, entry);
 860
 861                 spin_lock_irqsave(&ioapic_lock, flags);
 862                 set_native_irq_info(irq, TARGET_CPUS);
 863                 spin_unlock_irqrestore(&ioapic_lock, flags);
 864         }
 865         }
 866
 867         if (!first_notcon)
 868                 apic_printk(APIC_VERBOSE," not connected.\n");
 869 }
 870
 871 /*
 872  * Set up the 8259A-master output pin as broadcast to all
 873  * CPUs.
 874  */
 875 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 876 {
 877         struct IO_APIC_route_entry entry;
 878         unsigned long flags;
 879
 880         memset(&entry,0,sizeof(entry));
 881
 882         disable_8259A_irq(0);
 883
 884         /* mask LVT0 */
 885         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 886
 887         /*
 888          * We use logical delivery to get the timer IRQ
 889          * to the first CPU.
 890          */
 891         entry.dest_mode = INT_DEST_MODE;
 892         entry.mask = 0;                                 /* unmask IRQ now */
 893         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 894         entry.delivery_mode = INT_DELIVERY_MODE;
 895         entry.polarity = 0;
 896         entry.trigger = 0;
 897         entry.vector = vector;
 898
 899         /*
 900          * The timer IRQ doesn't have to know that behind the
 901          * scene we have a 8259A-master in AEOI mode ...
 902          */
 903         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 904
 905         /*
 906          * Add it to the IO-APIC irq-routing table:
 907          */
 908         spin_lock_irqsave(&ioapic_lock, flags);
 909         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 910         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 911         spin_unlock_irqrestore(&ioapic_lock, flags);
 912
 913         enable_8259A_irq(0);
 914 }
 915
 916 void __init UNEXPECTED_IO_APIC(void)
 917 {
 918 }
 919
 920 void __apicdebuginit print_IO_APIC(void)
 921 {
 922         int apic, i;
 923         union IO_APIC_reg_00 reg_00;
 924         union IO_APIC_reg_01 reg_01;
 925         union IO_APIC_reg_02 reg_02;
 926         unsigned long flags;
 927
 928         if (apic_verbosity == APIC_QUIET)
 929                 return;
 930
 931         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 932         for (i = 0; i < nr_ioapics; i++)
 933                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 934                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 935
 936         /*
 937          * We are a bit conservative about what we expect.  We have to
 938          * know about every hardware change ASAP.
 939          */
 940         printk(KERN_INFO "testing the IO APIC.......................\n");
 941
 942         for (apic = 0; apic < nr_ioapics; apic++) {
 943
 944         spin_lock_irqsave(&ioapic_lock, flags);
 945         reg_00.raw = io_apic_read(apic, 0);
 946         reg_01.raw = io_apic_read(apic, 1);
 947         if (reg_01.bits.version >= 0x10)
 948                 reg_02.raw = io_apic_read(apic, 2);
 949         spin_unlock_irqrestore(&ioapic_lock, flags);
 950
 951         printk("\n");
 952         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 953         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 954         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 955         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 956                 UNEXPECTED_IO_APIC();
 957
 958         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 959         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 960         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 961                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 962                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 963                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 964                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 965                 (reg_01.bits.entries != 0x2E) &&
 966                 (reg_01.bits.entries != 0x3F) &&
 967                 (reg_01.bits.entries != 0x03)
 968         )
 969                 UNEXPECTED_IO_APIC();
 970
 971         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 972         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 973         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 974                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 975                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 976                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 977                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 978                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 979         )
 980                 UNEXPECTED_IO_APIC();
 981         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 982                 UNEXPECTED_IO_APIC();
 983
 984         if (reg_01.bits.version >= 0x10) {
 985                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 986                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 987                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 988                         UNEXPECTED_IO_APIC();
 989         }
 990
 991         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 992
 993         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 994                           " Stat Dest Deli Vect:   \n");
 995
 996         for (i = 0; i <= reg_01.bits.entries; i++) {
 997                 struct IO_APIC_route_entry entry;
 998
 999                 entry = ioapic_read_entry(apic, i);
1000
1001                 printk(KERN_DEBUG " %02x %03X %02X  ",
1002                         i,
1003                         entry.dest.logical.logical_dest,
1004                         entry.dest.physical.physical_dest
1005                 );
1006
1007                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1008                         entry.mask,
1009                         entry.trigger,
1010                         entry.irr,
1011                         entry.polarity,
1012                         entry.delivery_status,
1013                         entry.dest_mode,
1014                         entry.delivery_mode,
1015                         entry.vector
1016                 );
1017         }
1018         }
1019         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1020         for (i = 0; i < NR_IRQS; i++) {
1021                 struct irq_pin_list *entry = irq_2_pin + i;
1022                 if (entry->pin < 0)
1023                         continue;
1024                 printk(KERN_DEBUG "IRQ%d ", i);
1025                 for (;;) {
1026                         printk("-> %d:%d", entry->apic, entry->pin);
1027                         if (!entry->next)
1028                                 break;
1029                         entry = irq_2_pin + entry->next;
1030                 }
1031                 printk("\n");
1032         }
1033
1034         printk(KERN_INFO ".................................... done.\n");
1035
1036         return;
1037 }
1038
1039 #if 0
1040
1041 static __apicdebuginit void print_APIC_bitfield (int base)
1042 {
1043         unsigned int v;
1044         int i, j;
1045
1046         if (apic_verbosity == APIC_QUIET)
1047                 return;
1048
1049         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1050         for (i = 0; i < 8; i++) {
1051                 v = apic_read(base + i*0x10);
1052                 for (j = 0; j < 32; j++) {
1053                         if (v & (1<<j))
1054                                 printk("1");
1055                         else
1056                                 printk("0");
1057                 }
1058                 printk("\n");
1059         }
1060 }
1061
1062 void __apicdebuginit print_local_APIC(void * dummy)
1063 {
1064         unsigned int v, ver, maxlvt;
1065
1066         if (apic_verbosity == APIC_QUIET)
1067                 return;
1068
1069         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1070                 smp_processor_id(), hard_smp_processor_id());
1071         v = apic_read(APIC_ID);
1072         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1073         v = apic_read(APIC_LVR);
1074         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1075         ver = GET_APIC_VERSION(v);
1076         maxlvt = get_maxlvt();
1077
1078         v = apic_read(APIC_TASKPRI);
1079         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1080
1081         v = apic_read(APIC_ARBPRI);
1082         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1083                 v & APIC_ARBPRI_MASK);
1084         v = apic_read(APIC_PROCPRI);
1085         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1086
1087         v = apic_read(APIC_EOI);
1088         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1089         v = apic_read(APIC_RRR);
1090         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1091         v = apic_read(APIC_LDR);
1092         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1093         v = apic_read(APIC_DFR);
1094         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1095         v = apic_read(APIC_SPIV);
1096         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1097
1098         printk(KERN_DEBUG "... APIC ISR field:\n");
1099         print_APIC_bitfield(APIC_ISR);
1100         printk(KERN_DEBUG "... APIC TMR field:\n");
1101         print_APIC_bitfield(APIC_TMR);
1102         printk(KERN_DEBUG "... APIC IRR field:\n");
1103         print_APIC_bitfield(APIC_IRR);
1104
1105         v = apic_read(APIC_ESR);
1106         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1107
1108         v = apic_read(APIC_ICR);
1109         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1110         v = apic_read(APIC_ICR2);
1111         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1112
1113         v = apic_read(APIC_LVTT);
1114         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1115
1116         if (maxlvt > 3) {                       /* PC is LVT#4. */
1117                 v = apic_read(APIC_LVTPC);
1118                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1119         }
1120         v = apic_read(APIC_LVT0);
1121         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1122         v = apic_read(APIC_LVT1);
1123         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1124
1125         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1126                 v = apic_read(APIC_LVTERR);
1127                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1128         }
1129
1130         v = apic_read(APIC_TMICT);
1131         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1132         v = apic_read(APIC_TMCCT);
1133         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1134         v = apic_read(APIC_TDCR);
1135         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1136         printk("\n");
1137 }
1138
1139 void print_all_local_APICs (void)
1140 {
1141         on_each_cpu(print_local_APIC, NULL, 1, 1);
1142 }
1143
1144 void __apicdebuginit print_PIC(void)
1145 {
1146         unsigned int v;
1147         unsigned long flags;
1148
1149         if (apic_verbosity == APIC_QUIET)
1150                 return;
1151
1152         printk(KERN_DEBUG "\nprinting PIC contents\n");
1153
1154         spin_lock_irqsave(&i8259A_lock, flags);
1155
1156         v = inb(0xa1) << 8 | inb(0x21);
1157         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1158
1159         v = inb(0xa0) << 8 | inb(0x20);
1160         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1161
1162         outb(0x0b,0xa0);
1163         outb(0x0b,0x20);
1164         v = inb(0xa0) << 8 | inb(0x20);
1165         outb(0x0a,0xa0);
1166         outb(0x0a,0x20);
1167
1168         spin_unlock_irqrestore(&i8259A_lock, flags);
1169
1170         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1171
1172         v = inb(0x4d1) << 8 | inb(0x4d0);
1173         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1174 }
1175
1176 #endif  /*  0  */
1177
1178 static void __init enable_IO_APIC(void)
1179 {
1180         union IO_APIC_reg_01 reg_01;
1181         int i8259_apic, i8259_pin;
1182         int i, apic;
1183         unsigned long flags;
1184
1185         for (i = 0; i < PIN_MAP_SIZE; i++) {
1186                 irq_2_pin[i].pin = -1;
1187                 irq_2_pin[i].next = 0;
1188         }
1189
1190         /*
1191          * The number of IO-APIC IRQ registers (== #pins):
1192          */
1193         for (apic = 0; apic < nr_ioapics; apic++) {
1194                 spin_lock_irqsave(&ioapic_lock, flags);
1195                 reg_01.raw = io_apic_read(apic, 1);
1196                 spin_unlock_irqrestore(&ioapic_lock, flags);
1197                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1198         }
1199         for(apic = 0; apic < nr_ioapics; apic++) {
1200                 int pin;
1201                 /* See if any of the pins is in ExtINT mode */
1202                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1203                         struct IO_APIC_route_entry entry;
1204                         entry = ioapic_read_entry(apic, pin);
1205
1206                         /* If the interrupt line is enabled and in ExtInt mode
1207                          * I have found the pin where the i8259 is connected.
1208                          */
1209                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1210                                 ioapic_i8259.apic = apic;
1211                                 ioapic_i8259.pin  = pin;
1212                                 goto found_i8259;
1213                         }
1214                 }
1215         }
1216  found_i8259:
1217         /* Look to see what if the MP table has reported the ExtINT */
1218         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1219         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1220         /* Trust the MP table if nothing is setup in the hardware */
1221         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1222                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1223                 ioapic_i8259.pin  = i8259_pin;
1224                 ioapic_i8259.apic = i8259_apic;
1225         }
1226         /* Complain if the MP table and the hardware disagree */
1227         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1228                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1229         {
1230                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1231         }
1232
1233         /*
1234          * Do not trust the IO-APIC being empty at bootup
1235          */
1236         clear_IO_APIC();
1237 }
1238
1239 /*
1240  * Not an __init, needed by the reboot code
1241  */
1242 void disable_IO_APIC(void)
1243 {
1244         /*
1245          * Clear the IO-APIC before rebooting:
1246          */
1247         clear_IO_APIC();
1248
1249         /*
1250          * If the i8259 is routed through an IOAPIC
1251          * Put that IOAPIC in virtual wire mode
1252          * so legacy interrupts can be delivered.
1253          */
1254         if (ioapic_i8259.pin != -1) {
1255                 struct IO_APIC_route_entry entry;
1256
1257                 memset(&entry, 0, sizeof(entry));
1258                 entry.mask            = 0; /* Enabled */
1259                 entry.trigger         = 0; /* Edge */
1260                 entry.irr             = 0;
1261                 entry.polarity        = 0; /* High */
1262                 entry.delivery_status = 0;
1263                 entry.dest_mode       = 0; /* Physical */
1264                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1265                 entry.vector          = 0;
1266                 entry.dest.physical.physical_dest =
1267                                         GET_APIC_ID(apic_read(APIC_ID));
1268
1269                 /*
1270                  * Add it to the IO-APIC irq-routing table:
1271                  */
1272                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1273         }
1274
1275         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1276 }
1277
1278 /*
1279  * There is a nasty bug in some older SMP boards, their mptable lies
1280  * about the timer IRQ. We do the following to work around the situation:
1281  *
1282  *      - timer IRQ defaults to IO-APIC IRQ
1283  *      - if this function detects that timer IRQs are defunct, then we fall
1284  *        back to ISA timer IRQs
1285  */
1286 static int __init timer_irq_works(void)
1287 {
1288         unsigned long t1 = jiffies;
1289
1290         local_irq_enable();
1291         /* Let ten ticks pass... */
1292         mdelay((10 * 1000) / HZ);
1293
1294         /*
1295          * Expect a few ticks at least, to be sure some possible
1296          * glue logic does not lock up after one or two first
1297          * ticks in a non-ExtINT mode.  Also the local APIC
1298          * might have cached one ExtINT interrupt.  Finally, at
1299          * least one tick may be lost due to delays.
1300          */
1301
1302         /* jiffies wrap? */
1303         if (jiffies - t1 > 4)
1304                 return 1;
1305         return 0;
1306 }
1307
1308 /*
1309  * In the SMP+IOAPIC case it might happen that there are an unspecified
1310  * number of pending IRQ events unhandled. These cases are very rare,
1311  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1312  * better to do it this way as thus we do not have to be aware of
1313  * 'pending' interrupts in the IRQ path, except at this point.
1314  */
1315 /*
1316  * Edge triggered needs to resend any interrupt
1317  * that was delayed but this is now handled in the device
1318  * independent code.
1319  */
1320
1321 /*
1322  * Starting up a edge-triggered IO-APIC interrupt is
1323  * nasty - we need to make sure that we get the edge.
1324  * If it is already asserted for some reason, we need
1325  * return 1 to indicate that is was pending.
1326  *
1327  * This is not complete - we should be able to fake
1328  * an edge even if it isn't on the 8259A...
1329  */
1330
1331 static unsigned int startup_ioapic_irq(unsigned int irq)
1332 {
1333         int was_pending = 0;
1334         unsigned long flags;
1335
1336         spin_lock_irqsave(&ioapic_lock, flags);
1337         if (irq < 16) {
1338                 disable_8259A_irq(irq);
1339                 if (i8259A_irq_pending(irq))
1340                         was_pending = 1;
1341         }
1342         __unmask_IO_APIC_irq(irq);
1343         spin_unlock_irqrestore(&ioapic_lock, flags);
1344
1345         return was_pending;
1346 }
1347
1348 static int ioapic_retrigger_irq(unsigned int irq)
1349 {
1350         cpumask_t mask;
1351         unsigned vector;
1352         unsigned long flags;
1353
1354         spin_lock_irqsave(&vector_lock, flags);
1355         vector = irq_vector[irq];
1356         cpus_clear(mask);
1357         cpu_set(first_cpu(irq_domain[irq]), mask);
1358
1359         send_IPI_mask(mask, vector);
1360         spin_unlock_irqrestore(&vector_lock, flags);
1361
1362         return 1;
1363 }
1364
1365 /*
1366  * Level and edge triggered IO-APIC interrupts need different handling,
1367  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1368  * handled with the level-triggered descriptor, but that one has slightly
1369  * more overhead. Level-triggered interrupts cannot be handled with the
1370  * edge-triggered handler, without risking IRQ storms and other ugly
1371  * races.
1372  */
1373
1374 static void ack_apic_edge(unsigned int irq)
1375 {
1376         move_native_irq(irq);
1377         ack_APIC_irq();
1378 }
1379
1380 static void ack_apic_level(unsigned int irq)
1381 {
1382         int do_unmask_irq = 0;
1383
1384 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1385         /* If we are moving the irq we need to mask it */
1386         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1387                 do_unmask_irq = 1;
1388                 mask_IO_APIC_irq(irq);
1389         }
1390 #endif
1391
1392         /*
1393          * We must acknowledge the irq before we move it or the acknowledge will
1394          * not propogate properly.
1395          */
1396         ack_APIC_irq();
1397
1398         /* Now we can move and renable the irq */
1399         move_masked_irq(irq);
1400         if (unlikely(do_unmask_irq))
1401                 unmask_IO_APIC_irq(irq);
1402 }
1403
1404 static struct irq_chip ioapic_chip __read_mostly = {
1405         .name           = "IO-APIC",
1406         .startup        = startup_ioapic_irq,
1407         .mask           = mask_IO_APIC_irq,
1408         .unmask         = unmask_IO_APIC_irq,
1409         .ack            = ack_apic_edge,
1410         .eoi            = ack_apic_level,
1411 #ifdef CONFIG_SMP
1412         .set_affinity   = set_ioapic_affinity_irq,
1413 #endif
1414         .retrigger      = ioapic_retrigger_irq,
1415 };
1416
1417 static inline void init_IO_APIC_traps(void)
1418 {
1419         int irq;
1420
1421         /*
1422          * NOTE! The local APIC isn't very good at handling
1423          * multiple interrupts at the same interrupt level.
1424          * As the interrupt level is determined by taking the
1425          * vector number and shifting that right by 4, we
1426          * want to spread these out a bit so that they don't
1427          * all fall in the same interrupt level.
1428          *
1429          * Also, we've got to be careful not to trash gate
1430          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1431          */
1432         for (irq = 0; irq < NR_IRQS ; irq++) {
1433                 int tmp = irq;
1434                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1435                         /*
1436                          * Hmm.. We don't have an entry for this,
1437                          * so default to an old-fashioned 8259
1438                          * interrupt if we can..
1439                          */
1440                         if (irq < 16)
1441                                 make_8259A_irq(irq);
1442                         else
1443                                 /* Strange. Oh, well.. */
1444                                 irq_desc[irq].chip = &no_irq_chip;
1445                 }
1446         }
1447 }
1448
1449 static void enable_lapic_irq (unsigned int irq)
1450 {
1451         unsigned long v;
1452
1453         v = apic_read(APIC_LVT0);
1454         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1455 }
1456
1457 static void disable_lapic_irq (unsigned int irq)
1458 {
1459         unsigned long v;
1460
1461         v = apic_read(APIC_LVT0);
1462         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1463 }
1464
1465 static void ack_lapic_irq (unsigned int irq)
1466 {
1467         ack_APIC_irq();
1468 }
1469
1470 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1471
1472 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1473         .typename = "local-APIC-edge",
1474         .startup = NULL, /* startup_irq() not used for IRQ0 */
1475         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1476         .enable = enable_lapic_irq,
1477         .disable = disable_lapic_irq,
1478         .ack = ack_lapic_irq,
1479         .end = end_lapic_irq,
1480 };
1481
1482 static void setup_nmi (void)
1483 {
1484         /*
1485          * Dirty trick to enable the NMI watchdog ...
1486          * We put the 8259A master into AEOI mode and
1487          * unmask on all local APICs LVT0 as NMI.
1488          *
1489          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1490          * is from Maciej W. Rozycki - so we do not have to EOI from
1491          * the NMI handler or the timer interrupt.
1492          */
1493         printk(KERN_INFO "activating NMI Watchdog ...");
1494
1495         enable_NMI_through_LVT0(NULL);
1496
1497         printk(" done.\n");
1498 }
1499
1500 /*
1501  * This looks a bit hackish but it's about the only one way of sending
1502  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1503  * not support the ExtINT mode, unfortunately.  We need to send these
1504  * cycles as some i82489DX-based boards have glue logic that keeps the
1505  * 8259A interrupt line asserted until INTA.  --macro
1506  */
1507 static inline void unlock_ExtINT_logic(void)
1508 {
1509         int apic, pin, i;
1510         struct IO_APIC_route_entry entry0, entry1;
1511         unsigned char save_control, save_freq_select;
1512         unsigned long flags;
1513
1514         pin  = find_isa_irq_pin(8, mp_INT);
1515         apic = find_isa_irq_apic(8, mp_INT);
1516         if (pin == -1)
1517                 return;
1518
1519         spin_lock_irqsave(&ioapic_lock, flags);
1520         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1521         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1522         spin_unlock_irqrestore(&ioapic_lock, flags);
1523         clear_IO_APIC_pin(apic, pin);
1524
1525         memset(&entry1, 0, sizeof(entry1));
1526
1527         entry1.dest_mode = 0;                   /* physical delivery */
1528         entry1.mask = 0;                        /* unmask IRQ now */
1529         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1530         entry1.delivery_mode = dest_ExtINT;
1531         entry1.polarity = entry0.polarity;
1532         entry1.trigger = 0;
1533         entry1.vector = 0;
1534
1535         spin_lock_irqsave(&ioapic_lock, flags);
1536         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1537         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1538         spin_unlock_irqrestore(&ioapic_lock, flags);
1539
1540         save_control = CMOS_READ(RTC_CONTROL);
1541         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1542         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1543                    RTC_FREQ_SELECT);
1544         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1545
1546         i = 100;
1547         while (i-- > 0) {
1548                 mdelay(10);
1549                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1550                         i -= 10;
1551         }
1552
1553         CMOS_WRITE(save_control, RTC_CONTROL);
1554         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1555         clear_IO_APIC_pin(apic, pin);
1556
1557         spin_lock_irqsave(&ioapic_lock, flags);
1558         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1559         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1560         spin_unlock_irqrestore(&ioapic_lock, flags);
1561 }
1562
1563 /*
1564  * This code may look a bit paranoid, but it's supposed to cooperate with
1565  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1566  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1567  * fanatically on his truly buggy board.
1568  *
1569  * FIXME: really need to revamp this for modern platforms only.
1570  */
1571 static inline void check_timer(void)
1572 {
1573         int apic1, pin1, apic2, pin2;
1574         int vector;
1575         cpumask_t mask;
1576
1577         /*
1578          * get/set the timer IRQ vector:
1579          */
1580         disable_8259A_irq(0);
1581         vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1582
1583         /*
1584          * Subtle, code in do_timer_interrupt() expects an AEOI
1585          * mode for the 8259A whenever interrupts are routed
1586          * through I/O APICs.  Also IRQ0 has to be enabled in
1587          * the 8259A which implies the virtual wire has to be
1588          * disabled in the local APIC.
1589          */
1590         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1591         init_8259A(1);
1592         if (timer_over_8254 > 0)
1593                 enable_8259A_irq(0);
1594
1595         pin1  = find_isa_irq_pin(0, mp_INT);
1596         apic1 = find_isa_irq_apic(0, mp_INT);
1597         pin2  = ioapic_i8259.pin;
1598         apic2 = ioapic_i8259.apic;
1599
1600         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1601                 vector, apic1, pin1, apic2, pin2);
1602
1603         if (pin1 != -1) {
1604                 /*
1605                  * Ok, does IRQ0 through the IOAPIC work?
1606                  */
1607                 unmask_IO_APIC_irq(0);
1608                 if (!no_timer_check && timer_irq_works()) {
1609                         nmi_watchdog_default();
1610                         if (nmi_watchdog == NMI_IO_APIC) {
1611                                 disable_8259A_irq(0);
1612                                 setup_nmi();
1613                                 enable_8259A_irq(0);
1614                         }
1615                         if (disable_timer_pin_1 > 0)
1616                                 clear_IO_APIC_pin(0, pin1);
1617                         return;
1618                 }
1619                 clear_IO_APIC_pin(apic1, pin1);
1620                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1621                                 "connected to IO-APIC\n");
1622         }
1623
1624         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1625                                 "through the 8259A ... ");
1626         if (pin2 != -1) {
1627                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1628                         apic2, pin2);
1629                 /*
1630                  * legacy devices should be connected to IO APIC #0
1631                  */
1632                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1633                 if (timer_irq_works()) {
1634                         apic_printk(APIC_VERBOSE," works.\n");
1635                         nmi_watchdog_default();
1636                         if (nmi_watchdog == NMI_IO_APIC) {
1637                                 setup_nmi();
1638                         }
1639                         return;
1640                 }
1641                 /*
1642                  * Cleanup, just in case ...
1643                  */
1644                 clear_IO_APIC_pin(apic2, pin2);
1645         }
1646         apic_printk(APIC_VERBOSE," failed.\n");
1647
1648         if (nmi_watchdog == NMI_IO_APIC) {
1649                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1650                 nmi_watchdog = 0;
1651         }
1652
1653         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1654
1655         disable_8259A_irq(0);
1656         irq_desc[0].chip = &lapic_irq_type;
1657         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1658         enable_8259A_irq(0);
1659
1660         if (timer_irq_works()) {
1661                 apic_printk(APIC_VERBOSE," works.\n");
1662                 return;
1663         }
1664         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1665         apic_printk(APIC_VERBOSE," failed.\n");
1666
1667         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1668
1669         init_8259A(0);
1670         make_8259A_irq(0);
1671         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1672
1673         unlock_ExtINT_logic();
1674
1675         if (timer_irq_works()) {
1676                 apic_printk(APIC_VERBOSE," works.\n");
1677                 return;
1678         }
1679         apic_printk(APIC_VERBOSE," failed :(.\n");
1680         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1681 }
1682
1683 static int __init notimercheck(char *s)
1684 {
1685         no_timer_check = 1;
1686         return 1;
1687 }
1688 __setup("no_timer_check", notimercheck);
1689
1690 /*
1691  *
1692  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1693  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1694  *   Linux doesn't really care, as it's not actually used
1695  *   for any interrupt handling anyway.
1696  */
1697 #define PIC_IRQS        (1<<2)
1698
1699 void __init setup_IO_APIC(void)
1700 {
1701         enable_IO_APIC();
1702
1703         if (acpi_ioapic)
1704                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1705         else
1706                 io_apic_irqs = ~PIC_IRQS;
1707
1708         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1709
1710         sync_Arb_IDs();
1711         setup_IO_APIC_irqs();
1712         init_IO_APIC_traps();
1713         check_timer();
1714         if (!acpi_ioapic)
1715                 print_IO_APIC();
1716 }
1717
1718 struct sysfs_ioapic_data {
1719         struct sys_device dev;
1720         struct IO_APIC_route_entry entry[0];
1721 };
1722 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1723
1724 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1725 {
1726         struct IO_APIC_route_entry *entry;
1727         struct sysfs_ioapic_data *data;
1728         int i;
1729
1730         data = container_of(dev, struct sysfs_ioapic_data, dev);
1731         entry = data->entry;
1732         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1733                 *entry = ioapic_read_entry(dev->id, i);
1734
1735         return 0;
1736 }
1737
1738 static int ioapic_resume(struct sys_device *dev)
1739 {
1740         struct IO_APIC_route_entry *entry;
1741         struct sysfs_ioapic_data *data;
1742         unsigned long flags;
1743         union IO_APIC_reg_00 reg_00;
1744         int i;
1745
1746         data = container_of(dev, struct sysfs_ioapic_data, dev);
1747         entry = data->entry;
1748
1749         spin_lock_irqsave(&ioapic_lock, flags);
1750         reg_00.raw = io_apic_read(dev->id, 0);
1751         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1752                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1753                 io_apic_write(dev->id, 0, reg_00.raw);
1754         }
1755         spin_unlock_irqrestore(&ioapic_lock, flags);
1756         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1757                 ioapic_write_entry(dev->id, i, entry[i]);
1758
1759         return 0;
1760 }
1761
1762 static struct sysdev_class ioapic_sysdev_class = {
1763         set_kset_name("ioapic"),
1764         .suspend = ioapic_suspend,
1765         .resume = ioapic_resume,
1766 };
1767
1768 static int __init ioapic_init_sysfs(void)
1769 {
1770         struct sys_device * dev;
1771         int i, size, error = 0;
1772
1773         error = sysdev_class_register(&ioapic_sysdev_class);
1774         if (error)
1775                 return error;
1776
1777         for (i = 0; i < nr_ioapics; i++ ) {
1778                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1779                         * sizeof(struct IO_APIC_route_entry);
1780                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1781                 if (!mp_ioapic_data[i]) {
1782                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1783                         continue;
1784                 }
1785                 memset(mp_ioapic_data[i], 0, size);
1786                 dev = &mp_ioapic_data[i]->dev;
1787                 dev->id = i;
1788                 dev->cls = &ioapic_sysdev_class;
1789                 error = sysdev_register(dev);
1790                 if (error) {
1791                         kfree(mp_ioapic_data[i]);
1792                         mp_ioapic_data[i] = NULL;
1793                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1794                         continue;
1795                 }
1796         }
1797
1798         return 0;
1799 }
1800
1801 device_initcall(ioapic_init_sysfs);
1802
1803 /*
1804  * Dynamic irq allocate and deallocation
1805  */
1806 int create_irq(void)
1807 {
1808         /* Allocate an unused irq */
1809         int irq;
1810         int new;
1811         int vector = 0;
1812         unsigned long flags;
1813         cpumask_t mask;
1814
1815         irq = -ENOSPC;
1816         spin_lock_irqsave(&vector_lock, flags);
1817         for (new = (NR_IRQS - 1); new >= 0; new--) {
1818                 if (platform_legacy_irq(new))
1819                         continue;
1820                 if (irq_vector[new] != 0)
1821                         continue;
1822                 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1823                 if (likely(vector > 0))
1824                         irq = new;
1825                 break;
1826         }
1827         spin_unlock_irqrestore(&vector_lock, flags);
1828
1829         if (irq >= 0) {
1830                 dynamic_irq_init(irq);
1831         }
1832         return irq;
1833 }
1834
1835 void destroy_irq(unsigned int irq)
1836 {
1837         unsigned long flags;
1838
1839         dynamic_irq_cleanup(irq);
1840
1841         spin_lock_irqsave(&vector_lock, flags);
1842         irq_vector[irq] = 0;
1843         spin_unlock_irqrestore(&vector_lock, flags);
1844 }
1845
1846 /*
1847  * MSI mesage composition
1848  */
1849 #ifdef CONFIG_PCI_MSI
1850 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1851 {
1852         int vector;
1853         unsigned dest;
1854         cpumask_t tmp;
1855
1856         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1857         if (vector >= 0) {
1858                 dest = cpu_mask_to_apicid(tmp);
1859
1860                 msg->address_hi = MSI_ADDR_BASE_HI;
1861                 msg->address_lo =
1862                         MSI_ADDR_BASE_LO |
1863                         ((INT_DEST_MODE == 0) ?
1864                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1865                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1866                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1867                                 MSI_ADDR_REDIRECTION_CPU:
1868                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1869                         MSI_ADDR_DEST_ID(dest);
1870
1871                 msg->data =
1872                         MSI_DATA_TRIGGER_EDGE |
1873                         MSI_DATA_LEVEL_ASSERT |
1874                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1875                                 MSI_DATA_DELIVERY_FIXED:
1876                                 MSI_DATA_DELIVERY_LOWPRI) |
1877                         MSI_DATA_VECTOR(vector);
1878         }
1879         return vector;
1880 }
1881
1882 #ifdef CONFIG_SMP
1883 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1884 {
1885         struct msi_msg msg;
1886         unsigned int dest;
1887         cpumask_t tmp;
1888         int vector;
1889
1890         cpus_and(tmp, mask, cpu_online_map);
1891         if (cpus_empty(tmp))
1892                 tmp = TARGET_CPUS;
1893
1894         cpus_and(mask, tmp, CPU_MASK_ALL);
1895
1896         vector = assign_irq_vector(irq, mask, &tmp);
1897         if (vector < 0)
1898                 return;
1899
1900         dest = cpu_mask_to_apicid(tmp);
1901
1902         read_msi_msg(irq, &msg);
1903
1904         msg.data &= ~MSI_DATA_VECTOR_MASK;
1905         msg.data |= MSI_DATA_VECTOR(vector);
1906         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1907         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1908
1909         write_msi_msg(irq, &msg);
1910         set_native_irq_info(irq, mask);
1911 }
1912 #endif /* CONFIG_SMP */
1913
1914 /*
1915  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1916  * which implement the MSI or MSI-X Capability Structure.
1917  */
1918 static struct irq_chip msi_chip = {
1919         .name           = "PCI-MSI",
1920         .unmask         = unmask_msi_irq,
1921         .mask           = mask_msi_irq,
1922         .ack            = ack_apic_edge,
1923 #ifdef CONFIG_SMP
1924         .set_affinity   = set_msi_irq_affinity,
1925 #endif
1926         .retrigger      = ioapic_retrigger_irq,
1927 };
1928
1929 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1930 {
1931         struct msi_msg msg;
1932         int ret;
1933         ret = msi_compose_msg(dev, irq, &msg);
1934         if (ret < 0)
1935                 return ret;
1936
1937         write_msi_msg(irq, &msg);
1938
1939         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1940
1941         return 0;
1942 }
1943
1944 void arch_teardown_msi_irq(unsigned int irq)
1945 {
1946         return;
1947 }
1948
1949 #endif /* CONFIG_PCI_MSI */
1950
1951 /*
1952  * Hypertransport interrupt support
1953  */
1954 #ifdef CONFIG_HT_IRQ
1955
1956 #ifdef CONFIG_SMP
1957
1958 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1959 {
1960         struct ht_irq_msg msg;
1961         fetch_ht_irq_msg(irq, &msg);
1962
1963         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1964         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1965
1966         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1967         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1968
1969         write_ht_irq_msg(irq, &msg);
1970 }
1971
1972 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1973 {
1974         unsigned int dest;
1975         cpumask_t tmp;
1976         int vector;
1977
1978         cpus_and(tmp, mask, cpu_online_map);
1979         if (cpus_empty(tmp))
1980                 tmp = TARGET_CPUS;
1981
1982         cpus_and(mask, tmp, CPU_MASK_ALL);
1983
1984         vector = assign_irq_vector(irq, mask, &tmp);
1985         if (vector < 0)
1986                 return;
1987
1988         dest = cpu_mask_to_apicid(tmp);
1989
1990         target_ht_irq(irq, dest, vector);
1991         set_native_irq_info(irq, mask);
1992 }
1993 #endif
1994
1995 static struct irq_chip ht_irq_chip = {
1996         .name           = "PCI-HT",
1997         .mask           = mask_ht_irq,
1998         .unmask         = unmask_ht_irq,
1999         .ack            = ack_apic_edge,
2000 #ifdef CONFIG_SMP
2001         .set_affinity   = set_ht_irq_affinity,
2002 #endif
2003         .retrigger      = ioapic_retrigger_irq,
2004 };
2005
2006 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2007 {
2008         int vector;
2009         cpumask_t tmp;
2010
2011         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2012         if (vector >= 0) {
2013                 struct ht_irq_msg msg;
2014                 unsigned dest;
2015
2016                 dest = cpu_mask_to_apicid(tmp);
2017
2018                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2019
2020                 msg.address_lo =
2021                         HT_IRQ_LOW_BASE |
2022                         HT_IRQ_LOW_DEST_ID(dest) |
2023                         HT_IRQ_LOW_VECTOR(vector) |
2024                         ((INT_DEST_MODE == 0) ?
2025                                 HT_IRQ_LOW_DM_PHYSICAL :
2026                                 HT_IRQ_LOW_DM_LOGICAL) |
2027                         HT_IRQ_LOW_RQEOI_EDGE |
2028                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2029                                 HT_IRQ_LOW_MT_FIXED :
2030                                 HT_IRQ_LOW_MT_ARBITRATED) |
2031                         HT_IRQ_LOW_IRQ_MASKED;
2032
2033                 write_ht_irq_msg(irq, &msg);
2034
2035                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2036                                               handle_edge_irq, "edge");
2037         }
2038         return vector;
2039 }
2040 #endif /* CONFIG_HT_IRQ */
2041
2042 /* --------------------------------------------------------------------------
2043                           ACPI-based IOAPIC Configuration
2044    -------------------------------------------------------------------------- */
2045
2046 #ifdef CONFIG_ACPI
2047
2048 #define IO_APIC_MAX_ID          0xFE
2049
2050 int __init io_apic_get_redir_entries (int ioapic)
2051 {
2052         union IO_APIC_reg_01    reg_01;
2053         unsigned long flags;
2054
2055         spin_lock_irqsave(&ioapic_lock, flags);
2056         reg_01.raw = io_apic_read(ioapic, 1);
2057         spin_unlock_irqrestore(&ioapic_lock, flags);
2058
2059         return reg_01.bits.entries;
2060 }
2061
2062
2063 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2064 {
2065         struct IO_APIC_route_entry entry;
2066         unsigned long flags;
2067         int vector;
2068         cpumask_t mask;
2069
2070         if (!IO_APIC_IRQ(irq)) {
2071                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2072                         ioapic);
2073                 return -EINVAL;
2074         }
2075
2076         /*
2077          * IRQs < 16 are already in the irq_2_pin[] map
2078          */
2079         if (irq >= 16)
2080                 add_pin_to_irq(irq, ioapic, pin);
2081
2082
2083         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
2084         if (vector < 0)
2085                 return vector;
2086
2087         /*
2088          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2089          * Note that we mask (disable) IRQs now -- these get enabled when the
2090          * corresponding device driver registers for this IRQ.
2091          */
2092
2093         memset(&entry,0,sizeof(entry));
2094
2095         entry.delivery_mode = INT_DELIVERY_MODE;
2096         entry.dest_mode = INT_DEST_MODE;
2097         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
2098         entry.trigger = triggering;
2099         entry.polarity = polarity;
2100         entry.mask = 1;                                  /* Disabled (masked) */
2101         entry.vector = vector & 0xff;
2102
2103         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2104                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2105                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2106                triggering, polarity);
2107
2108         ioapic_register_intr(irq, entry.vector, triggering);
2109
2110         if (!ioapic && (irq < 16))
2111                 disable_8259A_irq(irq);
2112
2113         ioapic_write_entry(ioapic, pin, entry);
2114
2115         spin_lock_irqsave(&ioapic_lock, flags);
2116         set_native_irq_info(irq, TARGET_CPUS);
2117         spin_unlock_irqrestore(&ioapic_lock, flags);
2118
2119         return 0;
2120 }
2121
2122 #endif /* CONFIG_ACPI */
2123
2124
2125 /*
2126  * This function currently is only a helper for the i386 smp boot process where
2127  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2128  * so mask in all cases should simply be TARGET_CPUS
2129  */
2130 #ifdef CONFIG_SMP
2131 void __init setup_ioapic_dest(void)
2132 {
2133         int pin, ioapic, irq, irq_entry;
2134
2135         if (skip_ioapic_setup == 1)
2136                 return;
2137
2138         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2139                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2140                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2141                         if (irq_entry == -1)
2142                                 continue;
2143                         irq = pin_2_irq(irq_entry, ioapic, pin);
2144                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2145                 }
2146
2147         }
2148 }
2149 #endif