2 * mrst.c: Intel Moorestown platform specific setup code
4 * (C) Copyright 2008 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) "mrst: " fmt
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/sfi.h>
18 #include <linux/intel_pmic_gpio.h>
19 #include <linux/spi/spi.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca953x.h>
22 #include <linux/gpio_keys.h>
23 #include <linux/input.h>
24 #include <linux/platform_device.h>
25 #include <linux/irq.h>
26 #include <linux/module.h>
27 #include <linux/notifier.h>
29 #include <asm/setup.h>
30 #include <asm/mpspec_def.h>
31 #include <asm/hw_irq.h>
33 #include <asm/io_apic.h>
35 #include <asm/mrst-vrtc.h>
37 #include <asm/i8259.h>
38 #include <asm/intel_scu_ipc.h>
39 #include <asm/apb_timer.h>
40 #include <asm/reboot.h>
43 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
44 * cmdline option x86_mrst_timer can be used to override the configuration
45 * to prefer one or the other.
46 * at runtime, there are basically three timer configurations:
47 * 1. per cpu apbt clock only
48 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
49 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
51 * by default (without cmdline option), platform code first detects cpu type
52 * to see if we are on lincroft or penwell, then set up both lapic or apbt
54 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
55 * config #3 is supported but not recommended on medfield.
57 * rating and feature summary:
58 * lapic (with C3STOP) --------- 100
59 * apbt (always-on) ------------ 110
60 * lapic (always-on,ARAT) ------ 150
63 __cpuinitdata enum mrst_timer_options mrst_timer_options;
65 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
66 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
67 enum mrst_cpu_type __mrst_cpu_chip;
68 EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
72 struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
73 EXPORT_SYMBOL_GPL(sfi_mrtc_array);
76 /* parse all the mtimer info to a static mtimer array */
77 static int __init sfi_parse_mtmr(struct sfi_table_header *table)
79 struct sfi_table_simple *sb;
80 struct sfi_timer_table_entry *pentry;
81 struct mpc_intsrc mp_irq;
84 sb = (struct sfi_table_simple *)table;
85 if (!sfi_mtimer_num) {
86 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
87 struct sfi_timer_table_entry);
88 pentry = (struct sfi_timer_table_entry *) sb->pentry;
89 totallen = sfi_mtimer_num * sizeof(*pentry);
90 memcpy(sfi_mtimer_array, pentry, totallen);
93 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
94 pentry = sfi_mtimer_array;
95 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
96 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
97 " irq = %d\n", totallen, (u32)pentry->phys_addr,
98 pentry->freq_hz, pentry->irq);
101 mp_irq.type = MP_INTSRC;
102 mp_irq.irqtype = mp_INT;
103 /* triggering mode edge bit 2-3, active high polarity bit 0-1 */
105 mp_irq.srcbus = MP_BUS_ISA;
106 mp_irq.srcbusirq = pentry->irq; /* IRQ */
107 mp_irq.dstapic = MP_APIC_ALL;
108 mp_irq.dstirq = pentry->irq;
109 mp_save_irq(&mp_irq);
115 struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
118 if (hint < sfi_mtimer_num) {
119 if (!sfi_mtimer_usage[hint]) {
120 pr_debug("hint taken for timer %d irq %d\n",\
121 hint, sfi_mtimer_array[hint].irq);
122 sfi_mtimer_usage[hint] = 1;
123 return &sfi_mtimer_array[hint];
126 /* take the first timer available */
127 for (i = 0; i < sfi_mtimer_num;) {
128 if (!sfi_mtimer_usage[i]) {
129 sfi_mtimer_usage[i] = 1;
130 return &sfi_mtimer_array[i];
137 void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
140 for (i = 0; i < sfi_mtimer_num;) {
141 if (mtmr->irq == sfi_mtimer_array[i].irq) {
142 sfi_mtimer_usage[i] = 0;
149 /* parse all the mrtc info to a global mrtc array */
150 int __init sfi_parse_mrtc(struct sfi_table_header *table)
152 struct sfi_table_simple *sb;
153 struct sfi_rtc_table_entry *pentry;
154 struct mpc_intsrc mp_irq;
158 sb = (struct sfi_table_simple *)table;
160 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
161 struct sfi_rtc_table_entry);
162 pentry = (struct sfi_rtc_table_entry *)sb->pentry;
163 totallen = sfi_mrtc_num * sizeof(*pentry);
164 memcpy(sfi_mrtc_array, pentry, totallen);
167 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
168 pentry = sfi_mrtc_array;
169 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
170 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
171 totallen, (u32)pentry->phys_addr, pentry->irq);
172 mp_irq.type = MP_INTSRC;
173 mp_irq.irqtype = mp_INT;
174 mp_irq.irqflag = 0xf; /* level trigger and active low */
175 mp_irq.srcbus = MP_BUS_ISA;
176 mp_irq.srcbusirq = pentry->irq; /* IRQ */
177 mp_irq.dstapic = MP_APIC_ALL;
178 mp_irq.dstirq = pentry->irq;
179 mp_save_irq(&mp_irq);
184 static unsigned long __init mrst_calibrate_tsc(void)
186 unsigned long flags, fast_calibrate;
188 local_irq_save(flags);
189 fast_calibrate = apbt_quick_calibrate();
190 local_irq_restore(flags);
193 return fast_calibrate;
198 static void __init mrst_time_init(void)
200 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
201 switch (mrst_timer_options) {
202 case MRST_TIMER_APBT_ONLY:
204 case MRST_TIMER_LAPIC_APBT:
205 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
206 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
209 if (!boot_cpu_has(X86_FEATURE_ARAT))
211 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
212 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
215 /* we need at least one APB timer */
216 pre_init_apic_IRQ0();
220 static void __cpuinit mrst_arch_setup(void)
222 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
223 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
224 else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
225 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
227 pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
228 boot_cpu_data.x86, boot_cpu_data.x86_model);
229 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
231 pr_debug("Moorestown CPU %s identified\n",
232 (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
233 "Lincroft" : "Penwell");
236 /* MID systems don't have i8042 controller */
237 static int mrst_i8042_detect(void)
242 /* Reboot and power off are handled by the SCU on a MID device */
243 static void mrst_power_off(void)
245 intel_scu_ipc_simple_command(0xf1, 1);
248 static void mrst_reboot(void)
250 intel_scu_ipc_simple_command(0xf1, 0);
254 * Moorestown specific x86_init function overrides and early setup
257 void __init x86_mrst_early_setup(void)
259 x86_init.resources.probe_roms = x86_init_noop;
260 x86_init.resources.reserve_resources = x86_init_noop;
262 x86_init.timers.timer_init = mrst_time_init;
263 x86_init.timers.setup_percpu_clockev = x86_init_noop;
265 x86_init.irqs.pre_vector_init = x86_init_noop;
267 x86_init.oem.arch_setup = mrst_arch_setup;
269 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
271 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
272 x86_platform.i8042_detect = mrst_i8042_detect;
273 x86_init.timers.wallclock_init = mrst_rtc_init;
274 x86_init.pci.init = pci_mrst_init;
275 x86_init.pci.fixup_irqs = x86_init_noop;
277 legacy_pic = &null_legacy_pic;
279 /* Moorestown specific power_off/restart method */
280 pm_power_off = mrst_power_off;
281 machine_ops.emergency_restart = mrst_reboot;
283 /* Avoid searching for BIOS MP tables */
284 x86_init.mpparse.find_smp_config = x86_init_noop;
285 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
286 set_bit(MP_BUS_ISA, mp_bus_not_pci);
290 * if user does not want to use per CPU apb timer, just give it a lower rating
291 * than local apic timer and skip the late per cpu timer init.
293 static inline int __init setup_x86_mrst_timer(char *arg)
298 if (strcmp("apbt_only", arg) == 0)
299 mrst_timer_options = MRST_TIMER_APBT_ONLY;
300 else if (strcmp("lapic_and_apbt", arg) == 0)
301 mrst_timer_options = MRST_TIMER_LAPIC_APBT;
303 pr_warning("X86 MRST timer option %s not recognised"
304 " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
310 __setup("x86_mrst_timer=", setup_x86_mrst_timer);
313 * Parsing GPIO table first, since the DEVS table will need this table
314 * to map the pin name to the actual pin.
316 static struct sfi_gpio_table_entry *gpio_table;
317 static int gpio_num_entry;
319 static int __init sfi_parse_gpio(struct sfi_table_header *table)
321 struct sfi_table_simple *sb;
322 struct sfi_gpio_table_entry *pentry;
327 sb = (struct sfi_table_simple *)table;
328 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
329 pentry = (struct sfi_gpio_table_entry *)sb->pentry;
331 gpio_table = (struct sfi_gpio_table_entry *)
332 kmalloc(num * sizeof(*pentry), GFP_KERNEL);
335 memcpy(gpio_table, pentry, num * sizeof(*pentry));
336 gpio_num_entry = num;
338 pr_debug("GPIO pin info:\n");
339 for (i = 0; i < num; i++, pentry++)
340 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
342 pentry->controller_name,
348 static int get_gpio_by_name(const char *name)
350 struct sfi_gpio_table_entry *pentry = gpio_table;
355 for (i = 0; i < gpio_num_entry; i++, pentry++) {
356 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
357 return pentry->pin_no;
363 * Here defines the array of devices platform data that IAFW would export
364 * through SFI "DEVS" table, we use name and type to match the device and
368 char name[SFI_NAME_LEN + 1];
371 void *(*get_platform_data)(void *info);
374 /* the offset for the mapping of global gpio pin to irq */
375 #define MRST_IRQ_OFFSET 0x100
377 static void __init *pmic_gpio_platform_data(void *info)
379 static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
380 int gpio_base = get_gpio_by_name("pmic_gpio_base");
384 pmic_gpio_pdata.gpio_base = gpio_base;
385 pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
386 pmic_gpio_pdata.gpiointr = 0xffffeff8;
388 return &pmic_gpio_pdata;
391 static void __init *max3111_platform_data(void *info)
393 struct spi_board_info *spi_info = info;
394 int intr = get_gpio_by_name("max3111_int");
398 spi_info->irq = intr + MRST_IRQ_OFFSET;
402 /* we have multiple max7315 on the board ... */
403 #define MAX7315_NUM 2
404 static void __init *max7315_platform_data(void *info)
406 static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
408 struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
409 struct i2c_board_info *i2c_info = info;
411 char base_pin_name[SFI_NAME_LEN + 1];
412 char intr_pin_name[SFI_NAME_LEN + 1];
414 if (nr == MAX7315_NUM) {
415 pr_err("too many max7315s, we only support %d\n",
419 /* we have several max7315 on the board, we only need load several
420 * instances of the same pca953x driver to cover them
422 strcpy(i2c_info->type, "max7315");
424 sprintf(base_pin_name, "max7315_%d_base", nr);
425 sprintf(intr_pin_name, "max7315_%d_int", nr);
427 strcpy(base_pin_name, "max7315_base");
428 strcpy(intr_pin_name, "max7315_int");
431 gpio_base = get_gpio_by_name(base_pin_name);
432 intr = get_gpio_by_name(intr_pin_name);
436 max7315->gpio_base = gpio_base;
438 i2c_info->irq = intr + MRST_IRQ_OFFSET;
439 max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
442 max7315->irq_base = -1;
447 static void __init *emc1403_platform_data(void *info)
449 static short intr2nd_pdata;
450 struct i2c_board_info *i2c_info = info;
451 int intr = get_gpio_by_name("thermal_int");
452 int intr2nd = get_gpio_by_name("thermal_alert");
454 if (intr == -1 || intr2nd == -1)
457 i2c_info->irq = intr + MRST_IRQ_OFFSET;
458 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
460 return &intr2nd_pdata;
463 static void __init *lis331dl_platform_data(void *info)
465 static short intr2nd_pdata;
466 struct i2c_board_info *i2c_info = info;
467 int intr = get_gpio_by_name("accel_int");
468 int intr2nd = get_gpio_by_name("accel_2");
470 if (intr == -1 || intr2nd == -1)
473 i2c_info->irq = intr + MRST_IRQ_OFFSET;
474 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
476 return &intr2nd_pdata;
479 static void __init *no_platform_data(void *info)
484 static const struct devs_id __initconst device_ids[] = {
485 {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
486 {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
487 {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
488 {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
489 {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
490 {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
491 {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
492 {"msic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
496 #define MAX_IPCDEVS 24
497 static struct platform_device *ipc_devs[MAX_IPCDEVS];
498 static int ipc_next_dev;
500 #define MAX_SCU_SPI 24
501 static struct spi_board_info *spi_devs[MAX_SCU_SPI];
502 static int spi_next_dev;
504 #define MAX_SCU_I2C 24
505 static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
506 static int i2c_bus[MAX_SCU_I2C];
507 static int i2c_next_dev;
509 static void __init intel_scu_device_register(struct platform_device *pdev)
511 if(ipc_next_dev == MAX_IPCDEVS)
512 pr_err("too many SCU IPC devices");
514 ipc_devs[ipc_next_dev++] = pdev;
517 static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
519 struct spi_board_info *new_dev;
521 if (spi_next_dev == MAX_SCU_SPI) {
522 pr_err("too many SCU SPI devices");
526 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
528 pr_err("failed to alloc mem for delayed spi dev %s\n",
532 memcpy(new_dev, sdev, sizeof(*sdev));
534 spi_devs[spi_next_dev++] = new_dev;
537 static void __init intel_scu_i2c_device_register(int bus,
538 struct i2c_board_info *idev)
540 struct i2c_board_info *new_dev;
542 if (i2c_next_dev == MAX_SCU_I2C) {
543 pr_err("too many SCU I2C devices");
547 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
549 pr_err("failed to alloc mem for delayed i2c dev %s\n",
553 memcpy(new_dev, idev, sizeof(*idev));
555 i2c_bus[i2c_next_dev] = bus;
556 i2c_devs[i2c_next_dev++] = new_dev;
559 BLOCKING_NOTIFIER_HEAD(intel_scu_notifier);
560 EXPORT_SYMBOL_GPL(intel_scu_notifier);
562 /* Called by IPC driver */
563 void intel_scu_devices_create(void)
567 for (i = 0; i < ipc_next_dev; i++)
568 platform_device_add(ipc_devs[i]);
570 for (i = 0; i < spi_next_dev; i++)
571 spi_register_board_info(spi_devs[i], 1);
573 for (i = 0; i < i2c_next_dev; i++) {
574 struct i2c_adapter *adapter;
575 struct i2c_client *client;
577 adapter = i2c_get_adapter(i2c_bus[i]);
579 client = i2c_new_device(adapter, i2c_devs[i]);
581 pr_err("can't create i2c device %s\n",
584 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
586 intel_scu_notifier_post(SCU_AVAILABLE, 0L);
588 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
590 /* Called by IPC driver */
591 void intel_scu_devices_destroy(void)
595 intel_scu_notifier_post(SCU_DOWN, 0L);
597 for (i = 0; i < ipc_next_dev; i++)
598 platform_device_del(ipc_devs[i]);
600 EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
602 static void __init install_irq_resource(struct platform_device *pdev, int irq)
604 /* Single threaded */
605 static struct resource __initdata res = {
607 .flags = IORESOURCE_IRQ,
610 platform_device_add_resources(pdev, &res, 1);
613 static void __init sfi_handle_ipc_dev(struct platform_device *pdev)
615 const struct devs_id *dev = device_ids;
618 while (dev->name[0]) {
619 if (dev->type == SFI_DEV_TYPE_IPC &&
620 !strncmp(dev->name, pdev->name, SFI_NAME_LEN)) {
621 pdata = dev->get_platform_data(pdev);
626 pdev->dev.platform_data = pdata;
627 intel_scu_device_register(pdev);
630 static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
632 const struct devs_id *dev = device_ids;
635 while (dev->name[0]) {
636 if (dev->type == SFI_DEV_TYPE_SPI &&
637 !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
638 pdata = dev->get_platform_data(spi_info);
643 spi_info->platform_data = pdata;
645 intel_scu_spi_device_register(spi_info);
647 spi_register_board_info(spi_info, 1);
650 static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
652 const struct devs_id *dev = device_ids;
655 while (dev->name[0]) {
656 if (dev->type == SFI_DEV_TYPE_I2C &&
657 !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
658 pdata = dev->get_platform_data(i2c_info);
663 i2c_info->platform_data = pdata;
666 intel_scu_i2c_device_register(bus, i2c_info);
668 i2c_register_board_info(bus, i2c_info, 1);
672 static int __init sfi_parse_devs(struct sfi_table_header *table)
674 struct sfi_table_simple *sb;
675 struct sfi_device_table_entry *pentry;
676 struct spi_board_info spi_info;
677 struct i2c_board_info i2c_info;
678 struct platform_device *pdev;
681 struct io_apic_irq_attr irq_attr;
683 sb = (struct sfi_table_simple *)table;
684 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
685 pentry = (struct sfi_device_table_entry *)sb->pentry;
687 for (i = 0; i < num; i++, pentry++) {
688 int irq = pentry->irq;
690 if (irq != (u8)0xff) { /* native RTE case */
691 /* these SPI2 devices are not exposed to system as PCI
692 * devices, but they have separate RTE entry in IOAPIC
693 * so we have to enable them one by one here
695 ioapic = mp_find_ioapic(irq);
696 irq_attr.ioapic = ioapic;
697 irq_attr.ioapic_pin = irq;
698 irq_attr.trigger = 1;
699 irq_attr.polarity = 1;
700 io_apic_set_pci_routing(NULL, irq, &irq_attr);
702 irq = 0; /* No irq */
704 switch (pentry->type) {
705 case SFI_DEV_TYPE_IPC:
706 /* ID as IRQ is a hack that will go away */
707 pdev = platform_device_alloc(pentry->name, irq);
709 pr_err("out of memory for SFI platform device '%s'.\n",
713 install_irq_resource(pdev, irq);
714 pr_debug("info[%2d]: IPC bus, name = %16.16s, "
715 "irq = 0x%2x\n", i, pentry->name, irq);
716 sfi_handle_ipc_dev(pdev);
718 case SFI_DEV_TYPE_SPI:
719 memset(&spi_info, 0, sizeof(spi_info));
720 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
722 spi_info.bus_num = pentry->host_num;
723 spi_info.chip_select = pentry->addr;
724 spi_info.max_speed_hz = pentry->max_freq;
725 pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
726 "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
730 spi_info.max_speed_hz,
731 spi_info.chip_select);
732 sfi_handle_spi_dev(&spi_info);
734 case SFI_DEV_TYPE_I2C:
735 memset(&i2c_info, 0, sizeof(i2c_info));
736 bus = pentry->host_num;
737 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
739 i2c_info.addr = pentry->addr;
740 pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
741 "irq = 0x%2x, addr = 0x%x\n", i, bus,
745 sfi_handle_i2c_dev(bus, &i2c_info);
747 case SFI_DEV_TYPE_UART:
748 case SFI_DEV_TYPE_HSI:
756 static int __init mrst_platform_init(void)
758 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
759 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
762 arch_initcall(mrst_platform_init);
765 * we will search these buttons in SFI GPIO table (by name)
766 * and register them dynamically. Please add all possible
767 * buttons here, we will shrink them if no GPIO found.
769 static struct gpio_keys_button gpio_button[] = {
770 {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000},
771 {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20},
772 {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20},
773 {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
774 {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
775 {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
776 {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
777 {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
778 {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
779 {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20},
782 static struct gpio_keys_platform_data mrst_gpio_keys = {
783 .buttons = gpio_button,
785 .nbuttons = -1, /* will fill it after search */
788 static struct platform_device pb_device = {
792 .platform_data = &mrst_gpio_keys,
797 * Shrink the non-existent buttons, register the gpio button
798 * device if there is some
800 static int __init pb_keys_init(void)
802 struct gpio_keys_button *gb = gpio_button;
803 int i, num, good = 0;
805 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
806 for (i = 0; i < num; i++) {
807 gb[i].gpio = get_gpio_by_name(gb[i].desc);
808 if (gb[i].gpio == -1)
817 mrst_gpio_keys.nbuttons = good;
818 return platform_device_register(&pb_device);
822 late_initcall(pb_keys_init);