arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  13  * @author Jason Yeh <jason.yeh@amd.com>
  14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  15  */
  16
  17 #include <linux/oprofile.h>
  18 #include <linux/device.h>
  19 #include <linux/pci.h>
  20 #include <linux/percpu.h>
  21
  22 #include <asm/ptrace.h>
  23 #include <asm/msr.h>
  24 #include <asm/nmi.h>
  25
  26 #include "op_x86_model.h"
  27 #include "op_counter.h"
  28
  29 #define NUM_COUNTERS 4
  30 #define NUM_CONTROLS 4
  31 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  32 #define NUM_VIRT_COUNTERS 32
  33 #define NUM_VIRT_CONTROLS 32
  34 #else
  35 #define NUM_VIRT_COUNTERS NUM_COUNTERS
  36 #define NUM_VIRT_CONTROLS NUM_CONTROLS
  37 #endif
  38
  39 #define OP_EVENT_MASK                   0x0FFF
  40 #define OP_CTR_OVERFLOW                 (1ULL<<31)
  41
  42 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
  43
  44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
  45
  46 #ifdef CONFIG_OPROFILE_IBS
  47
  48 /* IbsFetchCtl bits/masks */
  49 #define IBS_FETCH_RAND_EN               (1ULL<<57)
  50 #define IBS_FETCH_VAL                   (1ULL<<49)
  51 #define IBS_FETCH_ENABLE                (1ULL<<48)
  52 #define IBS_FETCH_CNT_MASK              0xFFFF0000ULL
  53
  54 /*IbsOpCtl bits */
  55 #define IBS_OP_CNT_CTL                  (1ULL<<19)
  56 #define IBS_OP_VAL                      (1ULL<<18)
  57 #define IBS_OP_ENABLE                   (1ULL<<17)
  58
  59 #define IBS_FETCH_SIZE                  6
  60 #define IBS_OP_SIZE                     12
  61
  62 static int has_ibs;     /* AMD Family10h and later */
  63
  64 struct op_ibs_config {
  65         unsigned long op_enabled;
  66         unsigned long fetch_enabled;
  67         unsigned long max_cnt_fetch;
  68         unsigned long max_cnt_op;
  69         unsigned long rand_en;
  70         unsigned long dispatched_ops;
  71 };
  72
  73 static struct op_ibs_config ibs_config;
  74
  75 #endif
  76
  77 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  78
  79 static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
  80 {
  81         int i;
  82
  83         for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
  84                 int hw_counter = op_x86_virt_to_phys(i);
  85                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
  86                         msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
  87                 else
  88                         msrs->multiplex[i].addr = 0;
  89         }
  90 }
  91
  92 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
  93                                struct op_msrs const * const msrs)
  94 {
  95         u64 val;
  96         int i;
  97
  98         /* enable active counters */
  99         for (i = 0; i < NUM_COUNTERS; ++i) {
 100                 int virt = op_x86_phys_to_virt(i);
 101                 if (!counter_config[virt].enabled)
 102                         continue;
 103                 rdmsrl(msrs->controls[i].addr, val);
 104                 val &= model->reserved;
 105                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 106                 wrmsrl(msrs->controls[i].addr, val);
 107         }
 108 }
 109
 110 #else
 111
 112 static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
 113
 114 #endif
 115
 116 /* functions for op_amd_spec */
 117
 118 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
 119 {
 120         int i;
 121
 122         for (i = 0; i < NUM_COUNTERS; i++) {
 123                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 124                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
 125                 else
 126                         msrs->counters[i].addr = 0;
 127         }
 128
 129         for (i = 0; i < NUM_CONTROLS; i++) {
 130                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
 131                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 132                 else
 133                         msrs->controls[i].addr = 0;
 134         }
 135
 136         op_mux_fill_in_addresses(msrs);
 137 }
 138
 139 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 140                               struct op_msrs const * const msrs)
 141 {
 142         u64 val;
 143         int i;
 144
 145         /* setup reset_value */
 146         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
 147                 if (counter_config[i].enabled)
 148                         reset_value[i] = counter_config[i].count;
 149                 else
 150                         reset_value[i] = 0;
 151         }
 152
 153         /* clear all counters */
 154         for (i = 0; i < NUM_CONTROLS; ++i) {
 155                 if (unlikely(!msrs->controls[i].addr))
 156                         continue;
 157                 rdmsrl(msrs->controls[i].addr, val);
 158                 val &= model->reserved;
 159                 wrmsrl(msrs->controls[i].addr, val);
 160         }
 161
 162         /* avoid a false detection of ctr overflows in NMI handler */
 163         for (i = 0; i < NUM_COUNTERS; ++i) {
 164                 if (unlikely(!msrs->counters[i].addr))
 165                         continue;
 166                 wrmsrl(msrs->counters[i].addr, -1LL);
 167         }
 168
 169         /* enable active counters */
 170         for (i = 0; i < NUM_COUNTERS; ++i) {
 171                 int virt = op_x86_phys_to_virt(i);
 172                 if (!counter_config[virt].enabled)
 173                         continue;
 174                 if (!msrs->counters[i].addr)
 175                         continue;
 176
 177                 /* setup counter registers */
 178                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 179
 180                 /* setup control registers */
 181                 rdmsrl(msrs->controls[i].addr, val);
 182                 val &= model->reserved;
 183                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 184                 wrmsrl(msrs->controls[i].addr, val);
 185         }
 186 }
 187
 188 #ifdef CONFIG_OPROFILE_IBS
 189
 190 static inline int
 191 op_amd_handle_ibs(struct pt_regs * const regs,
 192                   struct op_msrs const * const msrs)
 193 {
 194         u64 val, ctl;
 195         struct op_entry entry;
 196
 197         if (!has_ibs)
 198                 return 1;
 199
 200         if (ibs_config.fetch_enabled) {
 201                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 202                 if (ctl & IBS_FETCH_VAL) {
 203                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
 204                         oprofile_write_reserve(&entry, regs, val,
 205                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 206                         oprofile_add_data64(&entry, val);
 207                         oprofile_add_data64(&entry, ctl);
 208                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
 209                         oprofile_add_data64(&entry, val);
 210                         oprofile_write_commit(&entry);
 211
 212                         /* reenable the IRQ */
 213                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
 214                         ctl |= IBS_FETCH_ENABLE;
 215                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 216                 }
 217         }
 218
 219         if (ibs_config.op_enabled) {
 220                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
 221                 if (ctl & IBS_OP_VAL) {
 222                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
 223                         oprofile_write_reserve(&entry, regs, val,
 224                                                IBS_OP_CODE, IBS_OP_SIZE);
 225                         oprofile_add_data64(&entry, val);
 226                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
 227                         oprofile_add_data64(&entry, val);
 228                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
 229                         oprofile_add_data64(&entry, val);
 230                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
 231                         oprofile_add_data64(&entry, val);
 232                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
 233                         oprofile_add_data64(&entry, val);
 234                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
 235                         oprofile_add_data64(&entry, val);
 236                         oprofile_write_commit(&entry);
 237
 238                         /* reenable the IRQ */
 239                         ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
 240                         ctl |= IBS_OP_ENABLE;
 241                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
 242                 }
 243         }
 244
 245         return 1;
 246 }
 247
 248 static inline void op_amd_start_ibs(void)
 249 {
 250         u64 val;
 251         if (has_ibs && ibs_config.fetch_enabled) {
 252                 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 253                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
 254                 val |= IBS_FETCH_ENABLE;
 255                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
 256         }
 257
 258         if (has_ibs && ibs_config.op_enabled) {
 259                 val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
 260                 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
 261                 val |= IBS_OP_ENABLE;
 262                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
 263         }
 264 }
 265
 266 static void op_amd_stop_ibs(void)
 267 {
 268         if (has_ibs && ibs_config.fetch_enabled)
 269                 /* clear max count and enable */
 270                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 271
 272         if (has_ibs && ibs_config.op_enabled)
 273                 /* clear max count and enable */
 274                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 275 }
 276
 277 #else
 278
 279 static inline int op_amd_handle_ibs(struct pt_regs * const regs,
 280                                     struct op_msrs const * const msrs) { }
 281 static inline void op_amd_start_ibs(void) { }
 282 static inline void op_amd_stop_ibs(void) { }
 283
 284 #endif
 285
 286 static int op_amd_check_ctrs(struct pt_regs * const regs,
 287                              struct op_msrs const * const msrs)
 288 {
 289         u64 val;
 290         int i;
 291
 292         for (i = 0; i < NUM_COUNTERS; ++i) {
 293                 int virt = op_x86_phys_to_virt(i);
 294                 if (!reset_value[virt])
 295                         continue;
 296                 rdmsrl(msrs->counters[i].addr, val);
 297                 /* bit is clear if overflowed: */
 298                 if (val & OP_CTR_OVERFLOW)
 299                         continue;
 300                 oprofile_add_sample(regs, virt);
 301                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 302         }
 303
 304         op_amd_handle_ibs(regs, msrs);
 305
 306         /* See op_model_ppro.c */
 307         return 1;
 308 }
 309
 310 static void op_amd_start(struct op_msrs const * const msrs)
 311 {
 312         u64 val;
 313         int i;
 314
 315         for (i = 0; i < NUM_COUNTERS; ++i) {
 316                 if (!reset_value[op_x86_phys_to_virt(i)])
 317                         continue;
 318                 rdmsrl(msrs->controls[i].addr, val);
 319                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 320                 wrmsrl(msrs->controls[i].addr, val);
 321         }
 322
 323         op_amd_start_ibs();
 324 }
 325
 326 static void op_amd_stop(struct op_msrs const * const msrs)
 327 {
 328         u64 val;
 329         int i;
 330
 331         /*
 332          * Subtle: stop on all counters to avoid race with setting our
 333          * pm callback
 334          */
 335         for (i = 0; i < NUM_COUNTERS; ++i) {
 336                 if (!reset_value[op_x86_phys_to_virt(i)])
 337                         continue;
 338                 rdmsrl(msrs->controls[i].addr, val);
 339                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 340                 wrmsrl(msrs->controls[i].addr, val);
 341         }
 342
 343         op_amd_stop_ibs();
 344 }
 345
 346 static void op_amd_shutdown(struct op_msrs const * const msrs)
 347 {
 348         int i;
 349
 350         for (i = 0; i < NUM_COUNTERS; ++i) {
 351                 if (msrs->counters[i].addr)
 352                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 353         }
 354         for (i = 0; i < NUM_CONTROLS; ++i) {
 355                 if (msrs->controls[i].addr)
 356                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 357         }
 358 }
 359
 360 #ifdef CONFIG_OPROFILE_IBS
 361
 362 static u8 ibs_eilvt_off;
 363
 364 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 365 {
 366         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 367 }
 368
 369 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 370 {
 371         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 372 }
 373
 374 static int init_ibs_nmi(void)
 375 {
 376 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 377 #define IBSCTL                          0x1cc
 378         struct pci_dev *cpu_cfg;
 379         int nodes;
 380         u32 value = 0;
 381
 382         /* per CPU setup */
 383         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 384
 385         nodes = 0;
 386         cpu_cfg = NULL;
 387         do {
 388                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 389                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 390                                          cpu_cfg);
 391                 if (!cpu_cfg)
 392                         break;
 393                 ++nodes;
 394                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 395                                        | IBSCTL_LVTOFFSETVAL);
 396                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 397                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 398                         pci_dev_put(cpu_cfg);
 399                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 400                                 "IBSCTL = 0x%08x", value);
 401                         return 1;
 402                 }
 403         } while (1);
 404
 405         if (!nodes) {
 406                 printk(KERN_DEBUG "No CPU node configured for IBS");
 407                 return 1;
 408         }
 409
 410 #ifdef CONFIG_NUMA
 411         /* Sanity check */
 412         /* Works only for 64bit with proper numa implementation. */
 413         if (nodes != num_possible_nodes()) {
 414                 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
 415                         "found: %d, expected %d",
 416                         nodes, num_possible_nodes());
 417                 return 1;
 418         }
 419 #endif
 420         return 0;
 421 }
 422
 423 /* uninitialize the APIC for the IBS interrupts if needed */
 424 static void clear_ibs_nmi(void)
 425 {
 426         if (has_ibs)
 427                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 428 }
 429
 430 /* initialize the APIC for the IBS interrupts if available */
 431 static void ibs_init(void)
 432 {
 433         has_ibs = boot_cpu_has(X86_FEATURE_IBS);
 434
 435         if (!has_ibs)
 436                 return;
 437
 438         if (init_ibs_nmi()) {
 439                 has_ibs = 0;
 440                 return;
 441         }
 442
 443         printk(KERN_INFO "oprofile: AMD IBS detected\n");
 444 }
 445
 446 static void ibs_exit(void)
 447 {
 448         if (!has_ibs)
 449                 return;
 450
 451         clear_ibs_nmi();
 452 }
 453
 454 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 455
 456 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 457 {
 458         struct dentry *dir;
 459         int ret = 0;
 460
 461         /* architecture specific files */
 462         if (create_arch_files)
 463                 ret = create_arch_files(sb, root);
 464
 465         if (ret)
 466                 return ret;
 467
 468         if (!has_ibs)
 469                 return ret;
 470
 471         /* model specific files */
 472
 473         /* setup some reasonable defaults */
 474         ibs_config.max_cnt_fetch = 250000;
 475         ibs_config.fetch_enabled = 0;
 476         ibs_config.max_cnt_op = 250000;
 477         ibs_config.op_enabled = 0;
 478         ibs_config.dispatched_ops = 1;
 479
 480         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 481         oprofilefs_create_ulong(sb, dir, "enable",
 482                                 &ibs_config.fetch_enabled);
 483         oprofilefs_create_ulong(sb, dir, "max_count",
 484                                 &ibs_config.max_cnt_fetch);
 485         oprofilefs_create_ulong(sb, dir, "rand_enable",
 486                                 &ibs_config.rand_en);
 487
 488         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 489         oprofilefs_create_ulong(sb, dir, "enable",
 490                                 &ibs_config.op_enabled);
 491         oprofilefs_create_ulong(sb, dir, "max_count",
 492                                 &ibs_config.max_cnt_op);
 493         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 494                                 &ibs_config.dispatched_ops);
 495
 496         return 0;
 497 }
 498
 499 static int op_amd_init(struct oprofile_operations *ops)
 500 {
 501         ibs_init();
 502         create_arch_files = ops->create_files;
 503         ops->create_files = setup_ibs_files;
 504         return 0;
 505 }
 506
 507 static void op_amd_exit(void)
 508 {
 509         ibs_exit();
 510 }
 511
 512 #else
 513
 514 /* no IBS support */
 515
 516 static int op_amd_init(struct oprofile_operations *ops)
 517 {
 518         return 0;
 519 }
 520
 521 static void op_amd_exit(void) {}
 522
 523 #endif /* CONFIG_OPROFILE_IBS */
 524
 525 struct op_x86_model_spec op_amd_spec = {
 526         .num_counters           = NUM_COUNTERS,
 527         .num_controls           = NUM_CONTROLS,
 528         .num_virt_counters      = NUM_VIRT_COUNTERS,
 529         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
 530         .event_mask             = OP_EVENT_MASK,
 531         .init                   = op_amd_init,
 532         .exit                   = op_amd_exit,
 533         .fill_in_addresses      = &op_amd_fill_in_addresses,
 534         .setup_ctrs             = &op_amd_setup_ctrs,
 535         .check_ctrs             = &op_amd_check_ctrs,
 536         .start                  = &op_amd_start,
 537         .stop                   = &op_amd_stop,
 538         .shutdown               = &op_amd_shutdown,
 539 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 540         .switch_ctrl            = &op_mux_switch_ctrl,
 541 #endif
 542 };