arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affilates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 static int __read_mostly bypass_guest_pf = 1;
  51 module_param(bypass_guest_pf, bool, S_IRUGO);
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  73         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  74 #define KVM_GUEST_CR0_MASK                                              \
  75         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  77         (X86_CR0_WP | X86_CR0_NE)
  78 #define KVM_VM_CR0_ALWAYS_ON                                            \
  79         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  80 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  81         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  82          | X86_CR4_OSXMMEXCPT)
  83
  84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  86
  87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  88
  89 /*
  90  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  91  * ple_gap:    upper bound on the amount of time between two successive
  92  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  93  *             According to test, this time is usually small than 41 cycles.
  94  * ple_window: upper bound on the amount of time a guest is allowed to execute
  95  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  96  *             less than 2^12 cycles
  97  * Time is measured based on a counter that runs at the same rate as the TSC,
  98  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  99  */
 100 #define KVM_VMX_DEFAULT_PLE_GAP    41
 101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 103 module_param(ple_gap, int, S_IRUGO);
 104
 105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 106 module_param(ple_window, int, S_IRUGO);
 107
 108 #define NR_AUTOLOAD_MSRS 1
 109
 110 struct vmcs {
 111         u32 revision_id;
 112         u32 abort;
 113         char data[0];
 114 };
 115
 116 struct shared_msr_entry {
 117         unsigned index;
 118         u64 data;
 119         u64 mask;
 120 };
 121
 122 struct vcpu_vmx {
 123         struct kvm_vcpu       vcpu;
 124         struct list_head      local_vcpus_link;
 125         unsigned long         host_rsp;
 126         int                   launched;
 127         u8                    fail;
 128         u32                   idt_vectoring_info;
 129         struct shared_msr_entry *guest_msrs;
 130         int                   nmsrs;
 131         int                   save_nmsrs;
 132 #ifdef CONFIG_X86_64
 133         u64                   msr_host_kernel_gs_base;
 134         u64                   msr_guest_kernel_gs_base;
 135 #endif
 136         struct vmcs          *vmcs;
 137         struct msr_autoload {
 138                 unsigned nr;
 139                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 140                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 141         } msr_autoload;
 142         struct {
 143                 int           loaded;
 144                 u16           fs_sel, gs_sel, ldt_sel;
 145                 int           gs_ldt_reload_needed;
 146                 int           fs_reload_needed;
 147         } host_state;
 148         struct {
 149                 int vm86_active;
 150                 ulong save_rflags;
 151                 struct kvm_save_segment {
 152                         u16 selector;
 153                         unsigned long base;
 154                         u32 limit;
 155                         u32 ar;
 156                 } tr, es, ds, fs, gs;
 157                 struct {
 158                         bool pending;
 159                         u8 vector;
 160                         unsigned rip;
 161                 } irq;
 162         } rmode;
 163         int vpid;
 164         bool emulation_required;
 165
 166         /* Support for vnmi-less CPUs */
 167         int soft_vnmi_blocked;
 168         ktime_t entry_time;
 169         s64 vnmi_blocked_time;
 170         u32 exit_reason;
 171
 172         bool rdtscp_enabled;
 173 };
 174
 175 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 176 {
 177         return container_of(vcpu, struct vcpu_vmx, vcpu);
 178 }
 179
 180 static int init_rmode(struct kvm *kvm);
 181 static u64 construct_eptp(unsigned long root_hpa);
 182 static void kvm_cpu_vmxon(u64 addr);
 183 static void kvm_cpu_vmxoff(void);
 184
 185 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 186 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 187 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 188 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 189
 190 static unsigned long *vmx_io_bitmap_a;
 191 static unsigned long *vmx_io_bitmap_b;
 192 static unsigned long *vmx_msr_bitmap_legacy;
 193 static unsigned long *vmx_msr_bitmap_longmode;
 194
 195 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 196 static DEFINE_SPINLOCK(vmx_vpid_lock);
 197
 198 static struct vmcs_config {
 199         int size;
 200         int order;
 201         u32 revision_id;
 202         u32 pin_based_exec_ctrl;
 203         u32 cpu_based_exec_ctrl;
 204         u32 cpu_based_2nd_exec_ctrl;
 205         u32 vmexit_ctrl;
 206         u32 vmentry_ctrl;
 207 } vmcs_config;
 208
 209 static struct vmx_capability {
 210         u32 ept;
 211         u32 vpid;
 212 } vmx_capability;
 213
 214 #define VMX_SEGMENT_FIELD(seg)                                  \
 215         [VCPU_SREG_##seg] = {                                   \
 216                 .selector = GUEST_##seg##_SELECTOR,             \
 217                 .base = GUEST_##seg##_BASE,                     \
 218                 .limit = GUEST_##seg##_LIMIT,                   \
 219                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 220         }
 221
 222 static struct kvm_vmx_segment_field {
 223         unsigned selector;
 224         unsigned base;
 225         unsigned limit;
 226         unsigned ar_bytes;
 227 } kvm_vmx_segment_fields[] = {
 228         VMX_SEGMENT_FIELD(CS),
 229         VMX_SEGMENT_FIELD(DS),
 230         VMX_SEGMENT_FIELD(ES),
 231         VMX_SEGMENT_FIELD(FS),
 232         VMX_SEGMENT_FIELD(GS),
 233         VMX_SEGMENT_FIELD(SS),
 234         VMX_SEGMENT_FIELD(TR),
 235         VMX_SEGMENT_FIELD(LDTR),
 236 };
 237
 238 static u64 host_efer;
 239
 240 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 241
 242 /*
 243  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 244  * away by decrementing the array size.
 245  */
 246 static const u32 vmx_msr_index[] = {
 247 #ifdef CONFIG_X86_64
 248         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 249 #endif
 250         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 251 };
 252 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 253
 254 static inline bool is_page_fault(u32 intr_info)
 255 {
 256         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 257                              INTR_INFO_VALID_MASK)) ==
 258                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 259 }
 260
 261 static inline bool is_no_device(u32 intr_info)
 262 {
 263         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 264                              INTR_INFO_VALID_MASK)) ==
 265                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 266 }
 267
 268 static inline bool is_invalid_opcode(u32 intr_info)
 269 {
 270         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 271                              INTR_INFO_VALID_MASK)) ==
 272                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 273 }
 274
 275 static inline bool is_external_interrupt(u32 intr_info)
 276 {
 277         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 278                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 279 }
 280
 281 static inline bool is_machine_check(u32 intr_info)
 282 {
 283         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 284                              INTR_INFO_VALID_MASK)) ==
 285                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 286 }
 287
 288 static inline bool cpu_has_vmx_msr_bitmap(void)
 289 {
 290         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 291 }
 292
 293 static inline bool cpu_has_vmx_tpr_shadow(void)
 294 {
 295         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 296 }
 297
 298 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 299 {
 300         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 301 }
 302
 303 static inline bool cpu_has_secondary_exec_ctrls(void)
 304 {
 305         return vmcs_config.cpu_based_exec_ctrl &
 306                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 307 }
 308
 309 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 310 {
 311         return vmcs_config.cpu_based_2nd_exec_ctrl &
 312                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 313 }
 314
 315 static inline bool cpu_has_vmx_flexpriority(void)
 316 {
 317         return cpu_has_vmx_tpr_shadow() &&
 318                 cpu_has_vmx_virtualize_apic_accesses();
 319 }
 320
 321 static inline bool cpu_has_vmx_ept_execute_only(void)
 322 {
 323         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 324 }
 325
 326 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 327 {
 328         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 329 }
 330
 331 static inline bool cpu_has_vmx_eptp_writeback(void)
 332 {
 333         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 334 }
 335
 336 static inline bool cpu_has_vmx_ept_2m_page(void)
 337 {
 338         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 339 }
 340
 341 static inline bool cpu_has_vmx_ept_1g_page(void)
 342 {
 343         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 344 }
 345
 346 static inline bool cpu_has_vmx_ept_4levels(void)
 347 {
 348         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 349 }
 350
 351 static inline bool cpu_has_vmx_invept_individual_addr(void)
 352 {
 353         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 354 }
 355
 356 static inline bool cpu_has_vmx_invept_context(void)
 357 {
 358         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 359 }
 360
 361 static inline bool cpu_has_vmx_invept_global(void)
 362 {
 363         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 364 }
 365
 366 static inline bool cpu_has_vmx_invvpid_single(void)
 367 {
 368         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 369 }
 370
 371 static inline bool cpu_has_vmx_invvpid_global(void)
 372 {
 373         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 374 }
 375
 376 static inline bool cpu_has_vmx_ept(void)
 377 {
 378         return vmcs_config.cpu_based_2nd_exec_ctrl &
 379                 SECONDARY_EXEC_ENABLE_EPT;
 380 }
 381
 382 static inline bool cpu_has_vmx_unrestricted_guest(void)
 383 {
 384         return vmcs_config.cpu_based_2nd_exec_ctrl &
 385                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 386 }
 387
 388 static inline bool cpu_has_vmx_ple(void)
 389 {
 390         return vmcs_config.cpu_based_2nd_exec_ctrl &
 391                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 392 }
 393
 394 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 395 {
 396         return flexpriority_enabled && irqchip_in_kernel(kvm);
 397 }
 398
 399 static inline bool cpu_has_vmx_vpid(void)
 400 {
 401         return vmcs_config.cpu_based_2nd_exec_ctrl &
 402                 SECONDARY_EXEC_ENABLE_VPID;
 403 }
 404
 405 static inline bool cpu_has_vmx_rdtscp(void)
 406 {
 407         return vmcs_config.cpu_based_2nd_exec_ctrl &
 408                 SECONDARY_EXEC_RDTSCP;
 409 }
 410
 411 static inline bool cpu_has_virtual_nmis(void)
 412 {
 413         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 414 }
 415
 416 static inline bool cpu_has_vmx_wbinvd_exit(void)
 417 {
 418         return vmcs_config.cpu_based_2nd_exec_ctrl &
 419                 SECONDARY_EXEC_WBINVD_EXITING;
 420 }
 421
 422 static inline bool report_flexpriority(void)
 423 {
 424         return flexpriority_enabled;
 425 }
 426
 427 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 428 {
 429         int i;
 430
 431         for (i = 0; i < vmx->nmsrs; ++i)
 432                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 433                         return i;
 434         return -1;
 435 }
 436
 437 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 438 {
 439     struct {
 440         u64 vpid : 16;
 441         u64 rsvd : 48;
 442         u64 gva;
 443     } operand = { vpid, 0, gva };
 444
 445     asm volatile (__ex(ASM_VMX_INVVPID)
 446                   /* CF==1 or ZF==1 --> rc = -1 */
 447                   "; ja 1f ; ud2 ; 1:"
 448                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 449 }
 450
 451 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 452 {
 453         struct {
 454                 u64 eptp, gpa;
 455         } operand = {eptp, gpa};
 456
 457         asm volatile (__ex(ASM_VMX_INVEPT)
 458                         /* CF==1 or ZF==1 --> rc = -1 */
 459                         "; ja 1f ; ud2 ; 1:\n"
 460                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 461 }
 462
 463 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 464 {
 465         int i;
 466
 467         i = __find_msr_index(vmx, msr);
 468         if (i >= 0)
 469                 return &vmx->guest_msrs[i];
 470         return NULL;
 471 }
 472
 473 static void vmcs_clear(struct vmcs *vmcs)
 474 {
 475         u64 phys_addr = __pa(vmcs);
 476         u8 error;
 477
 478         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 479                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 480                       : "cc", "memory");
 481         if (error)
 482                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 483                        vmcs, phys_addr);
 484 }
 485
 486 static void vmcs_load(struct vmcs *vmcs)
 487 {
 488         u64 phys_addr = __pa(vmcs);
 489         u8 error;
 490
 491         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 492                         : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 493                         : "cc", "memory");
 494         if (error)
 495                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 496                        vmcs, phys_addr);
 497 }
 498
 499 static void __vcpu_clear(void *arg)
 500 {
 501         struct vcpu_vmx *vmx = arg;
 502         int cpu = raw_smp_processor_id();
 503
 504         if (vmx->vcpu.cpu == cpu)
 505                 vmcs_clear(vmx->vmcs);
 506         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 507                 per_cpu(current_vmcs, cpu) = NULL;
 508         rdtscll(vmx->vcpu.arch.host_tsc);
 509         list_del(&vmx->local_vcpus_link);
 510         vmx->vcpu.cpu = -1;
 511         vmx->launched = 0;
 512 }
 513
 514 static void vcpu_clear(struct vcpu_vmx *vmx)
 515 {
 516         if (vmx->vcpu.cpu == -1)
 517                 return;
 518         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 519 }
 520
 521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 522 {
 523         if (vmx->vpid == 0)
 524                 return;
 525
 526         if (cpu_has_vmx_invvpid_single())
 527                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 528 }
 529
 530 static inline void vpid_sync_vcpu_global(void)
 531 {
 532         if (cpu_has_vmx_invvpid_global())
 533                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 534 }
 535
 536 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 537 {
 538         if (cpu_has_vmx_invvpid_single())
 539                 vpid_sync_vcpu_single(vmx);
 540         else
 541                 vpid_sync_vcpu_global();
 542 }
 543
 544 static inline void ept_sync_global(void)
 545 {
 546         if (cpu_has_vmx_invept_global())
 547                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 548 }
 549
 550 static inline void ept_sync_context(u64 eptp)
 551 {
 552         if (enable_ept) {
 553                 if (cpu_has_vmx_invept_context())
 554                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 555                 else
 556                         ept_sync_global();
 557         }
 558 }
 559
 560 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 561 {
 562         if (enable_ept) {
 563                 if (cpu_has_vmx_invept_individual_addr())
 564                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 565                                         eptp, gpa);
 566                 else
 567                         ept_sync_context(eptp);
 568         }
 569 }
 570
 571 static unsigned long vmcs_readl(unsigned long field)
 572 {
 573         unsigned long value;
 574
 575         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 576                       : "=a"(value) : "d"(field) : "cc");
 577         return value;
 578 }
 579
 580 static u16 vmcs_read16(unsigned long field)
 581 {
 582         return vmcs_readl(field);
 583 }
 584
 585 static u32 vmcs_read32(unsigned long field)
 586 {
 587         return vmcs_readl(field);
 588 }
 589
 590 static u64 vmcs_read64(unsigned long field)
 591 {
 592 #ifdef CONFIG_X86_64
 593         return vmcs_readl(field);
 594 #else
 595         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 596 #endif
 597 }
 598
 599 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 600 {
 601         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 602                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 603         dump_stack();
 604 }
 605
 606 static void vmcs_writel(unsigned long field, unsigned long value)
 607 {
 608         u8 error;
 609
 610         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 611                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 612         if (unlikely(error))
 613                 vmwrite_error(field, value);
 614 }
 615
 616 static void vmcs_write16(unsigned long field, u16 value)
 617 {
 618         vmcs_writel(field, value);
 619 }
 620
 621 static void vmcs_write32(unsigned long field, u32 value)
 622 {
 623         vmcs_writel(field, value);
 624 }
 625
 626 static void vmcs_write64(unsigned long field, u64 value)
 627 {
 628         vmcs_writel(field, value);
 629 #ifndef CONFIG_X86_64
 630         asm volatile ("");
 631         vmcs_writel(field+1, value >> 32);
 632 #endif
 633 }
 634
 635 static void vmcs_clear_bits(unsigned long field, u32 mask)
 636 {
 637         vmcs_writel(field, vmcs_readl(field) & ~mask);
 638 }
 639
 640 static void vmcs_set_bits(unsigned long field, u32 mask)
 641 {
 642         vmcs_writel(field, vmcs_readl(field) | mask);
 643 }
 644
 645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 646 {
 647         u32 eb;
 648
 649         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 650              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 651         if ((vcpu->guest_debug &
 652              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 653             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 654                 eb |= 1u << BP_VECTOR;
 655         if (to_vmx(vcpu)->rmode.vm86_active)
 656                 eb = ~0;
 657         if (enable_ept)
 658                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 659         if (vcpu->fpu_active)
 660                 eb &= ~(1u << NM_VECTOR);
 661         vmcs_write32(EXCEPTION_BITMAP, eb);
 662 }
 663
 664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 665 {
 666         unsigned i;
 667         struct msr_autoload *m = &vmx->msr_autoload;
 668
 669         for (i = 0; i < m->nr; ++i)
 670                 if (m->guest[i].index == msr)
 671                         break;
 672
 673         if (i == m->nr)
 674                 return;
 675         --m->nr;
 676         m->guest[i] = m->guest[m->nr];
 677         m->host[i] = m->host[m->nr];
 678         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 679         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 680 }
 681
 682 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 683                                   u64 guest_val, u64 host_val)
 684 {
 685         unsigned i;
 686         struct msr_autoload *m = &vmx->msr_autoload;
 687
 688         for (i = 0; i < m->nr; ++i)
 689                 if (m->guest[i].index == msr)
 690                         break;
 691
 692         if (i == m->nr) {
 693                 ++m->nr;
 694                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 695                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 696         }
 697
 698         m->guest[i].index = msr;
 699         m->guest[i].value = guest_val;
 700         m->host[i].index = msr;
 701         m->host[i].value = host_val;
 702 }
 703
 704 static void reload_tss(void)
 705 {
 706         /*
 707          * VT restores TR but not its size.  Useless.
 708          */
 709         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 710         struct desc_struct *descs;
 711
 712         descs = (void *)gdt->address;
 713         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 714         load_TR_desc();
 715 }
 716
 717 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 718 {
 719         u64 guest_efer;
 720         u64 ignore_bits;
 721
 722         guest_efer = vmx->vcpu.arch.efer;
 723
 724         /*
 725          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 726          * outside long mode
 727          */
 728         ignore_bits = EFER_NX | EFER_SCE;
 729 #ifdef CONFIG_X86_64
 730         ignore_bits |= EFER_LMA | EFER_LME;
 731         /* SCE is meaningful only in long mode on Intel */
 732         if (guest_efer & EFER_LMA)
 733                 ignore_bits &= ~(u64)EFER_SCE;
 734 #endif
 735         guest_efer &= ~ignore_bits;
 736         guest_efer |= host_efer & ignore_bits;
 737         vmx->guest_msrs[efer_offset].data = guest_efer;
 738         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 739
 740         clear_atomic_switch_msr(vmx, MSR_EFER);
 741         /* On ept, can't emulate nx, and must switch nx atomically */
 742         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 743                 guest_efer = vmx->vcpu.arch.efer;
 744                 if (!(guest_efer & EFER_LMA))
 745                         guest_efer &= ~EFER_LME;
 746                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 747                 return false;
 748         }
 749
 750         return true;
 751 }
 752
 753 static unsigned long segment_base(u16 selector)
 754 {
 755         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 756         struct desc_struct *d;
 757         unsigned long table_base;
 758         unsigned long v;
 759
 760         if (!(selector & ~3))
 761                 return 0;
 762
 763         table_base = gdt->address;
 764
 765         if (selector & 4) {           /* from ldt */
 766                 u16 ldt_selector = kvm_read_ldt();
 767
 768                 if (!(ldt_selector & ~3))
 769                         return 0;
 770
 771                 table_base = segment_base(ldt_selector);
 772         }
 773         d = (struct desc_struct *)(table_base + (selector & ~7));
 774         v = get_desc_base(d);
 775 #ifdef CONFIG_X86_64
 776        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 777                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 778 #endif
 779         return v;
 780 }
 781
 782 static inline unsigned long kvm_read_tr_base(void)
 783 {
 784         u16 tr;
 785         asm("str %0" : "=g"(tr));
 786         return segment_base(tr);
 787 }
 788
 789 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 790 {
 791         struct vcpu_vmx *vmx = to_vmx(vcpu);
 792         int i;
 793
 794         if (vmx->host_state.loaded)
 795                 return;
 796
 797         vmx->host_state.loaded = 1;
 798         /*
 799          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 800          * allow segment selectors with cpl > 0 or ti == 1.
 801          */
 802         vmx->host_state.ldt_sel = kvm_read_ldt();
 803         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 804         savesegment(fs, vmx->host_state.fs_sel);
 805         if (!(vmx->host_state.fs_sel & 7)) {
 806                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 807                 vmx->host_state.fs_reload_needed = 0;
 808         } else {
 809                 vmcs_write16(HOST_FS_SELECTOR, 0);
 810                 vmx->host_state.fs_reload_needed = 1;
 811         }
 812         savesegment(gs, vmx->host_state.gs_sel);
 813         if (!(vmx->host_state.gs_sel & 7))
 814                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 815         else {
 816                 vmcs_write16(HOST_GS_SELECTOR, 0);
 817                 vmx->host_state.gs_ldt_reload_needed = 1;
 818         }
 819
 820 #ifdef CONFIG_X86_64
 821         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 822         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 823 #else
 824         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 825         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 826 #endif
 827
 828 #ifdef CONFIG_X86_64
 829         if (is_long_mode(&vmx->vcpu)) {
 830                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 831                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 832         }
 833 #endif
 834         for (i = 0; i < vmx->save_nmsrs; ++i)
 835                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 836                                    vmx->guest_msrs[i].data,
 837                                    vmx->guest_msrs[i].mask);
 838 }
 839
 840 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 841 {
 842         if (!vmx->host_state.loaded)
 843                 return;
 844
 845         ++vmx->vcpu.stat.host_state_reload;
 846         vmx->host_state.loaded = 0;
 847         if (vmx->host_state.fs_reload_needed)
 848                 loadsegment(fs, vmx->host_state.fs_sel);
 849         if (vmx->host_state.gs_ldt_reload_needed) {
 850                 kvm_load_ldt(vmx->host_state.ldt_sel);
 851 #ifdef CONFIG_X86_64
 852                 load_gs_index(vmx->host_state.gs_sel);
 853                 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
 854 #else
 855                 loadsegment(gs, vmx->host_state.gs_sel);
 856 #endif
 857         }
 858         reload_tss();
 859 #ifdef CONFIG_X86_64
 860         if (is_long_mode(&vmx->vcpu)) {
 861                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 862                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 863         }
 864 #endif
 865         if (current_thread_info()->status & TS_USEDFPU)
 866                 clts();
 867         load_gdt(&__get_cpu_var(host_gdt));
 868 }
 869
 870 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 871 {
 872         preempt_disable();
 873         __vmx_load_host_state(vmx);
 874         preempt_enable();
 875 }
 876
 877 /*
 878  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 879  * vcpu mutex is already taken.
 880  */
 881 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 882 {
 883         struct vcpu_vmx *vmx = to_vmx(vcpu);
 884         u64 tsc_this, delta, new_offset;
 885         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 886
 887         if (!vmm_exclusive)
 888                 kvm_cpu_vmxon(phys_addr);
 889         else if (vcpu->cpu != cpu)
 890                 vcpu_clear(vmx);
 891
 892         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 893                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 894                 vmcs_load(vmx->vmcs);
 895         }
 896
 897         if (vcpu->cpu != cpu) {
 898                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 899                 unsigned long sysenter_esp;
 900
 901                 kvm_migrate_timers(vcpu);
 902                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 903                 local_irq_disable();
 904                 list_add(&vmx->local_vcpus_link,
 905                          &per_cpu(vcpus_on_cpu, cpu));
 906                 local_irq_enable();
 907
 908                 vcpu->cpu = cpu;
 909                 /*
 910                  * Linux uses per-cpu TSS and GDT, so set these when switching
 911                  * processors.
 912                  */
 913                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 914                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
 915
 916                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 917                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 918
 919                 /*
 920                  * Make sure the time stamp counter is monotonous.
 921                  */
 922                 rdtscll(tsc_this);
 923                 if (tsc_this < vcpu->arch.host_tsc) {
 924                         delta = vcpu->arch.host_tsc - tsc_this;
 925                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 926                         vmcs_write64(TSC_OFFSET, new_offset);
 927                 }
 928         }
 929 }
 930
 931 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 932 {
 933         __vmx_load_host_state(to_vmx(vcpu));
 934         if (!vmm_exclusive) {
 935                 __vcpu_clear(to_vmx(vcpu));
 936                 kvm_cpu_vmxoff();
 937         }
 938 }
 939
 940 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 941 {
 942         ulong cr0;
 943
 944         if (vcpu->fpu_active)
 945                 return;
 946         vcpu->fpu_active = 1;
 947         cr0 = vmcs_readl(GUEST_CR0);
 948         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 949         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 950         vmcs_writel(GUEST_CR0, cr0);
 951         update_exception_bitmap(vcpu);
 952         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 953         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 954 }
 955
 956 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 957
 958 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 959 {
 960         vmx_decache_cr0_guest_bits(vcpu);
 961         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 962         update_exception_bitmap(vcpu);
 963         vcpu->arch.cr0_guest_owned_bits = 0;
 964         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 965         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 966 }
 967
 968 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 969 {
 970         unsigned long rflags, save_rflags;
 971
 972         rflags = vmcs_readl(GUEST_RFLAGS);
 973         if (to_vmx(vcpu)->rmode.vm86_active) {
 974                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 975                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 976                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 977         }
 978         return rflags;
 979 }
 980
 981 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 982 {
 983         if (to_vmx(vcpu)->rmode.vm86_active) {
 984                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 985                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 986         }
 987         vmcs_writel(GUEST_RFLAGS, rflags);
 988 }
 989
 990 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 991 {
 992         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 993         int ret = 0;
 994
 995         if (interruptibility & GUEST_INTR_STATE_STI)
 996                 ret |= KVM_X86_SHADOW_INT_STI;
 997         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 998                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
 999
1000         return ret & mask;
1001 }
1002
1003 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1004 {
1005         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1006         u32 interruptibility = interruptibility_old;
1007
1008         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1009
1010         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1011                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1012         else if (mask & KVM_X86_SHADOW_INT_STI)
1013                 interruptibility |= GUEST_INTR_STATE_STI;
1014
1015         if ((interruptibility != interruptibility_old))
1016                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1017 }
1018
1019 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1020 {
1021         unsigned long rip;
1022
1023         rip = kvm_rip_read(vcpu);
1024         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1025         kvm_rip_write(vcpu, rip);
1026
1027         /* skipping an emulated instruction also counts */
1028         vmx_set_interrupt_shadow(vcpu, 0);
1029 }
1030
1031 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1032                                 bool has_error_code, u32 error_code,
1033                                 bool reinject)
1034 {
1035         struct vcpu_vmx *vmx = to_vmx(vcpu);
1036         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1037
1038         if (has_error_code) {
1039                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1040                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1041         }
1042
1043         if (vmx->rmode.vm86_active) {
1044                 vmx->rmode.irq.pending = true;
1045                 vmx->rmode.irq.vector = nr;
1046                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1047                 if (kvm_exception_is_soft(nr))
1048                         vmx->rmode.irq.rip +=
1049                                 vmx->vcpu.arch.event_exit_inst_len;
1050                 intr_info |= INTR_TYPE_SOFT_INTR;
1051                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1052                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1053                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1054                 return;
1055         }
1056
1057         if (kvm_exception_is_soft(nr)) {
1058                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1059                              vmx->vcpu.arch.event_exit_inst_len);
1060                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1061         } else
1062                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1063
1064         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1065 }
1066
1067 static bool vmx_rdtscp_supported(void)
1068 {
1069         return cpu_has_vmx_rdtscp();
1070 }
1071
1072 /*
1073  * Swap MSR entry in host/guest MSR entry array.
1074  */
1075 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1076 {
1077         struct shared_msr_entry tmp;
1078
1079         tmp = vmx->guest_msrs[to];
1080         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1081         vmx->guest_msrs[from] = tmp;
1082 }
1083
1084 /*
1085  * Set up the vmcs to automatically save and restore system
1086  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1087  * mode, as fiddling with msrs is very expensive.
1088  */
1089 static void setup_msrs(struct vcpu_vmx *vmx)
1090 {
1091         int save_nmsrs, index;
1092         unsigned long *msr_bitmap;
1093
1094         vmx_load_host_state(vmx);
1095         save_nmsrs = 0;
1096 #ifdef CONFIG_X86_64
1097         if (is_long_mode(&vmx->vcpu)) {
1098                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1099                 if (index >= 0)
1100                         move_msr_up(vmx, index, save_nmsrs++);
1101                 index = __find_msr_index(vmx, MSR_LSTAR);
1102                 if (index >= 0)
1103                         move_msr_up(vmx, index, save_nmsrs++);
1104                 index = __find_msr_index(vmx, MSR_CSTAR);
1105                 if (index >= 0)
1106                         move_msr_up(vmx, index, save_nmsrs++);
1107                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1108                 if (index >= 0 && vmx->rdtscp_enabled)
1109                         move_msr_up(vmx, index, save_nmsrs++);
1110                 /*
1111                  * MSR_STAR is only needed on long mode guests, and only
1112                  * if efer.sce is enabled.
1113                  */
1114                 index = __find_msr_index(vmx, MSR_STAR);
1115                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1116                         move_msr_up(vmx, index, save_nmsrs++);
1117         }
1118 #endif
1119         index = __find_msr_index(vmx, MSR_EFER);
1120         if (index >= 0 && update_transition_efer(vmx, index))
1121                 move_msr_up(vmx, index, save_nmsrs++);
1122
1123         vmx->save_nmsrs = save_nmsrs;
1124
1125         if (cpu_has_vmx_msr_bitmap()) {
1126                 if (is_long_mode(&vmx->vcpu))
1127                         msr_bitmap = vmx_msr_bitmap_longmode;
1128                 else
1129                         msr_bitmap = vmx_msr_bitmap_legacy;
1130
1131                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1132         }
1133 }
1134
1135 /*
1136  * reads and returns guest's timestamp counter "register"
1137  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1138  */
1139 static u64 guest_read_tsc(void)
1140 {
1141         u64 host_tsc, tsc_offset;
1142
1143         rdtscll(host_tsc);
1144         tsc_offset = vmcs_read64(TSC_OFFSET);
1145         return host_tsc + tsc_offset;
1146 }
1147
1148 /*
1149  * writes 'guest_tsc' into guest's timestamp counter "register"
1150  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1151  */
1152 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1153 {
1154         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1155 }
1156
1157 /*
1158  * Reads an msr value (of 'msr_index') into 'pdata'.
1159  * Returns 0 on success, non-0 otherwise.
1160  * Assumes vcpu_load() was already called.
1161  */
1162 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1163 {
1164         u64 data;
1165         struct shared_msr_entry *msr;
1166
1167         if (!pdata) {
1168                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1169                 return -EINVAL;
1170         }
1171
1172         switch (msr_index) {
1173 #ifdef CONFIG_X86_64
1174         case MSR_FS_BASE:
1175                 data = vmcs_readl(GUEST_FS_BASE);
1176                 break;
1177         case MSR_GS_BASE:
1178                 data = vmcs_readl(GUEST_GS_BASE);
1179                 break;
1180         case MSR_KERNEL_GS_BASE:
1181                 vmx_load_host_state(to_vmx(vcpu));
1182                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1183                 break;
1184 #endif
1185         case MSR_EFER:
1186                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1187         case MSR_IA32_TSC:
1188                 data = guest_read_tsc();
1189                 break;
1190         case MSR_IA32_SYSENTER_CS:
1191                 data = vmcs_read32(GUEST_SYSENTER_CS);
1192                 break;
1193         case MSR_IA32_SYSENTER_EIP:
1194                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1195                 break;
1196         case MSR_IA32_SYSENTER_ESP:
1197                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1198                 break;
1199         case MSR_TSC_AUX:
1200                 if (!to_vmx(vcpu)->rdtscp_enabled)
1201                         return 1;
1202                 /* Otherwise falls through */
1203         default:
1204                 vmx_load_host_state(to_vmx(vcpu));
1205                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1206                 if (msr) {
1207                         vmx_load_host_state(to_vmx(vcpu));
1208                         data = msr->data;
1209                         break;
1210                 }
1211                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1212         }
1213
1214         *pdata = data;
1215         return 0;
1216 }
1217
1218 /*
1219  * Writes msr value into into the appropriate "register".
1220  * Returns 0 on success, non-0 otherwise.
1221  * Assumes vcpu_load() was already called.
1222  */
1223 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1224 {
1225         struct vcpu_vmx *vmx = to_vmx(vcpu);
1226         struct shared_msr_entry *msr;
1227         u64 host_tsc;
1228         int ret = 0;
1229
1230         switch (msr_index) {
1231         case MSR_EFER:
1232                 vmx_load_host_state(vmx);
1233                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1234                 break;
1235 #ifdef CONFIG_X86_64
1236         case MSR_FS_BASE:
1237                 vmcs_writel(GUEST_FS_BASE, data);
1238                 break;
1239         case MSR_GS_BASE:
1240                 vmcs_writel(GUEST_GS_BASE, data);
1241                 break;
1242         case MSR_KERNEL_GS_BASE:
1243                 vmx_load_host_state(vmx);
1244                 vmx->msr_guest_kernel_gs_base = data;
1245                 break;
1246 #endif
1247         case MSR_IA32_SYSENTER_CS:
1248                 vmcs_write32(GUEST_SYSENTER_CS, data);
1249                 break;
1250         case MSR_IA32_SYSENTER_EIP:
1251                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1252                 break;
1253         case MSR_IA32_SYSENTER_ESP:
1254                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1255                 break;
1256         case MSR_IA32_TSC:
1257                 rdtscll(host_tsc);
1258                 guest_write_tsc(data, host_tsc);
1259                 break;
1260         case MSR_IA32_CR_PAT:
1261                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1262                         vmcs_write64(GUEST_IA32_PAT, data);
1263                         vcpu->arch.pat = data;
1264                         break;
1265                 }
1266                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1267                 break;
1268         case MSR_TSC_AUX:
1269                 if (!vmx->rdtscp_enabled)
1270                         return 1;
1271                 /* Check reserved bit, higher 32 bits should be zero */
1272                 if ((data >> 32) != 0)
1273                         return 1;
1274                 /* Otherwise falls through */
1275         default:
1276                 msr = find_msr_entry(vmx, msr_index);
1277                 if (msr) {
1278                         vmx_load_host_state(vmx);
1279                         msr->data = data;
1280                         break;
1281                 }
1282                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1283         }
1284
1285         return ret;
1286 }
1287
1288 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1289 {
1290         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1291         switch (reg) {
1292         case VCPU_REGS_RSP:
1293                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1294                 break;
1295         case VCPU_REGS_RIP:
1296                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1297                 break;
1298         case VCPU_EXREG_PDPTR:
1299                 if (enable_ept)
1300                         ept_save_pdptrs(vcpu);
1301                 break;
1302         default:
1303                 break;
1304         }
1305 }
1306
1307 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1308 {
1309         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1310                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1311         else
1312                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1313
1314         update_exception_bitmap(vcpu);
1315 }
1316
1317 static __init int cpu_has_kvm_support(void)
1318 {
1319         return cpu_has_vmx();
1320 }
1321
1322 static __init int vmx_disabled_by_bios(void)
1323 {
1324         u64 msr;
1325
1326         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1327         if (msr & FEATURE_CONTROL_LOCKED) {
1328                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1329                         && tboot_enabled())
1330                         return 1;
1331                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1332                         && !tboot_enabled())
1333                         return 1;
1334         }
1335
1336         return 0;
1337         /* locked but not enabled */
1338 }
1339
1340 static void kvm_cpu_vmxon(u64 addr)
1341 {
1342         asm volatile (ASM_VMX_VMXON_RAX
1343                         : : "a"(&addr), "m"(addr)
1344                         : "memory", "cc");
1345 }
1346
1347 static int hardware_enable(void *garbage)
1348 {
1349         int cpu = raw_smp_processor_id();
1350         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1351         u64 old, test_bits;
1352
1353         if (read_cr4() & X86_CR4_VMXE)
1354                 return -EBUSY;
1355
1356         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1357         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1358
1359         test_bits = FEATURE_CONTROL_LOCKED;
1360         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1361         if (tboot_enabled())
1362                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1363
1364         if ((old & test_bits) != test_bits) {
1365                 /* enable and lock */
1366                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1367         }
1368         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1369
1370         if (vmm_exclusive) {
1371                 kvm_cpu_vmxon(phys_addr);
1372                 ept_sync_global();
1373         }
1374
1375         store_gdt(&__get_cpu_var(host_gdt));
1376
1377         return 0;
1378 }
1379
1380 static void vmclear_local_vcpus(void)
1381 {
1382         int cpu = raw_smp_processor_id();
1383         struct vcpu_vmx *vmx, *n;
1384
1385         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1386                                  local_vcpus_link)
1387                 __vcpu_clear(vmx);
1388 }
1389
1390
1391 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1392  * tricks.
1393  */
1394 static void kvm_cpu_vmxoff(void)
1395 {
1396         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1397 }
1398
1399 static void hardware_disable(void *garbage)
1400 {
1401         if (vmm_exclusive) {
1402                 vmclear_local_vcpus();
1403                 kvm_cpu_vmxoff();
1404         }
1405         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1406 }
1407
1408 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1409                                       u32 msr, u32 *result)
1410 {
1411         u32 vmx_msr_low, vmx_msr_high;
1412         u32 ctl = ctl_min | ctl_opt;
1413
1414         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1415
1416         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1417         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1418
1419         /* Ensure minimum (required) set of control bits are supported. */
1420         if (ctl_min & ~ctl)
1421                 return -EIO;
1422
1423         *result = ctl;
1424         return 0;
1425 }
1426
1427 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1428 {
1429         u32 vmx_msr_low, vmx_msr_high;
1430         u32 min, opt, min2, opt2;
1431         u32 _pin_based_exec_control = 0;
1432         u32 _cpu_based_exec_control = 0;
1433         u32 _cpu_based_2nd_exec_control = 0;
1434         u32 _vmexit_control = 0;
1435         u32 _vmentry_control = 0;
1436
1437         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1438         opt = PIN_BASED_VIRTUAL_NMIS;
1439         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1440                                 &_pin_based_exec_control) < 0)
1441                 return -EIO;
1442
1443         min = CPU_BASED_HLT_EXITING |
1444 #ifdef CONFIG_X86_64
1445               CPU_BASED_CR8_LOAD_EXITING |
1446               CPU_BASED_CR8_STORE_EXITING |
1447 #endif
1448               CPU_BASED_CR3_LOAD_EXITING |
1449               CPU_BASED_CR3_STORE_EXITING |
1450               CPU_BASED_USE_IO_BITMAPS |
1451               CPU_BASED_MOV_DR_EXITING |
1452               CPU_BASED_USE_TSC_OFFSETING |
1453               CPU_BASED_MWAIT_EXITING |
1454               CPU_BASED_MONITOR_EXITING |
1455               CPU_BASED_INVLPG_EXITING;
1456         opt = CPU_BASED_TPR_SHADOW |
1457               CPU_BASED_USE_MSR_BITMAPS |
1458               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1459         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1460                                 &_cpu_based_exec_control) < 0)
1461                 return -EIO;
1462 #ifdef CONFIG_X86_64
1463         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1464                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1465                                            ~CPU_BASED_CR8_STORE_EXITING;
1466 #endif
1467         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1468                 min2 = 0;
1469                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1470                         SECONDARY_EXEC_WBINVD_EXITING |
1471                         SECONDARY_EXEC_ENABLE_VPID |
1472                         SECONDARY_EXEC_ENABLE_EPT |
1473                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1474                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1475                         SECONDARY_EXEC_RDTSCP;
1476                 if (adjust_vmx_controls(min2, opt2,
1477                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1478                                         &_cpu_based_2nd_exec_control) < 0)
1479                         return -EIO;
1480         }
1481 #ifndef CONFIG_X86_64
1482         if (!(_cpu_based_2nd_exec_control &
1483                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1484                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1485 #endif
1486         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1487                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1488                    enabled */
1489                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1490                                              CPU_BASED_CR3_STORE_EXITING |
1491                                              CPU_BASED_INVLPG_EXITING);
1492                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1493                       vmx_capability.ept, vmx_capability.vpid);
1494         }
1495
1496         min = 0;
1497 #ifdef CONFIG_X86_64
1498         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1499 #endif
1500         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1501         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1502                                 &_vmexit_control) < 0)
1503                 return -EIO;
1504
1505         min = 0;
1506         opt = VM_ENTRY_LOAD_IA32_PAT;
1507         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1508                                 &_vmentry_control) < 0)
1509                 return -EIO;
1510
1511         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1512
1513         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1514         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1515                 return -EIO;
1516
1517 #ifdef CONFIG_X86_64
1518         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1519         if (vmx_msr_high & (1u<<16))
1520                 return -EIO;
1521 #endif
1522
1523         /* Require Write-Back (WB) memory type for VMCS accesses. */
1524         if (((vmx_msr_high >> 18) & 15) != 6)
1525                 return -EIO;
1526
1527         vmcs_conf->size = vmx_msr_high & 0x1fff;
1528         vmcs_conf->order = get_order(vmcs_config.size);
1529         vmcs_conf->revision_id = vmx_msr_low;
1530
1531         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1532         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1533         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1534         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1535         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1536
1537         return 0;
1538 }
1539
1540 static struct vmcs *alloc_vmcs_cpu(int cpu)
1541 {
1542         int node = cpu_to_node(cpu);
1543         struct page *pages;
1544         struct vmcs *vmcs;
1545
1546         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1547         if (!pages)
1548                 return NULL;
1549         vmcs = page_address(pages);
1550         memset(vmcs, 0, vmcs_config.size);
1551         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1552         return vmcs;
1553 }
1554
1555 static struct vmcs *alloc_vmcs(void)
1556 {
1557         return alloc_vmcs_cpu(raw_smp_processor_id());
1558 }
1559
1560 static void free_vmcs(struct vmcs *vmcs)
1561 {
1562         free_pages((unsigned long)vmcs, vmcs_config.order);
1563 }
1564
1565 static void free_kvm_area(void)
1566 {
1567         int cpu;
1568
1569         for_each_possible_cpu(cpu) {
1570                 free_vmcs(per_cpu(vmxarea, cpu));
1571                 per_cpu(vmxarea, cpu) = NULL;
1572         }
1573 }
1574
1575 static __init int alloc_kvm_area(void)
1576 {
1577         int cpu;
1578
1579         for_each_possible_cpu(cpu) {
1580                 struct vmcs *vmcs;
1581
1582                 vmcs = alloc_vmcs_cpu(cpu);
1583                 if (!vmcs) {
1584                         free_kvm_area();
1585                         return -ENOMEM;
1586                 }
1587
1588                 per_cpu(vmxarea, cpu) = vmcs;
1589         }
1590         return 0;
1591 }
1592
1593 static __init int hardware_setup(void)
1594 {
1595         if (setup_vmcs_config(&vmcs_config) < 0)
1596                 return -EIO;
1597
1598         if (boot_cpu_has(X86_FEATURE_NX))
1599                 kvm_enable_efer_bits(EFER_NX);
1600
1601         if (!cpu_has_vmx_vpid())
1602                 enable_vpid = 0;
1603
1604         if (!cpu_has_vmx_ept() ||
1605             !cpu_has_vmx_ept_4levels()) {
1606                 enable_ept = 0;
1607                 enable_unrestricted_guest = 0;
1608         }
1609
1610         if (!cpu_has_vmx_unrestricted_guest())
1611                 enable_unrestricted_guest = 0;
1612
1613         if (!cpu_has_vmx_flexpriority())
1614                 flexpriority_enabled = 0;
1615
1616         if (!cpu_has_vmx_tpr_shadow())
1617                 kvm_x86_ops->update_cr8_intercept = NULL;
1618
1619         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1620                 kvm_disable_largepages();
1621
1622         if (!cpu_has_vmx_ple())
1623                 ple_gap = 0;
1624
1625         return alloc_kvm_area();
1626 }
1627
1628 static __exit void hardware_unsetup(void)
1629 {
1630         free_kvm_area();
1631 }
1632
1633 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1634 {
1635         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1636
1637         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1638                 vmcs_write16(sf->selector, save->selector);
1639                 vmcs_writel(sf->base, save->base);
1640                 vmcs_write32(sf->limit, save->limit);
1641                 vmcs_write32(sf->ar_bytes, save->ar);
1642         } else {
1643                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1644                         << AR_DPL_SHIFT;
1645                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1646         }
1647 }
1648
1649 static void enter_pmode(struct kvm_vcpu *vcpu)
1650 {
1651         unsigned long flags;
1652         struct vcpu_vmx *vmx = to_vmx(vcpu);
1653
1654         vmx->emulation_required = 1;
1655         vmx->rmode.vm86_active = 0;
1656
1657         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1658         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1659         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1660
1661         flags = vmcs_readl(GUEST_RFLAGS);
1662         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1663         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1664         vmcs_writel(GUEST_RFLAGS, flags);
1665
1666         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1667                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1668
1669         update_exception_bitmap(vcpu);
1670
1671         if (emulate_invalid_guest_state)
1672                 return;
1673
1674         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1675         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1676         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1677         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1678
1679         vmcs_write16(GUEST_SS_SELECTOR, 0);
1680         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1681
1682         vmcs_write16(GUEST_CS_SELECTOR,
1683                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1684         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1685 }
1686
1687 static gva_t rmode_tss_base(struct kvm *kvm)
1688 {
1689         if (!kvm->arch.tss_addr) {
1690                 struct kvm_memslots *slots;
1691                 gfn_t base_gfn;
1692
1693                 slots = kvm_memslots(kvm);
1694                 base_gfn = slots->memslots[0].base_gfn +
1695                                  kvm->memslots->memslots[0].npages - 3;
1696                 return base_gfn << PAGE_SHIFT;
1697         }
1698         return kvm->arch.tss_addr;
1699 }
1700
1701 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1702 {
1703         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1704
1705         save->selector = vmcs_read16(sf->selector);
1706         save->base = vmcs_readl(sf->base);
1707         save->limit = vmcs_read32(sf->limit);
1708         save->ar = vmcs_read32(sf->ar_bytes);
1709         vmcs_write16(sf->selector, save->base >> 4);
1710         vmcs_write32(sf->base, save->base & 0xfffff);
1711         vmcs_write32(sf->limit, 0xffff);
1712         vmcs_write32(sf->ar_bytes, 0xf3);
1713 }
1714
1715 static void enter_rmode(struct kvm_vcpu *vcpu)
1716 {
1717         unsigned long flags;
1718         struct vcpu_vmx *vmx = to_vmx(vcpu);
1719
1720         if (enable_unrestricted_guest)
1721                 return;
1722
1723         vmx->emulation_required = 1;
1724         vmx->rmode.vm86_active = 1;
1725
1726         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1727         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1728
1729         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1730         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1731
1732         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1733         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1734
1735         flags = vmcs_readl(GUEST_RFLAGS);
1736         vmx->rmode.save_rflags = flags;
1737
1738         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1739
1740         vmcs_writel(GUEST_RFLAGS, flags);
1741         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1742         update_exception_bitmap(vcpu);
1743
1744         if (emulate_invalid_guest_state)
1745                 goto continue_rmode;
1746
1747         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1748         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1749         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1750
1751         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1752         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1753         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1754                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1755         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1756
1757         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1758         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1759         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1760         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1761
1762 continue_rmode:
1763         kvm_mmu_reset_context(vcpu);
1764         init_rmode(vcpu->kvm);
1765 }
1766
1767 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1768 {
1769         struct vcpu_vmx *vmx = to_vmx(vcpu);
1770         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1771
1772         if (!msr)
1773                 return;
1774
1775         /*
1776          * Force kernel_gs_base reloading before EFER changes, as control
1777          * of this msr depends on is_long_mode().
1778          */
1779         vmx_load_host_state(to_vmx(vcpu));
1780         vcpu->arch.efer = efer;
1781         if (efer & EFER_LMA) {
1782                 vmcs_write32(VM_ENTRY_CONTROLS,
1783                              vmcs_read32(VM_ENTRY_CONTROLS) |
1784                              VM_ENTRY_IA32E_MODE);
1785                 msr->data = efer;
1786         } else {
1787                 vmcs_write32(VM_ENTRY_CONTROLS,
1788                              vmcs_read32(VM_ENTRY_CONTROLS) &
1789                              ~VM_ENTRY_IA32E_MODE);
1790
1791                 msr->data = efer & ~EFER_LME;
1792         }
1793         setup_msrs(vmx);
1794 }
1795
1796 #ifdef CONFIG_X86_64
1797
1798 static void enter_lmode(struct kvm_vcpu *vcpu)
1799 {
1800         u32 guest_tr_ar;
1801
1802         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1803         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1804                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1805                        __func__);
1806                 vmcs_write32(GUEST_TR_AR_BYTES,
1807                              (guest_tr_ar & ~AR_TYPE_MASK)
1808                              | AR_TYPE_BUSY_64_TSS);
1809         }
1810         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1811 }
1812
1813 static void exit_lmode(struct kvm_vcpu *vcpu)
1814 {
1815         vmcs_write32(VM_ENTRY_CONTROLS,
1816                      vmcs_read32(VM_ENTRY_CONTROLS)
1817                      & ~VM_ENTRY_IA32E_MODE);
1818         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1819 }
1820
1821 #endif
1822
1823 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1824 {
1825         vpid_sync_context(to_vmx(vcpu));
1826         if (enable_ept) {
1827                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1828                         return;
1829                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1830         }
1831 }
1832
1833 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1834 {
1835         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1836
1837         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1838         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1839 }
1840
1841 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1842 {
1843         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1844
1845         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1846         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1847 }
1848
1849 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1850 {
1851         if (!test_bit(VCPU_EXREG_PDPTR,
1852                       (unsigned long *)&vcpu->arch.regs_dirty))
1853                 return;
1854
1855         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1856                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1857                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1858                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1859                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1860         }
1861 }
1862
1863 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1864 {
1865         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1866                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1867                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1868                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1869                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1870         }
1871
1872         __set_bit(VCPU_EXREG_PDPTR,
1873                   (unsigned long *)&vcpu->arch.regs_avail);
1874         __set_bit(VCPU_EXREG_PDPTR,
1875                   (unsigned long *)&vcpu->arch.regs_dirty);
1876 }
1877
1878 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1879
1880 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1881                                         unsigned long cr0,
1882                                         struct kvm_vcpu *vcpu)
1883 {
1884         if (!(cr0 & X86_CR0_PG)) {
1885                 /* From paging/starting to nonpaging */
1886                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1887                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1888                              (CPU_BASED_CR3_LOAD_EXITING |
1889                               CPU_BASED_CR3_STORE_EXITING));
1890                 vcpu->arch.cr0 = cr0;
1891                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1892         } else if (!is_paging(vcpu)) {
1893                 /* From nonpaging to paging */
1894                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1895                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1896                              ~(CPU_BASED_CR3_LOAD_EXITING |
1897                                CPU_BASED_CR3_STORE_EXITING));
1898                 vcpu->arch.cr0 = cr0;
1899                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1900         }
1901
1902         if (!(cr0 & X86_CR0_WP))
1903                 *hw_cr0 &= ~X86_CR0_WP;
1904 }
1905
1906 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1907 {
1908         struct vcpu_vmx *vmx = to_vmx(vcpu);
1909         unsigned long hw_cr0;
1910
1911         if (enable_unrestricted_guest)
1912                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1913                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1914         else
1915                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1916
1917         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1918                 enter_pmode(vcpu);
1919
1920         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1921                 enter_rmode(vcpu);
1922
1923 #ifdef CONFIG_X86_64
1924         if (vcpu->arch.efer & EFER_LME) {
1925                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1926                         enter_lmode(vcpu);
1927                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1928                         exit_lmode(vcpu);
1929         }
1930 #endif
1931
1932         if (enable_ept)
1933                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1934
1935         if (!vcpu->fpu_active)
1936                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1937
1938         vmcs_writel(CR0_READ_SHADOW, cr0);
1939         vmcs_writel(GUEST_CR0, hw_cr0);
1940         vcpu->arch.cr0 = cr0;
1941 }
1942
1943 static u64 construct_eptp(unsigned long root_hpa)
1944 {
1945         u64 eptp;
1946
1947         /* TODO write the value reading from MSR */
1948         eptp = VMX_EPT_DEFAULT_MT |
1949                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1950         eptp |= (root_hpa & PAGE_MASK);
1951
1952         return eptp;
1953 }
1954
1955 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1956 {
1957         unsigned long guest_cr3;
1958         u64 eptp;
1959
1960         guest_cr3 = cr3;
1961         if (enable_ept) {
1962                 eptp = construct_eptp(cr3);
1963                 vmcs_write64(EPT_POINTER, eptp);
1964                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1965                         vcpu->kvm->arch.ept_identity_map_addr;
1966                 ept_load_pdptrs(vcpu);
1967         }
1968
1969         vmx_flush_tlb(vcpu);
1970         vmcs_writel(GUEST_CR3, guest_cr3);
1971 }
1972
1973 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1974 {
1975         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1976                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1977
1978         vcpu->arch.cr4 = cr4;
1979         if (enable_ept) {
1980                 if (!is_paging(vcpu)) {
1981                         hw_cr4 &= ~X86_CR4_PAE;
1982                         hw_cr4 |= X86_CR4_PSE;
1983                 } else if (!(cr4 & X86_CR4_PAE)) {
1984                         hw_cr4 &= ~X86_CR4_PAE;
1985                 }
1986         }
1987
1988         vmcs_writel(CR4_READ_SHADOW, cr4);
1989         vmcs_writel(GUEST_CR4, hw_cr4);
1990 }
1991
1992 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1993 {
1994         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1995
1996         return vmcs_readl(sf->base);
1997 }
1998
1999 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2000                             struct kvm_segment *var, int seg)
2001 {
2002         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2003         u32 ar;
2004
2005         var->base = vmcs_readl(sf->base);
2006         var->limit = vmcs_read32(sf->limit);
2007         var->selector = vmcs_read16(sf->selector);
2008         ar = vmcs_read32(sf->ar_bytes);
2009         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2010                 ar = 0;
2011         var->type = ar & 15;
2012         var->s = (ar >> 4) & 1;
2013         var->dpl = (ar >> 5) & 3;
2014         var->present = (ar >> 7) & 1;
2015         var->avl = (ar >> 12) & 1;
2016         var->l = (ar >> 13) & 1;
2017         var->db = (ar >> 14) & 1;
2018         var->g = (ar >> 15) & 1;
2019         var->unusable = (ar >> 16) & 1;
2020 }
2021
2022 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2023 {
2024         if (!is_protmode(vcpu))
2025                 return 0;
2026
2027         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2028                 return 3;
2029
2030         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2031 }
2032
2033 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2034 {
2035         u32 ar;
2036
2037         if (var->unusable)
2038                 ar = 1 << 16;
2039         else {
2040                 ar = var->type & 15;
2041                 ar |= (var->s & 1) << 4;
2042                 ar |= (var->dpl & 3) << 5;
2043                 ar |= (var->present & 1) << 7;
2044                 ar |= (var->avl & 1) << 12;
2045                 ar |= (var->l & 1) << 13;
2046                 ar |= (var->db & 1) << 14;
2047                 ar |= (var->g & 1) << 15;
2048         }
2049         if (ar == 0) /* a 0 value means unusable */
2050                 ar = AR_UNUSABLE_MASK;
2051
2052         return ar;
2053 }
2054
2055 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2056                             struct kvm_segment *var, int seg)
2057 {
2058         struct vcpu_vmx *vmx = to_vmx(vcpu);
2059         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2060         u32 ar;
2061
2062         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2063                 vmx->rmode.tr.selector = var->selector;
2064                 vmx->rmode.tr.base = var->base;
2065                 vmx->rmode.tr.limit = var->limit;
2066                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2067                 return;
2068         }
2069         vmcs_writel(sf->base, var->base);
2070         vmcs_write32(sf->limit, var->limit);
2071         vmcs_write16(sf->selector, var->selector);
2072         if (vmx->rmode.vm86_active && var->s) {
2073                 /*
2074                  * Hack real-mode segments into vm86 compatibility.
2075                  */
2076                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2077                         vmcs_writel(sf->base, 0xf0000);
2078                 ar = 0xf3;
2079         } else
2080                 ar = vmx_segment_access_rights(var);
2081
2082         /*
2083          *   Fix the "Accessed" bit in AR field of segment registers for older
2084          * qemu binaries.
2085          *   IA32 arch specifies that at the time of processor reset the
2086          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2087          * is setting it to 0 in the usedland code. This causes invalid guest
2088          * state vmexit when "unrestricted guest" mode is turned on.
2089          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2090          * tree. Newer qemu binaries with that qemu fix would not need this
2091          * kvm hack.
2092          */
2093         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2094                 ar |= 0x1; /* Accessed */
2095
2096         vmcs_write32(sf->ar_bytes, ar);
2097 }
2098
2099 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2100 {
2101         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2102
2103         *db = (ar >> 14) & 1;
2104         *l = (ar >> 13) & 1;
2105 }
2106
2107 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2108 {
2109         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2110         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2111 }
2112
2113 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2114 {
2115         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2116         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2117 }
2118
2119 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2120 {
2121         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2122         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2123 }
2124
2125 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2126 {
2127         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2128         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2129 }
2130
2131 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2132 {
2133         struct kvm_segment var;
2134         u32 ar;
2135
2136         vmx_get_segment(vcpu, &var, seg);
2137         ar = vmx_segment_access_rights(&var);
2138
2139         if (var.base != (var.selector << 4))
2140                 return false;
2141         if (var.limit != 0xffff)
2142                 return false;
2143         if (ar != 0xf3)
2144                 return false;
2145
2146         return true;
2147 }
2148
2149 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2150 {
2151         struct kvm_segment cs;
2152         unsigned int cs_rpl;
2153
2154         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2155         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2156
2157         if (cs.unusable)
2158                 return false;
2159         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2160                 return false;
2161         if (!cs.s)
2162                 return false;
2163         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2164                 if (cs.dpl > cs_rpl)
2165                         return false;
2166         } else {
2167                 if (cs.dpl != cs_rpl)
2168                         return false;
2169         }
2170         if (!cs.present)
2171                 return false;
2172
2173         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2174         return true;
2175 }
2176
2177 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2178 {
2179         struct kvm_segment ss;
2180         unsigned int ss_rpl;
2181
2182         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2183         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2184
2185         if (ss.unusable)
2186                 return true;
2187         if (ss.type != 3 && ss.type != 7)
2188                 return false;
2189         if (!ss.s)
2190                 return false;
2191         if (ss.dpl != ss_rpl) /* DPL != RPL */
2192                 return false;
2193         if (!ss.present)
2194                 return false;
2195
2196         return true;
2197 }
2198
2199 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2200 {
2201         struct kvm_segment var;
2202         unsigned int rpl;
2203
2204         vmx_get_segment(vcpu, &var, seg);
2205         rpl = var.selector & SELECTOR_RPL_MASK;
2206
2207         if (var.unusable)
2208                 return true;
2209         if (!var.s)
2210                 return false;
2211         if (!var.present)
2212                 return false;
2213         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2214                 if (var.dpl < rpl) /* DPL < RPL */
2215                         return false;
2216         }
2217
2218         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2219          * rights flags
2220          */
2221         return true;
2222 }
2223
2224 static bool tr_valid(struct kvm_vcpu *vcpu)
2225 {
2226         struct kvm_segment tr;
2227
2228         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2229
2230         if (tr.unusable)
2231                 return false;
2232         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2233                 return false;
2234         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2235                 return false;
2236         if (!tr.present)
2237                 return false;
2238
2239         return true;
2240 }
2241
2242 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2243 {
2244         struct kvm_segment ldtr;
2245
2246         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2247
2248         if (ldtr.unusable)
2249                 return true;
2250         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2251                 return false;
2252         if (ldtr.type != 2)
2253                 return false;
2254         if (!ldtr.present)
2255                 return false;
2256
2257         return true;
2258 }
2259
2260 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2261 {
2262         struct kvm_segment cs, ss;
2263
2264         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2265         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2266
2267         return ((cs.selector & SELECTOR_RPL_MASK) ==
2268                  (ss.selector & SELECTOR_RPL_MASK));
2269 }
2270
2271 /*
2272  * Check if guest state is valid. Returns true if valid, false if
2273  * not.
2274  * We assume that registers are always usable
2275  */
2276 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2277 {
2278         /* real mode guest state checks */
2279         if (!is_protmode(vcpu)) {
2280                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2281                         return false;
2282                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2283                         return false;
2284                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2285                         return false;
2286                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2287                         return false;
2288                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2289                         return false;
2290                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2291                         return false;
2292         } else {
2293         /* protected mode guest state checks */
2294                 if (!cs_ss_rpl_check(vcpu))
2295                         return false;
2296                 if (!code_segment_valid(vcpu))
2297                         return false;
2298                 if (!stack_segment_valid(vcpu))
2299                         return false;
2300                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2301                         return false;
2302                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2303                         return false;
2304                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2305                         return false;
2306                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2307                         return false;
2308                 if (!tr_valid(vcpu))
2309                         return false;
2310                 if (!ldtr_valid(vcpu))
2311                         return false;
2312         }
2313         /* TODO:
2314          * - Add checks on RIP
2315          * - Add checks on RFLAGS
2316          */
2317
2318         return true;
2319 }
2320
2321 static int init_rmode_tss(struct kvm *kvm)
2322 {
2323         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2324         u16 data = 0;
2325         int ret = 0;
2326         int r;
2327
2328         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2329         if (r < 0)
2330                 goto out;
2331         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2332         r = kvm_write_guest_page(kvm, fn++, &data,
2333                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2334         if (r < 0)
2335                 goto out;
2336         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2337         if (r < 0)
2338                 goto out;
2339         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2340         if (r < 0)
2341                 goto out;
2342         data = ~0;
2343         r = kvm_write_guest_page(kvm, fn, &data,
2344                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2345                                  sizeof(u8));
2346         if (r < 0)
2347                 goto out;
2348
2349         ret = 1;
2350 out:
2351         return ret;
2352 }
2353
2354 static int init_rmode_identity_map(struct kvm *kvm)
2355 {
2356         int i, r, ret;
2357         pfn_t identity_map_pfn;
2358         u32 tmp;
2359
2360         if (!enable_ept)
2361                 return 1;
2362         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2363                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2364                         "haven't been allocated!\n");
2365                 return 0;
2366         }
2367         if (likely(kvm->arch.ept_identity_pagetable_done))
2368                 return 1;
2369         ret = 0;
2370         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2371         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2372         if (r < 0)
2373                 goto out;
2374         /* Set up identity-mapping pagetable for EPT in real mode */
2375         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2376                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2377                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2378                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2379                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2380                 if (r < 0)
2381                         goto out;
2382         }
2383         kvm->arch.ept_identity_pagetable_done = true;
2384         ret = 1;
2385 out:
2386         return ret;
2387 }
2388
2389 static void seg_setup(int seg)
2390 {
2391         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2392         unsigned int ar;
2393
2394         vmcs_write16(sf->selector, 0);
2395         vmcs_writel(sf->base, 0);
2396         vmcs_write32(sf->limit, 0xffff);
2397         if (enable_unrestricted_guest) {
2398                 ar = 0x93;
2399                 if (seg == VCPU_SREG_CS)
2400                         ar |= 0x08; /* code segment */
2401         } else
2402                 ar = 0xf3;
2403
2404         vmcs_write32(sf->ar_bytes, ar);
2405 }
2406
2407 static int alloc_apic_access_page(struct kvm *kvm)
2408 {
2409         struct kvm_userspace_memory_region kvm_userspace_mem;
2410         int r = 0;
2411
2412         mutex_lock(&kvm->slots_lock);
2413         if (kvm->arch.apic_access_page)
2414                 goto out;
2415         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2416         kvm_userspace_mem.flags = 0;
2417         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2418         kvm_userspace_mem.memory_size = PAGE_SIZE;
2419         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2420         if (r)
2421                 goto out;
2422
2423         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2424 out:
2425         mutex_unlock(&kvm->slots_lock);
2426         return r;
2427 }
2428
2429 static int alloc_identity_pagetable(struct kvm *kvm)
2430 {
2431         struct kvm_userspace_memory_region kvm_userspace_mem;
2432         int r = 0;
2433
2434         mutex_lock(&kvm->slots_lock);
2435         if (kvm->arch.ept_identity_pagetable)
2436                 goto out;
2437         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2438         kvm_userspace_mem.flags = 0;
2439         kvm_userspace_mem.guest_phys_addr =
2440                 kvm->arch.ept_identity_map_addr;
2441         kvm_userspace_mem.memory_size = PAGE_SIZE;
2442         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2443         if (r)
2444                 goto out;
2445
2446         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2447                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2448 out:
2449         mutex_unlock(&kvm->slots_lock);
2450         return r;
2451 }
2452
2453 static void allocate_vpid(struct vcpu_vmx *vmx)
2454 {
2455         int vpid;
2456
2457         vmx->vpid = 0;
2458         if (!enable_vpid)
2459                 return;
2460         spin_lock(&vmx_vpid_lock);
2461         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2462         if (vpid < VMX_NR_VPIDS) {
2463                 vmx->vpid = vpid;
2464                 __set_bit(vpid, vmx_vpid_bitmap);
2465         }
2466         spin_unlock(&vmx_vpid_lock);
2467 }
2468
2469 static void free_vpid(struct vcpu_vmx *vmx)
2470 {
2471         if (!enable_vpid)
2472                 return;
2473         spin_lock(&vmx_vpid_lock);
2474         if (vmx->vpid != 0)
2475                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2476         spin_unlock(&vmx_vpid_lock);
2477 }
2478
2479 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2480 {
2481         int f = sizeof(unsigned long);
2482
2483         if (!cpu_has_vmx_msr_bitmap())
2484                 return;
2485
2486         /*
2487          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2488          * have the write-low and read-high bitmap offsets the wrong way round.
2489          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2490          */
2491         if (msr <= 0x1fff) {
2492                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2493                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2494         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2495                 msr &= 0x1fff;
2496                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2497                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2498         }
2499 }
2500
2501 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2502 {
2503         if (!longmode_only)
2504                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2505         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2506 }
2507
2508 /*
2509  * Sets up the vmcs for emulated real mode.
2510  */
2511 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2512 {
2513         u32 host_sysenter_cs, msr_low, msr_high;
2514         u32 junk;
2515         u64 host_pat, tsc_this, tsc_base;
2516         unsigned long a;
2517         struct desc_ptr dt;
2518         int i;
2519         unsigned long kvm_vmx_return;
2520         u32 exec_control;
2521
2522         /* I/O */
2523         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2524         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2525
2526         if (cpu_has_vmx_msr_bitmap())
2527                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2528
2529         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2530
2531         /* Control */
2532         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2533                 vmcs_config.pin_based_exec_ctrl);
2534
2535         exec_control = vmcs_config.cpu_based_exec_ctrl;
2536         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2537                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2538 #ifdef CONFIG_X86_64
2539                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2540                                 CPU_BASED_CR8_LOAD_EXITING;
2541 #endif
2542         }
2543         if (!enable_ept)
2544                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2545                                 CPU_BASED_CR3_LOAD_EXITING  |
2546                                 CPU_BASED_INVLPG_EXITING;
2547         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2548
2549         if (cpu_has_secondary_exec_ctrls()) {
2550                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2551                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2552                         exec_control &=
2553                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2554                 if (vmx->vpid == 0)
2555                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2556                 if (!enable_ept) {
2557                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2558                         enable_unrestricted_guest = 0;
2559                 }
2560                 if (!enable_unrestricted_guest)
2561                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2562                 if (!ple_gap)
2563                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2564                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2565         }
2566
2567         if (ple_gap) {
2568                 vmcs_write32(PLE_GAP, ple_gap);
2569                 vmcs_write32(PLE_WINDOW, ple_window);
2570         }
2571
2572         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2573         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2574         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2575
2576         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2577         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2578         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2579
2580         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2581         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2582         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2583         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2584         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2585         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2586 #ifdef CONFIG_X86_64
2587         rdmsrl(MSR_FS_BASE, a);
2588         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2589         rdmsrl(MSR_GS_BASE, a);
2590         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2591 #else
2592         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2593         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2594 #endif
2595
2596         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2597
2598         native_store_idt(&dt);
2599         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2600
2601         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2602         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2603         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2604         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2605         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2606         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2607         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2608
2609         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2610         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2611         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2612         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2613         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2614         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2615
2616         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2617                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2618                 host_pat = msr_low | ((u64) msr_high << 32);
2619                 vmcs_write64(HOST_IA32_PAT, host_pat);
2620         }
2621         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2622                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2623                 host_pat = msr_low | ((u64) msr_high << 32);
2624                 /* Write the default value follow host pat */
2625                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2626                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2627                 vmx->vcpu.arch.pat = host_pat;
2628         }
2629
2630         for (i = 0; i < NR_VMX_MSR; ++i) {
2631                 u32 index = vmx_msr_index[i];
2632                 u32 data_low, data_high;
2633                 int j = vmx->nmsrs;
2634
2635                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2636                         continue;
2637                 if (wrmsr_safe(index, data_low, data_high) < 0)
2638                         continue;
2639                 vmx->guest_msrs[j].index = i;
2640                 vmx->guest_msrs[j].data = 0;
2641                 vmx->guest_msrs[j].mask = -1ull;
2642                 ++vmx->nmsrs;
2643         }
2644
2645         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2646
2647         /* 22.2.1, 20.8.1 */
2648         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2649
2650         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2651         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2652         if (enable_ept)
2653                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2654         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2655
2656         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2657         rdtscll(tsc_this);
2658         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2659                 tsc_base = tsc_this;
2660
2661         guest_write_tsc(0, tsc_base);
2662
2663         return 0;
2664 }
2665
2666 static int init_rmode(struct kvm *kvm)
2667 {
2668         int idx, ret = 0;
2669
2670         idx = srcu_read_lock(&kvm->srcu);
2671         if (!init_rmode_tss(kvm))
2672                 goto exit;
2673         if (!init_rmode_identity_map(kvm))
2674                 goto exit;
2675
2676         ret = 1;
2677 exit:
2678         srcu_read_unlock(&kvm->srcu, idx);
2679         return ret;
2680 }
2681
2682 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2683 {
2684         struct vcpu_vmx *vmx = to_vmx(vcpu);
2685         u64 msr;
2686         int ret;
2687
2688         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2689         if (!init_rmode(vmx->vcpu.kvm)) {
2690                 ret = -ENOMEM;
2691                 goto out;
2692         }
2693
2694         vmx->rmode.vm86_active = 0;
2695
2696         vmx->soft_vnmi_blocked = 0;
2697
2698         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2699         kvm_set_cr8(&vmx->vcpu, 0);
2700         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2701         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2702                 msr |= MSR_IA32_APICBASE_BSP;
2703         kvm_set_apic_base(&vmx->vcpu, msr);
2704
2705         ret = fx_init(&vmx->vcpu);
2706         if (ret != 0)
2707                 goto out;
2708
2709         seg_setup(VCPU_SREG_CS);
2710         /*
2711          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2712          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2713          */
2714         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2715                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2716                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2717         } else {
2718                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2719                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2720         }
2721
2722         seg_setup(VCPU_SREG_DS);
2723         seg_setup(VCPU_SREG_ES);
2724         seg_setup(VCPU_SREG_FS);
2725         seg_setup(VCPU_SREG_GS);
2726         seg_setup(VCPU_SREG_SS);
2727
2728         vmcs_write16(GUEST_TR_SELECTOR, 0);
2729         vmcs_writel(GUEST_TR_BASE, 0);
2730         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2731         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2732
2733         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2734         vmcs_writel(GUEST_LDTR_BASE, 0);
2735         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2736         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2737
2738         vmcs_write32(GUEST_SYSENTER_CS, 0);
2739         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2740         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2741
2742         vmcs_writel(GUEST_RFLAGS, 0x02);
2743         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2744                 kvm_rip_write(vcpu, 0xfff0);
2745         else
2746                 kvm_rip_write(vcpu, 0);
2747         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2748
2749         vmcs_writel(GUEST_DR7, 0x400);
2750
2751         vmcs_writel(GUEST_GDTR_BASE, 0);
2752         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2753
2754         vmcs_writel(GUEST_IDTR_BASE, 0);
2755         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2756
2757         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2758         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2759         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2760
2761         /* Special registers */
2762         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2763
2764         setup_msrs(vmx);
2765
2766         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2767
2768         if (cpu_has_vmx_tpr_shadow()) {
2769                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2770                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2771                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2772                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2773                 vmcs_write32(TPR_THRESHOLD, 0);
2774         }
2775
2776         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2777                 vmcs_write64(APIC_ACCESS_ADDR,
2778                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2779
2780         if (vmx->vpid != 0)
2781                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2782
2783         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2784         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2785         vmx_set_cr4(&vmx->vcpu, 0);
2786         vmx_set_efer(&vmx->vcpu, 0);
2787         vmx_fpu_activate(&vmx->vcpu);
2788         update_exception_bitmap(&vmx->vcpu);
2789
2790         vpid_sync_context(vmx);
2791
2792         ret = 0;
2793
2794         /* HACK: Don't enable emulation on guest boot/reset */
2795         vmx->emulation_required = 0;
2796
2797 out:
2798         return ret;
2799 }
2800
2801 static void enable_irq_window(struct kvm_vcpu *vcpu)
2802 {
2803         u32 cpu_based_vm_exec_control;
2804
2805         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2806         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2807         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2808 }
2809
2810 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2811 {
2812         u32 cpu_based_vm_exec_control;
2813
2814         if (!cpu_has_virtual_nmis()) {
2815                 enable_irq_window(vcpu);
2816                 return;
2817         }
2818
2819         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2820         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2821         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2822 }
2823
2824 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2825 {
2826         struct vcpu_vmx *vmx = to_vmx(vcpu);
2827         uint32_t intr;
2828         int irq = vcpu->arch.interrupt.nr;
2829
2830         trace_kvm_inj_virq(irq);
2831
2832         ++vcpu->stat.irq_injections;
2833         if (vmx->rmode.vm86_active) {
2834                 vmx->rmode.irq.pending = true;
2835                 vmx->rmode.irq.vector = irq;
2836                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2837                 if (vcpu->arch.interrupt.soft)
2838                         vmx->rmode.irq.rip +=
2839                                 vmx->vcpu.arch.event_exit_inst_len;
2840                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2841                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2842                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2843                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2844                 return;
2845         }
2846         intr = irq | INTR_INFO_VALID_MASK;
2847         if (vcpu->arch.interrupt.soft) {
2848                 intr |= INTR_TYPE_SOFT_INTR;
2849                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2850                              vmx->vcpu.arch.event_exit_inst_len);
2851         } else
2852                 intr |= INTR_TYPE_EXT_INTR;
2853         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2854 }
2855
2856 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2857 {
2858         struct vcpu_vmx *vmx = to_vmx(vcpu);
2859
2860         if (!cpu_has_virtual_nmis()) {
2861                 /*
2862                  * Tracking the NMI-blocked state in software is built upon
2863                  * finding the next open IRQ window. This, in turn, depends on
2864                  * well-behaving guests: They have to keep IRQs disabled at
2865                  * least as long as the NMI handler runs. Otherwise we may
2866                  * cause NMI nesting, maybe breaking the guest. But as this is
2867                  * highly unlikely, we can live with the residual risk.
2868                  */
2869                 vmx->soft_vnmi_blocked = 1;
2870                 vmx->vnmi_blocked_time = 0;
2871         }
2872
2873         ++vcpu->stat.nmi_injections;
2874         if (vmx->rmode.vm86_active) {
2875                 vmx->rmode.irq.pending = true;
2876                 vmx->rmode.irq.vector = NMI_VECTOR;
2877                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2878                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2879                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2880                              INTR_INFO_VALID_MASK);
2881                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2882                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2883                 return;
2884         }
2885         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2886                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2887 }
2888
2889 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2890 {
2891         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2892                 return 0;
2893
2894         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2895                         (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2896 }
2897
2898 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2899 {
2900         if (!cpu_has_virtual_nmis())
2901                 return to_vmx(vcpu)->soft_vnmi_blocked;
2902         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2903 }
2904
2905 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2906 {
2907         struct vcpu_vmx *vmx = to_vmx(vcpu);
2908
2909         if (!cpu_has_virtual_nmis()) {
2910                 if (vmx->soft_vnmi_blocked != masked) {
2911                         vmx->soft_vnmi_blocked = masked;
2912                         vmx->vnmi_blocked_time = 0;
2913                 }
2914         } else {
2915                 if (masked)
2916                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2917                                       GUEST_INTR_STATE_NMI);
2918                 else
2919                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2920                                         GUEST_INTR_STATE_NMI);
2921         }
2922 }
2923
2924 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2925 {
2926         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2927                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2928                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2929 }
2930
2931 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2932 {
2933         int ret;
2934         struct kvm_userspace_memory_region tss_mem = {
2935                 .slot = TSS_PRIVATE_MEMSLOT,
2936                 .guest_phys_addr = addr,
2937                 .memory_size = PAGE_SIZE * 3,
2938                 .flags = 0,
2939         };
2940
2941         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2942         if (ret)
2943                 return ret;
2944         kvm->arch.tss_addr = addr;
2945         return 0;
2946 }
2947
2948 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2949                                   int vec, u32 err_code)
2950 {
2951         /*
2952          * Instruction with address size override prefix opcode 0x67
2953          * Cause the #SS fault with 0 error code in VM86 mode.
2954          */
2955         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2956                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2957                         return 1;
2958         /*
2959          * Forward all other exceptions that are valid in real mode.
2960          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2961          *        the required debugging infrastructure rework.
2962          */
2963         switch (vec) {
2964         case DB_VECTOR:
2965                 if (vcpu->guest_debug &
2966                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2967                         return 0;
2968                 kvm_queue_exception(vcpu, vec);
2969                 return 1;
2970         case BP_VECTOR:
2971                 /*
2972                  * Update instruction length as we may reinject the exception
2973                  * from user space while in guest debugging mode.
2974                  */
2975                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2976                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2977                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2978                         return 0;
2979                 /* fall through */
2980         case DE_VECTOR:
2981         case OF_VECTOR:
2982         case BR_VECTOR:
2983         case UD_VECTOR:
2984         case DF_VECTOR:
2985         case SS_VECTOR:
2986         case GP_VECTOR:
2987         case MF_VECTOR:
2988                 kvm_queue_exception(vcpu, vec);
2989                 return 1;
2990         }
2991         return 0;
2992 }
2993
2994 /*
2995  * Trigger machine check on the host. We assume all the MSRs are already set up
2996  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2997  * We pass a fake environment to the machine check handler because we want
2998  * the guest to be always treated like user space, no matter what context
2999  * it used internally.
3000  */
3001 static void kvm_machine_check(void)
3002 {
3003 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3004         struct pt_regs regs = {
3005                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3006                 .flags = X86_EFLAGS_IF,
3007         };
3008
3009         do_machine_check(&regs, 0);
3010 #endif
3011 }
3012
3013 static int handle_machine_check(struct kvm_vcpu *vcpu)
3014 {
3015         /* already handled by vcpu_run */
3016         return 1;
3017 }
3018
3019 static int handle_exception(struct kvm_vcpu *vcpu)
3020 {
3021         struct vcpu_vmx *vmx = to_vmx(vcpu);
3022         struct kvm_run *kvm_run = vcpu->run;
3023         u32 intr_info, ex_no, error_code;
3024         unsigned long cr2, rip, dr6;
3025         u32 vect_info;
3026         enum emulation_result er;
3027
3028         vect_info = vmx->idt_vectoring_info;
3029         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3030
3031         if (is_machine_check(intr_info))
3032                 return handle_machine_check(vcpu);
3033
3034         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3035             !is_page_fault(intr_info)) {
3036                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3037                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3038                 vcpu->run->internal.ndata = 2;
3039                 vcpu->run->internal.data[0] = vect_info;
3040                 vcpu->run->internal.data[1] = intr_info;
3041                 return 0;
3042         }
3043
3044         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3045                 return 1;  /* already handled by vmx_vcpu_run() */
3046
3047         if (is_no_device(intr_info)) {
3048                 vmx_fpu_activate(vcpu);
3049                 return 1;
3050         }
3051
3052         if (is_invalid_opcode(intr_info)) {
3053                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3054                 if (er != EMULATE_DONE)
3055                         kvm_queue_exception(vcpu, UD_VECTOR);
3056                 return 1;
3057         }
3058
3059         error_code = 0;
3060         rip = kvm_rip_read(vcpu);
3061         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3062                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3063         if (is_page_fault(intr_info)) {
3064                 /* EPT won't cause page fault directly */
3065                 if (enable_ept)
3066                         BUG();
3067                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3068                 trace_kvm_page_fault(cr2, error_code);
3069
3070                 if (kvm_event_needs_reinjection(vcpu))
3071                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3072                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3073         }
3074
3075         if (vmx->rmode.vm86_active &&
3076             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3077                                                                 error_code)) {
3078                 if (vcpu->arch.halt_request) {
3079                         vcpu->arch.halt_request = 0;
3080                         return kvm_emulate_halt(vcpu);
3081                 }
3082                 return 1;
3083         }
3084
3085         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3086         switch (ex_no) {
3087         case DB_VECTOR:
3088                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3089                 if (!(vcpu->guest_debug &
3090                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3091                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3092                         kvm_queue_exception(vcpu, DB_VECTOR);
3093                         return 1;
3094                 }
3095                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3096                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3097                 /* fall through */
3098         case BP_VECTOR:
3099                 /*
3100                  * Update instruction length as we may reinject #BP from
3101                  * user space while in guest debugging mode. Reading it for
3102                  * #DB as well causes no harm, it is not used in that case.
3103                  */
3104                 vmx->vcpu.arch.event_exit_inst_len =
3105                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3106                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3107                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3108                 kvm_run->debug.arch.exception = ex_no;
3109                 break;
3110         default:
3111                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3112                 kvm_run->ex.exception = ex_no;
3113                 kvm_run->ex.error_code = error_code;
3114                 break;
3115         }
3116         return 0;
3117 }
3118
3119 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3120 {
3121         ++vcpu->stat.irq_exits;
3122         return 1;
3123 }
3124
3125 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3126 {
3127         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3128         return 0;
3129 }
3130
3131 static int handle_io(struct kvm_vcpu *vcpu)
3132 {
3133         unsigned long exit_qualification;
3134         int size, in, string;
3135         unsigned port;
3136
3137         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3138         string = (exit_qualification & 16) != 0;
3139         in = (exit_qualification & 8) != 0;
3140
3141         ++vcpu->stat.io_exits;
3142
3143         if (string || in)
3144                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3145
3146         port = exit_qualification >> 16;
3147         size = (exit_qualification & 7) + 1;
3148         skip_emulated_instruction(vcpu);
3149
3150         return kvm_fast_pio_out(vcpu, size, port);
3151 }
3152
3153 static void
3154 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3155 {
3156         /*
3157          * Patch in the VMCALL instruction:
3158          */
3159         hypercall[0] = 0x0f;
3160         hypercall[1] = 0x01;
3161         hypercall[2] = 0xc1;
3162 }
3163
3164 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3165 {
3166         if (err)
3167                 kvm_inject_gp(vcpu, 0);
3168         else
3169                 skip_emulated_instruction(vcpu);
3170 }
3171
3172 static int handle_cr(struct kvm_vcpu *vcpu)
3173 {
3174         unsigned long exit_qualification, val;
3175         int cr;
3176         int reg;
3177         int err;
3178
3179         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3180         cr = exit_qualification & 15;
3181         reg = (exit_qualification >> 8) & 15;
3182         switch ((exit_qualification >> 4) & 3) {
3183         case 0: /* mov to cr */
3184                 val = kvm_register_read(vcpu, reg);
3185                 trace_kvm_cr_write(cr, val);
3186                 switch (cr) {
3187                 case 0:
3188                         err = kvm_set_cr0(vcpu, val);
3189                         complete_insn_gp(vcpu, err);
3190                         return 1;
3191                 case 3:
3192                         err = kvm_set_cr3(vcpu, val);
3193                         complete_insn_gp(vcpu, err);
3194                         return 1;
3195                 case 4:
3196                         err = kvm_set_cr4(vcpu, val);
3197                         complete_insn_gp(vcpu, err);
3198                         return 1;
3199                 case 8: {
3200                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3201                                 u8 cr8 = kvm_register_read(vcpu, reg);
3202                                 kvm_set_cr8(vcpu, cr8);
3203                                 skip_emulated_instruction(vcpu);
3204                                 if (irqchip_in_kernel(vcpu->kvm))
3205                                         return 1;
3206                                 if (cr8_prev <= cr8)
3207                                         return 1;
3208                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3209                                 return 0;
3210                         }
3211                 };
3212                 break;
3213         case 2: /* clts */
3214                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3215                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3216                 skip_emulated_instruction(vcpu);
3217                 vmx_fpu_activate(vcpu);
3218                 return 1;
3219         case 1: /*mov from cr*/
3220                 switch (cr) {
3221                 case 3:
3222                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3223                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3224                         skip_emulated_instruction(vcpu);
3225                         return 1;
3226                 case 8:
3227                         val = kvm_get_cr8(vcpu);
3228                         kvm_register_write(vcpu, reg, val);
3229                         trace_kvm_cr_read(cr, val);
3230                         skip_emulated_instruction(vcpu);
3231                         return 1;
3232                 }
3233                 break;
3234         case 3: /* lmsw */
3235                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3236                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3237                 kvm_lmsw(vcpu, val);
3238
3239                 skip_emulated_instruction(vcpu);
3240                 return 1;
3241         default:
3242                 break;
3243         }
3244         vcpu->run->exit_reason = 0;
3245         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3246                (int)(exit_qualification >> 4) & 3, cr);
3247         return 0;
3248 }
3249
3250 static int handle_dr(struct kvm_vcpu *vcpu)
3251 {
3252         unsigned long exit_qualification;
3253         int dr, reg;
3254
3255         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3256         if (!kvm_require_cpl(vcpu, 0))
3257                 return 1;
3258         dr = vmcs_readl(GUEST_DR7);
3259         if (dr & DR7_GD) {
3260                 /*
3261                  * As the vm-exit takes precedence over the debug trap, we
3262                  * need to emulate the latter, either for the host or the
3263                  * guest debugging itself.
3264                  */
3265                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3266                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3267                         vcpu->run->debug.arch.dr7 = dr;
3268                         vcpu->run->debug.arch.pc =
3269                                 vmcs_readl(GUEST_CS_BASE) +
3270                                 vmcs_readl(GUEST_RIP);
3271                         vcpu->run->debug.arch.exception = DB_VECTOR;
3272                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3273                         return 0;
3274                 } else {
3275                         vcpu->arch.dr7 &= ~DR7_GD;
3276                         vcpu->arch.dr6 |= DR6_BD;
3277                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3278                         kvm_queue_exception(vcpu, DB_VECTOR);
3279                         return 1;
3280                 }
3281         }
3282
3283         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3284         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3285         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3286         if (exit_qualification & TYPE_MOV_FROM_DR) {
3287                 unsigned long val;
3288                 if (!kvm_get_dr(vcpu, dr, &val))
3289                         kvm_register_write(vcpu, reg, val);
3290         } else
3291                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3292         skip_emulated_instruction(vcpu);
3293         return 1;
3294 }
3295
3296 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3297 {
3298         vmcs_writel(GUEST_DR7, val);
3299 }
3300
3301 static int handle_cpuid(struct kvm_vcpu *vcpu)
3302 {
3303         kvm_emulate_cpuid(vcpu);
3304         return 1;
3305 }
3306
3307 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3308 {
3309         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3310         u64 data;
3311
3312         if (vmx_get_msr(vcpu, ecx, &data)) {
3313                 trace_kvm_msr_read_ex(ecx);
3314                 kvm_inject_gp(vcpu, 0);
3315                 return 1;
3316         }
3317
3318         trace_kvm_msr_read(ecx, data);
3319
3320         /* FIXME: handling of bits 32:63 of rax, rdx */
3321         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3322         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3323         skip_emulated_instruction(vcpu);
3324         return 1;
3325 }
3326
3327 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3328 {
3329         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3330         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3331                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3332
3333         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3334                 trace_kvm_msr_write_ex(ecx, data);
3335                 kvm_inject_gp(vcpu, 0);
3336                 return 1;
3337         }
3338
3339         trace_kvm_msr_write(ecx, data);
3340         skip_emulated_instruction(vcpu);
3341         return 1;
3342 }
3343
3344 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3345 {
3346         return 1;
3347 }
3348
3349 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3350 {
3351         u32 cpu_based_vm_exec_control;
3352
3353         /* clear pending irq */
3354         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3355         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3356         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3357
3358         ++vcpu->stat.irq_window_exits;
3359
3360         /*
3361          * If the user space waits to inject interrupts, exit as soon as
3362          * possible
3363          */
3364         if (!irqchip_in_kernel(vcpu->kvm) &&
3365             vcpu->run->request_interrupt_window &&
3366             !kvm_cpu_has_interrupt(vcpu)) {
3367                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3368                 return 0;
3369         }
3370         return 1;
3371 }
3372
3373 static int handle_halt(struct kvm_vcpu *vcpu)
3374 {
3375         skip_emulated_instruction(vcpu);
3376         return kvm_emulate_halt(vcpu);
3377 }
3378
3379 static int handle_vmcall(struct kvm_vcpu *vcpu)
3380 {
3381         skip_emulated_instruction(vcpu);
3382         kvm_emulate_hypercall(vcpu);
3383         return 1;
3384 }
3385
3386 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3387 {
3388         kvm_queue_exception(vcpu, UD_VECTOR);
3389         return 1;
3390 }
3391
3392 static int handle_invlpg(struct kvm_vcpu *vcpu)
3393 {
3394         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3395
3396         kvm_mmu_invlpg(vcpu, exit_qualification);
3397         skip_emulated_instruction(vcpu);
3398         return 1;
3399 }
3400
3401 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3402 {
3403         skip_emulated_instruction(vcpu);
3404         kvm_emulate_wbinvd(vcpu);
3405         return 1;
3406 }
3407
3408 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3409 {
3410         u64 new_bv = kvm_read_edx_eax(vcpu);
3411         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3412
3413         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3414                 skip_emulated_instruction(vcpu);
3415         return 1;
3416 }
3417
3418 static int handle_apic_access(struct kvm_vcpu *vcpu)
3419 {
3420         return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3421 }
3422
3423 static int handle_task_switch(struct kvm_vcpu *vcpu)
3424 {
3425         struct vcpu_vmx *vmx = to_vmx(vcpu);
3426         unsigned long exit_qualification;
3427         bool has_error_code = false;
3428         u32 error_code = 0;
3429         u16 tss_selector;
3430         int reason, type, idt_v;
3431
3432         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3433         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3434
3435         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3436
3437         reason = (u32)exit_qualification >> 30;
3438         if (reason == TASK_SWITCH_GATE && idt_v) {
3439                 switch (type) {
3440                 case INTR_TYPE_NMI_INTR:
3441                         vcpu->arch.nmi_injected = false;
3442                         if (cpu_has_virtual_nmis())
3443                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3444                                               GUEST_INTR_STATE_NMI);
3445                         break;
3446                 case INTR_TYPE_EXT_INTR:
3447                 case INTR_TYPE_SOFT_INTR:
3448                         kvm_clear_interrupt_queue(vcpu);
3449                         break;
3450                 case INTR_TYPE_HARD_EXCEPTION:
3451                         if (vmx->idt_vectoring_info &
3452                             VECTORING_INFO_DELIVER_CODE_MASK) {
3453                                 has_error_code = true;
3454                                 error_code =
3455                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3456                         }
3457                         /* fall through */
3458                 case INTR_TYPE_SOFT_EXCEPTION:
3459                         kvm_clear_exception_queue(vcpu);
3460                         break;
3461                 default:
3462                         break;
3463                 }
3464         }
3465         tss_selector = exit_qualification;
3466
3467         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3468                        type != INTR_TYPE_EXT_INTR &&
3469                        type != INTR_TYPE_NMI_INTR))
3470                 skip_emulated_instruction(vcpu);
3471
3472         if (kvm_task_switch(vcpu, tss_selector, reason,
3473                                 has_error_code, error_code) == EMULATE_FAIL) {
3474                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3475                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3476                 vcpu->run->internal.ndata = 0;
3477                 return 0;
3478         }
3479
3480         /* clear all local breakpoint enable flags */
3481         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3482
3483         /*
3484          * TODO: What about debug traps on tss switch?
3485          *       Are we supposed to inject them and update dr6?
3486          */
3487
3488         return 1;
3489 }
3490
3491 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3492 {
3493         unsigned long exit_qualification;
3494         gpa_t gpa;
3495         int gla_validity;
3496
3497         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3498
3499         if (exit_qualification & (1 << 6)) {
3500                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3501                 return -EINVAL;
3502         }
3503
3504         gla_validity = (exit_qualification >> 7) & 0x3;
3505         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3506                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3507                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3508                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3509                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3510                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3511                         (long unsigned int)exit_qualification);
3512                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3513                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3514                 return 0;
3515         }
3516
3517         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3518         trace_kvm_page_fault(gpa, exit_qualification);
3519         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3520 }
3521
3522 static u64 ept_rsvd_mask(u64 spte, int level)
3523 {
3524         int i;
3525         u64 mask = 0;
3526
3527         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3528                 mask |= (1ULL << i);
3529
3530         if (level > 2)
3531                 /* bits 7:3 reserved */
3532                 mask |= 0xf8;
3533         else if (level == 2) {
3534                 if (spte & (1ULL << 7))
3535                         /* 2MB ref, bits 20:12 reserved */
3536                         mask |= 0x1ff000;
3537                 else
3538                         /* bits 6:3 reserved */
3539                         mask |= 0x78;
3540         }
3541
3542         return mask;
3543 }
3544
3545 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3546                                        int level)
3547 {
3548         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3549
3550         /* 010b (write-only) */
3551         WARN_ON((spte & 0x7) == 0x2);
3552
3553         /* 110b (write/execute) */
3554         WARN_ON((spte & 0x7) == 0x6);
3555
3556         /* 100b (execute-only) and value not supported by logical processor */
3557         if (!cpu_has_vmx_ept_execute_only())
3558                 WARN_ON((spte & 0x7) == 0x4);
3559
3560         /* not 000b */
3561         if ((spte & 0x7)) {
3562                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3563
3564                 if (rsvd_bits != 0) {
3565                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3566                                          __func__, rsvd_bits);
3567                         WARN_ON(1);
3568                 }
3569
3570                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3571                         u64 ept_mem_type = (spte & 0x38) >> 3;
3572
3573                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3574                             ept_mem_type == 7) {
3575                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3576                                                 __func__, ept_mem_type);
3577                                 WARN_ON(1);
3578                         }
3579                 }
3580         }
3581 }
3582
3583 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3584 {
3585         u64 sptes[4];
3586         int nr_sptes, i;
3587         gpa_t gpa;
3588
3589         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3590
3591         printk(KERN_ERR "EPT: Misconfiguration.\n");
3592         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3593
3594         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3595
3596         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3597                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3598
3599         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3600         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3601
3602         return 0;
3603 }
3604
3605 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3606 {
3607         u32 cpu_based_vm_exec_control;
3608
3609         /* clear pending NMI */
3610         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3611         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3612         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3613         ++vcpu->stat.nmi_window_exits;
3614
3615         return 1;
3616 }
3617
3618 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3619 {
3620         struct vcpu_vmx *vmx = to_vmx(vcpu);
3621         enum emulation_result err = EMULATE_DONE;
3622         int ret = 1;
3623
3624         while (!guest_state_valid(vcpu)) {
3625                 err = emulate_instruction(vcpu, 0, 0, 0);
3626
3627                 if (err == EMULATE_DO_MMIO) {
3628                         ret = 0;
3629                         goto out;
3630                 }
3631
3632                 if (err != EMULATE_DONE)
3633                         return 0;
3634
3635                 if (signal_pending(current))
3636                         goto out;
3637                 if (need_resched())
3638                         schedule();
3639         }
3640
3641         vmx->emulation_required = 0;
3642 out:
3643         return ret;
3644 }
3645
3646 /*
3647  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3648  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3649  */
3650 static int handle_pause(struct kvm_vcpu *vcpu)
3651 {
3652         skip_emulated_instruction(vcpu);
3653         kvm_vcpu_on_spin(vcpu);
3654
3655         return 1;
3656 }
3657
3658 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3659 {
3660         kvm_queue_exception(vcpu, UD_VECTOR);
3661         return 1;
3662 }
3663
3664 /*
3665  * The exit handlers return 1 if the exit was handled fully and guest execution
3666  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3667  * to be done to userspace and return 0.
3668  */
3669 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3670         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3671         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3672         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3673         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3674         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3675         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3676         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3677         [EXIT_REASON_CPUID]                   = handle_cpuid,
3678         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3679         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3680         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3681         [EXIT_REASON_HLT]                     = handle_halt,
3682         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3683         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3684         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3685         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3686         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3687         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3688         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3689         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3690         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3691         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3692         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3693         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3694         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3695         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3696         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3697         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3698         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3699         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3700         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3701         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3702         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3703         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3704 };
3705
3706 static const int kvm_vmx_max_exit_handlers =
3707         ARRAY_SIZE(kvm_vmx_exit_handlers);
3708
3709 /*
3710  * The guest has exited.  See if we can fix it or if we need userspace
3711  * assistance.
3712  */
3713 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3714 {
3715         struct vcpu_vmx *vmx = to_vmx(vcpu);
3716         u32 exit_reason = vmx->exit_reason;
3717         u32 vectoring_info = vmx->idt_vectoring_info;
3718
3719         trace_kvm_exit(exit_reason, vcpu);
3720
3721         /* If guest state is invalid, start emulating */
3722         if (vmx->emulation_required && emulate_invalid_guest_state)
3723                 return handle_invalid_guest_state(vcpu);
3724
3725         /* Access CR3 don't cause VMExit in paging mode, so we need
3726          * to sync with guest real CR3. */
3727         if (enable_ept && is_paging(vcpu))
3728                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3729
3730         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3731                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3732                 vcpu->run->fail_entry.hardware_entry_failure_reason
3733                         = exit_reason;
3734                 return 0;
3735         }
3736
3737         if (unlikely(vmx->fail)) {
3738                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3739                 vcpu->run->fail_entry.hardware_entry_failure_reason
3740                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3741                 return 0;
3742         }
3743
3744         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3745                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3746                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3747                         exit_reason != EXIT_REASON_TASK_SWITCH))
3748                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3749                        "(0x%x) and exit reason is 0x%x\n",
3750                        __func__, vectoring_info, exit_reason);
3751
3752         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3753                 if (vmx_interrupt_allowed(vcpu)) {
3754                         vmx->soft_vnmi_blocked = 0;
3755                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3756                            vcpu->arch.nmi_pending) {
3757                         /*
3758                          * This CPU don't support us in finding the end of an
3759                          * NMI-blocked window if the guest runs with IRQs
3760                          * disabled. So we pull the trigger after 1 s of
3761                          * futile waiting, but inform the user about this.
3762                          */
3763                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3764                                "state on VCPU %d after 1 s timeout\n",
3765                                __func__, vcpu->vcpu_id);
3766                         vmx->soft_vnmi_blocked = 0;
3767                 }
3768         }
3769
3770         if (exit_reason < kvm_vmx_max_exit_handlers
3771             && kvm_vmx_exit_handlers[exit_reason])
3772                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3773         else {
3774                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3775                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3776         }
3777         return 0;
3778 }
3779
3780 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3781 {
3782         if (irr == -1 || tpr < irr) {
3783                 vmcs_write32(TPR_THRESHOLD, 0);
3784                 return;
3785         }
3786
3787         vmcs_write32(TPR_THRESHOLD, irr);
3788 }
3789
3790 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3791 {
3792         u32 exit_intr_info;
3793         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3794         bool unblock_nmi;
3795         u8 vector;
3796         int type;
3797         bool idtv_info_valid;
3798
3799         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3800
3801         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3802
3803         /* Handle machine checks before interrupts are enabled */
3804         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3805             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3806                 && is_machine_check(exit_intr_info)))
3807                 kvm_machine_check();
3808
3809         /* We need to handle NMIs before interrupts are enabled */
3810         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3811             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3812                 kvm_before_handle_nmi(&vmx->vcpu);
3813                 asm("int $2");
3814                 kvm_after_handle_nmi(&vmx->vcpu);
3815         }
3816
3817         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3818
3819         if (cpu_has_virtual_nmis()) {
3820                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3821                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3822                 /*
3823                  * SDM 3: 27.7.1.2 (September 2008)
3824                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3825                  * a guest IRET fault.
3826                  * SDM 3: 23.2.2 (September 2008)
3827                  * Bit 12 is undefined in any of the following cases:
3828                  *  If the VM exit sets the valid bit in the IDT-vectoring
3829                  *   information field.
3830                  *  If the VM exit is due to a double fault.
3831                  */
3832                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3833                     vector != DF_VECTOR && !idtv_info_valid)
3834                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3835                                       GUEST_INTR_STATE_NMI);
3836         } else if (unlikely(vmx->soft_vnmi_blocked))
3837                 vmx->vnmi_blocked_time +=
3838                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3839
3840         vmx->vcpu.arch.nmi_injected = false;
3841         kvm_clear_exception_queue(&vmx->vcpu);
3842         kvm_clear_interrupt_queue(&vmx->vcpu);
3843
3844         if (!idtv_info_valid)
3845                 return;
3846
3847         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3848         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3849
3850         switch (type) {
3851         case INTR_TYPE_NMI_INTR:
3852                 vmx->vcpu.arch.nmi_injected = true;
3853                 /*
3854                  * SDM 3: 27.7.1.2 (September 2008)
3855                  * Clear bit "block by NMI" before VM entry if a NMI
3856                  * delivery faulted.
3857                  */
3858                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3859                                 GUEST_INTR_STATE_NMI);
3860                 break;
3861         case INTR_TYPE_SOFT_EXCEPTION:
3862                 vmx->vcpu.arch.event_exit_inst_len =
3863                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3864                 /* fall through */
3865         case INTR_TYPE_HARD_EXCEPTION:
3866                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3867                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3868                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3869                 } else
3870                         kvm_queue_exception(&vmx->vcpu, vector);
3871                 break;
3872         case INTR_TYPE_SOFT_INTR:
3873                 vmx->vcpu.arch.event_exit_inst_len =
3874                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3875                 /* fall through */
3876         case INTR_TYPE_EXT_INTR:
3877                 kvm_queue_interrupt(&vmx->vcpu, vector,
3878                         type == INTR_TYPE_SOFT_INTR);
3879                 break;
3880         default:
3881                 break;
3882         }
3883 }
3884
3885 /*
3886  * Failure to inject an interrupt should give us the information
3887  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3888  * when fetching the interrupt redirection bitmap in the real-mode
3889  * tss, this doesn't happen.  So we do it ourselves.
3890  */
3891 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3892 {
3893         vmx->rmode.irq.pending = 0;
3894         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3895                 return;
3896         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3897         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3898                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3899                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3900                 return;
3901         }
3902         vmx->idt_vectoring_info =
3903                 VECTORING_INFO_VALID_MASK
3904                 | INTR_TYPE_EXT_INTR
3905                 | vmx->rmode.irq.vector;
3906 }
3907
3908 #ifdef CONFIG_X86_64
3909 #define R "r"
3910 #define Q "q"
3911 #else
3912 #define R "e"
3913 #define Q "l"
3914 #endif
3915
3916 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3917 {
3918         struct vcpu_vmx *vmx = to_vmx(vcpu);
3919
3920         /* Record the guest's net vcpu time for enforced NMI injections. */
3921         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3922                 vmx->entry_time = ktime_get();
3923
3924         /* Don't enter VMX if guest state is invalid, let the exit handler
3925            start emulation until we arrive back to a valid state */
3926         if (vmx->emulation_required && emulate_invalid_guest_state)
3927                 return;
3928
3929         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3930                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3931         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3932                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3933
3934         /* When single-stepping over STI and MOV SS, we must clear the
3935          * corresponding interruptibility bits in the guest state. Otherwise
3936          * vmentry fails as it then expects bit 14 (BS) in pending debug
3937          * exceptions being set, but that's not correct for the guest debugging
3938          * case. */
3939         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3940                 vmx_set_interrupt_shadow(vcpu, 0);
3941
3942         asm(
3943                 /* Store host registers */
3944                 "push %%"R"dx; push %%"R"bp;"
3945                 "push %%"R"cx \n\t"
3946                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3947                 "je 1f \n\t"
3948                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3949                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3950                 "1: \n\t"
3951                 /* Reload cr2 if changed */
3952                 "mov %c[cr2](%0), %%"R"ax \n\t"
3953                 "mov %%cr2, %%"R"dx \n\t"
3954                 "cmp %%"R"ax, %%"R"dx \n\t"
3955                 "je 2f \n\t"
3956                 "mov %%"R"ax, %%cr2 \n\t"
3957                 "2: \n\t"
3958                 /* Check if vmlaunch of vmresume is needed */
3959                 "cmpl $0, %c[launched](%0) \n\t"
3960                 /* Load guest registers.  Don't clobber flags. */
3961                 "mov %c[rax](%0), %%"R"ax \n\t"
3962                 "mov %c[rbx](%0), %%"R"bx \n\t"
3963                 "mov %c[rdx](%0), %%"R"dx \n\t"
3964                 "mov %c[rsi](%0), %%"R"si \n\t"
3965                 "mov %c[rdi](%0), %%"R"di \n\t"
3966                 "mov %c[rbp](%0), %%"R"bp \n\t"
3967 #ifdef CONFIG_X86_64
3968                 "mov %c[r8](%0),  %%r8  \n\t"
3969                 "mov %c[r9](%0),  %%r9  \n\t"
3970                 "mov %c[r10](%0), %%r10 \n\t"
3971                 "mov %c[r11](%0), %%r11 \n\t"
3972                 "mov %c[r12](%0), %%r12 \n\t"
3973                 "mov %c[r13](%0), %%r13 \n\t"
3974                 "mov %c[r14](%0), %%r14 \n\t"
3975                 "mov %c[r15](%0), %%r15 \n\t"
3976 #endif
3977                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3978
3979                 /* Enter guest mode */
3980                 "jne .Llaunched \n\t"
3981                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3982                 "jmp .Lkvm_vmx_return \n\t"
3983                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3984                 ".Lkvm_vmx_return: "
3985                 /* Save guest registers, load host registers, keep flags */
3986                 "xchg %0,     (%%"R"sp) \n\t"
3987                 "mov %%"R"ax, %c[rax](%0) \n\t"
3988                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3989                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3990                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3991                 "mov %%"R"si, %c[rsi](%0) \n\t"
3992                 "mov %%"R"di, %c[rdi](%0) \n\t"
3993                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3994 #ifdef CONFIG_X86_64
3995                 "mov %%r8,  %c[r8](%0) \n\t"
3996                 "mov %%r9,  %c[r9](%0) \n\t"
3997                 "mov %%r10, %c[r10](%0) \n\t"
3998                 "mov %%r11, %c[r11](%0) \n\t"
3999                 "mov %%r12, %c[r12](%0) \n\t"
4000                 "mov %%r13, %c[r13](%0) \n\t"
4001                 "mov %%r14, %c[r14](%0) \n\t"
4002                 "mov %%r15, %c[r15](%0) \n\t"
4003 #endif
4004                 "mov %%cr2, %%"R"ax   \n\t"
4005                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4006
4007                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
4008                 "setbe %c[fail](%0) \n\t"
4009               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4010                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4011                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4012                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4013                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4014                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4015                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4016                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4017                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4018                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4019                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4020 #ifdef CONFIG_X86_64
4021                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4022                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4023                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4024                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4025                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4026                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4027                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4028                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4029 #endif
4030                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4031               : "cc", "memory"
4032                 , R"bx", R"di", R"si"
4033 #ifdef CONFIG_X86_64
4034                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4035 #endif
4036               );
4037
4038         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4039                                   | (1 << VCPU_EXREG_PDPTR));
4040         vcpu->arch.regs_dirty = 0;
4041
4042         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4043         if (vmx->rmode.irq.pending)
4044                 fixup_rmode_irq(vmx);
4045
4046         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4047         vmx->launched = 1;
4048
4049         vmx_complete_interrupts(vmx);
4050 }
4051
4052 #undef R
4053 #undef Q
4054
4055 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4056 {
4057         struct vcpu_vmx *vmx = to_vmx(vcpu);
4058
4059         if (vmx->vmcs) {
4060                 vcpu_clear(vmx);
4061                 free_vmcs(vmx->vmcs);
4062                 vmx->vmcs = NULL;
4063         }
4064 }
4065
4066 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4067 {
4068         struct vcpu_vmx *vmx = to_vmx(vcpu);
4069
4070         free_vpid(vmx);
4071         vmx_free_vmcs(vcpu);
4072         kfree(vmx->guest_msrs);
4073         kvm_vcpu_uninit(vcpu);
4074         kmem_cache_free(kvm_vcpu_cache, vmx);
4075 }
4076
4077 static inline void vmcs_init(struct vmcs *vmcs)
4078 {
4079         u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4080
4081         if (!vmm_exclusive)
4082                 kvm_cpu_vmxon(phys_addr);
4083
4084         vmcs_clear(vmcs);
4085
4086         if (!vmm_exclusive)
4087                 kvm_cpu_vmxoff();
4088 }
4089
4090 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4091 {
4092         int err;
4093         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4094         int cpu;
4095
4096         if (!vmx)
4097                 return ERR_PTR(-ENOMEM);
4098
4099         allocate_vpid(vmx);
4100
4101         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4102         if (err)
4103                 goto free_vcpu;
4104
4105         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4106         if (!vmx->guest_msrs) {
4107                 err = -ENOMEM;
4108                 goto uninit_vcpu;
4109         }
4110
4111         vmx->vmcs = alloc_vmcs();
4112         if (!vmx->vmcs)
4113                 goto free_msrs;
4114
4115         vmcs_init(vmx->vmcs);
4116
4117         cpu = get_cpu();
4118         vmx_vcpu_load(&vmx->vcpu, cpu);
4119         err = vmx_vcpu_setup(vmx);
4120         vmx_vcpu_put(&vmx->vcpu);
4121         put_cpu();
4122         if (err)
4123                 goto free_vmcs;
4124         if (vm_need_virtualize_apic_accesses(kvm))
4125                 if (alloc_apic_access_page(kvm) != 0)
4126                         goto free_vmcs;
4127
4128         if (enable_ept) {
4129                 if (!kvm->arch.ept_identity_map_addr)
4130                         kvm->arch.ept_identity_map_addr =
4131                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4132                 if (alloc_identity_pagetable(kvm) != 0)
4133                         goto free_vmcs;
4134         }
4135
4136         return &vmx->vcpu;
4137
4138 free_vmcs:
4139         free_vmcs(vmx->vmcs);
4140 free_msrs:
4141         kfree(vmx->guest_msrs);
4142 uninit_vcpu:
4143         kvm_vcpu_uninit(&vmx->vcpu);
4144 free_vcpu:
4145         free_vpid(vmx);
4146         kmem_cache_free(kvm_vcpu_cache, vmx);
4147         return ERR_PTR(err);
4148 }
4149
4150 static void __init vmx_check_processor_compat(void *rtn)
4151 {
4152         struct vmcs_config vmcs_conf;
4153
4154         *(int *)rtn = 0;
4155         if (setup_vmcs_config(&vmcs_conf) < 0)
4156                 *(int *)rtn = -EIO;
4157         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4158                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4159                                 smp_processor_id());
4160                 *(int *)rtn = -EIO;
4161         }
4162 }
4163
4164 static int get_ept_level(void)
4165 {
4166         return VMX_EPT_DEFAULT_GAW + 1;
4167 }
4168
4169 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4170 {
4171         u64 ret;
4172
4173         /* For VT-d and EPT combination
4174          * 1. MMIO: always map as UC
4175          * 2. EPT with VT-d:
4176          *   a. VT-d without snooping control feature: can't guarantee the
4177          *      result, try to trust guest.
4178          *   b. VT-d with snooping control feature: snooping control feature of
4179          *      VT-d engine can guarantee the cache correctness. Just set it
4180          *      to WB to keep consistent with host. So the same as item 3.
4181          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4182          *    consistent with host MTRR
4183          */
4184         if (is_mmio)
4185                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4186         else if (vcpu->kvm->arch.iommu_domain &&
4187                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4188                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4189                       VMX_EPT_MT_EPTE_SHIFT;
4190         else
4191                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4192                         | VMX_EPT_IPAT_BIT;
4193
4194         return ret;
4195 }
4196
4197 #define _ER(x) { EXIT_REASON_##x, #x }
4198
4199 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4200         _ER(EXCEPTION_NMI),
4201         _ER(EXTERNAL_INTERRUPT),
4202         _ER(TRIPLE_FAULT),
4203         _ER(PENDING_INTERRUPT),
4204         _ER(NMI_WINDOW),
4205         _ER(TASK_SWITCH),
4206         _ER(CPUID),
4207         _ER(HLT),
4208         _ER(INVLPG),
4209         _ER(RDPMC),
4210         _ER(RDTSC),
4211         _ER(VMCALL),
4212         _ER(VMCLEAR),
4213         _ER(VMLAUNCH),
4214         _ER(VMPTRLD),
4215         _ER(VMPTRST),
4216         _ER(VMREAD),
4217         _ER(VMRESUME),
4218         _ER(VMWRITE),
4219         _ER(VMOFF),
4220         _ER(VMON),
4221         _ER(CR_ACCESS),
4222         _ER(DR_ACCESS),
4223         _ER(IO_INSTRUCTION),
4224         _ER(MSR_READ),
4225         _ER(MSR_WRITE),
4226         _ER(MWAIT_INSTRUCTION),
4227         _ER(MONITOR_INSTRUCTION),
4228         _ER(PAUSE_INSTRUCTION),
4229         _ER(MCE_DURING_VMENTRY),
4230         _ER(TPR_BELOW_THRESHOLD),
4231         _ER(APIC_ACCESS),
4232         _ER(EPT_VIOLATION),
4233         _ER(EPT_MISCONFIG),
4234         _ER(WBINVD),
4235         { -1, NULL }
4236 };
4237
4238 #undef _ER
4239
4240 static int vmx_get_lpage_level(void)
4241 {
4242         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4243                 return PT_DIRECTORY_LEVEL;
4244         else
4245                 /* For shadow and EPT supported 1GB page */
4246                 return PT_PDPE_LEVEL;
4247 }
4248
4249 static inline u32 bit(int bitno)
4250 {
4251         return 1 << (bitno & 31);
4252 }
4253
4254 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4255 {
4256         struct kvm_cpuid_entry2 *best;
4257         struct vcpu_vmx *vmx = to_vmx(vcpu);
4258         u32 exec_control;
4259
4260         vmx->rdtscp_enabled = false;
4261         if (vmx_rdtscp_supported()) {
4262                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4263                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4264                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4265                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4266                                 vmx->rdtscp_enabled = true;
4267                         else {
4268                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4269                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4270                                                 exec_control);
4271                         }
4272                 }
4273         }
4274 }
4275
4276 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4277 {
4278 }
4279
4280 static struct kvm_x86_ops vmx_x86_ops = {
4281         .cpu_has_kvm_support = cpu_has_kvm_support,
4282         .disabled_by_bios = vmx_disabled_by_bios,
4283         .hardware_setup = hardware_setup,
4284         .hardware_unsetup = hardware_unsetup,
4285         .check_processor_compatibility = vmx_check_processor_compat,
4286         .hardware_enable = hardware_enable,
4287         .hardware_disable = hardware_disable,
4288         .cpu_has_accelerated_tpr = report_flexpriority,
4289
4290         .vcpu_create = vmx_create_vcpu,
4291         .vcpu_free = vmx_free_vcpu,
4292         .vcpu_reset = vmx_vcpu_reset,
4293
4294         .prepare_guest_switch = vmx_save_host_state,
4295         .vcpu_load = vmx_vcpu_load,
4296         .vcpu_put = vmx_vcpu_put,
4297
4298         .set_guest_debug = set_guest_debug,
4299         .get_msr = vmx_get_msr,
4300         .set_msr = vmx_set_msr,
4301         .get_segment_base = vmx_get_segment_base,
4302         .get_segment = vmx_get_segment,
4303         .set_segment = vmx_set_segment,
4304         .get_cpl = vmx_get_cpl,
4305         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4306         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4307         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4308         .set_cr0 = vmx_set_cr0,
4309         .set_cr3 = vmx_set_cr3,
4310         .set_cr4 = vmx_set_cr4,
4311         .set_efer = vmx_set_efer,
4312         .get_idt = vmx_get_idt,
4313         .set_idt = vmx_set_idt,
4314         .get_gdt = vmx_get_gdt,
4315         .set_gdt = vmx_set_gdt,
4316         .set_dr7 = vmx_set_dr7,
4317         .cache_reg = vmx_cache_reg,
4318         .get_rflags = vmx_get_rflags,
4319         .set_rflags = vmx_set_rflags,
4320         .fpu_activate = vmx_fpu_activate,
4321         .fpu_deactivate = vmx_fpu_deactivate,
4322
4323         .tlb_flush = vmx_flush_tlb,
4324
4325         .run = vmx_vcpu_run,
4326         .handle_exit = vmx_handle_exit,
4327         .skip_emulated_instruction = skip_emulated_instruction,
4328         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4329         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4330         .patch_hypercall = vmx_patch_hypercall,
4331         .set_irq = vmx_inject_irq,
4332         .set_nmi = vmx_inject_nmi,
4333         .queue_exception = vmx_queue_exception,
4334         .interrupt_allowed = vmx_interrupt_allowed,
4335         .nmi_allowed = vmx_nmi_allowed,
4336         .get_nmi_mask = vmx_get_nmi_mask,
4337         .set_nmi_mask = vmx_set_nmi_mask,
4338         .enable_nmi_window = enable_nmi_window,
4339         .enable_irq_window = enable_irq_window,
4340         .update_cr8_intercept = update_cr8_intercept,
4341
4342         .set_tss_addr = vmx_set_tss_addr,
4343         .get_tdp_level = get_ept_level,
4344         .get_mt_mask = vmx_get_mt_mask,
4345
4346         .exit_reasons_str = vmx_exit_reasons_str,
4347         .get_lpage_level = vmx_get_lpage_level,
4348
4349         .cpuid_update = vmx_cpuid_update,
4350
4351         .rdtscp_supported = vmx_rdtscp_supported,
4352
4353         .set_supported_cpuid = vmx_set_supported_cpuid,
4354
4355         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4356 };
4357
4358 static int __init vmx_init(void)
4359 {
4360         int r, i;
4361
4362         rdmsrl_safe(MSR_EFER, &host_efer);
4363
4364         for (i = 0; i < NR_VMX_MSR; ++i)
4365                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4366
4367         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4368         if (!vmx_io_bitmap_a)
4369                 return -ENOMEM;
4370
4371         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4372         if (!vmx_io_bitmap_b) {
4373                 r = -ENOMEM;
4374                 goto out;
4375         }
4376
4377         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4378         if (!vmx_msr_bitmap_legacy) {
4379                 r = -ENOMEM;
4380                 goto out1;
4381         }
4382
4383         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4384         if (!vmx_msr_bitmap_longmode) {
4385                 r = -ENOMEM;
4386                 goto out2;
4387         }
4388
4389         /*
4390          * Allow direct access to the PC debug port (it is often used for I/O
4391          * delays, but the vmexits simply slow things down).
4392          */
4393         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4394         clear_bit(0x80, vmx_io_bitmap_a);
4395
4396         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4397
4398         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4399         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4400
4401         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4402
4403         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4404                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4405         if (r)
4406                 goto out3;
4407
4408         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4409         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4410         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4411         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4412         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4413         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4414
4415         if (enable_ept) {
4416                 bypass_guest_pf = 0;
4417                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4418                         VMX_EPT_WRITABLE_MASK);
4419                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4420                                 VMX_EPT_EXECUTABLE_MASK);
4421                 kvm_enable_tdp();
4422         } else
4423                 kvm_disable_tdp();
4424
4425         if (bypass_guest_pf)
4426                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4427
4428         return 0;
4429
4430 out3:
4431         free_page((unsigned long)vmx_msr_bitmap_longmode);
4432 out2:
4433         free_page((unsigned long)vmx_msr_bitmap_legacy);
4434 out1:
4435         free_page((unsigned long)vmx_io_bitmap_b);
4436 out:
4437         free_page((unsigned long)vmx_io_bitmap_a);
4438         return r;
4439 }
4440
4441 static void __exit vmx_exit(void)
4442 {
4443         free_page((unsigned long)vmx_msr_bitmap_legacy);
4444         free_page((unsigned long)vmx_msr_bitmap_longmode);
4445         free_page((unsigned long)vmx_io_bitmap_b);
4446         free_page((unsigned long)vmx_io_bitmap_a);
4447
4448         kvm_exit();
4449 }
4450
4451 module_init(vmx_init)
4452 module_exit(vmx_exit)