arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP    128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 130 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 131 module_param(ple_gap, int, S_IRUGO);
 132
 133 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 134 module_param(ple_window, int, S_IRUGO);
 135
 136 extern const ulong vmx_return;
 137
 138 #define NR_AUTOLOAD_MSRS 8
 139 #define VMCS02_POOL_SIZE 1
 140
 141 struct vmcs {
 142         u32 revision_id;
 143         u32 abort;
 144         char data[0];
 145 };
 146
 147 /*
 148  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 149  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 150  * loaded on this CPU (so we can clear them if the CPU goes down).
 151  */
 152 struct loaded_vmcs {
 153         struct vmcs *vmcs;
 154         int cpu;
 155         int launched;
 156         struct list_head loaded_vmcss_on_cpu_link;
 157 };
 158
 159 struct shared_msr_entry {
 160         unsigned index;
 161         u64 data;
 162         u64 mask;
 163 };
 164
 165 /*
 166  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 167  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 168  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 169  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 170  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 171  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 172  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 173  * underlying hardware which will be used to run L2.
 174  * This structure is packed to ensure that its layout is identical across
 175  * machines (necessary for live migration).
 176  * If there are changes in this struct, VMCS12_REVISION must be changed.
 177  */
 178 typedef u64 natural_width;
 179 struct __packed vmcs12 {
 180         /* According to the Intel spec, a VMCS region must start with the
 181          * following two fields. Then follow implementation-specific data.
 182          */
 183         u32 revision_id;
 184         u32 abort;
 185
 186         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 187         u32 padding[7]; /* room for future expansion */
 188
 189         u64 io_bitmap_a;
 190         u64 io_bitmap_b;
 191         u64 msr_bitmap;
 192         u64 vm_exit_msr_store_addr;
 193         u64 vm_exit_msr_load_addr;
 194         u64 vm_entry_msr_load_addr;
 195         u64 tsc_offset;
 196         u64 virtual_apic_page_addr;
 197         u64 apic_access_addr;
 198         u64 ept_pointer;
 199         u64 guest_physical_address;
 200         u64 vmcs_link_pointer;
 201         u64 guest_ia32_debugctl;
 202         u64 guest_ia32_pat;
 203         u64 guest_ia32_efer;
 204         u64 guest_ia32_perf_global_ctrl;
 205         u64 guest_pdptr0;
 206         u64 guest_pdptr1;
 207         u64 guest_pdptr2;
 208         u64 guest_pdptr3;
 209         u64 guest_bndcfgs;
 210         u64 host_ia32_pat;
 211         u64 host_ia32_efer;
 212         u64 host_ia32_perf_global_ctrl;
 213         u64 padding64[8]; /* room for future expansion */
 214         /*
 215          * To allow migration of L1 (complete with its L2 guests) between
 216          * machines of different natural widths (32 or 64 bit), we cannot have
 217          * unsigned long fields with no explict size. We use u64 (aliased
 218          * natural_width) instead. Luckily, x86 is little-endian.
 219          */
 220         natural_width cr0_guest_host_mask;
 221         natural_width cr4_guest_host_mask;
 222         natural_width cr0_read_shadow;
 223         natural_width cr4_read_shadow;
 224         natural_width cr3_target_value0;
 225         natural_width cr3_target_value1;
 226         natural_width cr3_target_value2;
 227         natural_width cr3_target_value3;
 228         natural_width exit_qualification;
 229         natural_width guest_linear_address;
 230         natural_width guest_cr0;
 231         natural_width guest_cr3;
 232         natural_width guest_cr4;
 233         natural_width guest_es_base;
 234         natural_width guest_cs_base;
 235         natural_width guest_ss_base;
 236         natural_width guest_ds_base;
 237         natural_width guest_fs_base;
 238         natural_width guest_gs_base;
 239         natural_width guest_ldtr_base;
 240         natural_width guest_tr_base;
 241         natural_width guest_gdtr_base;
 242         natural_width guest_idtr_base;
 243         natural_width guest_dr7;
 244         natural_width guest_rsp;
 245         natural_width guest_rip;
 246         natural_width guest_rflags;
 247         natural_width guest_pending_dbg_exceptions;
 248         natural_width guest_sysenter_esp;
 249         natural_width guest_sysenter_eip;
 250         natural_width host_cr0;
 251         natural_width host_cr3;
 252         natural_width host_cr4;
 253         natural_width host_fs_base;
 254         natural_width host_gs_base;
 255         natural_width host_tr_base;
 256         natural_width host_gdtr_base;
 257         natural_width host_idtr_base;
 258         natural_width host_ia32_sysenter_esp;
 259         natural_width host_ia32_sysenter_eip;
 260         natural_width host_rsp;
 261         natural_width host_rip;
 262         natural_width paddingl[8]; /* room for future expansion */
 263         u32 pin_based_vm_exec_control;
 264         u32 cpu_based_vm_exec_control;
 265         u32 exception_bitmap;
 266         u32 page_fault_error_code_mask;
 267         u32 page_fault_error_code_match;
 268         u32 cr3_target_count;
 269         u32 vm_exit_controls;
 270         u32 vm_exit_msr_store_count;
 271         u32 vm_exit_msr_load_count;
 272         u32 vm_entry_controls;
 273         u32 vm_entry_msr_load_count;
 274         u32 vm_entry_intr_info_field;
 275         u32 vm_entry_exception_error_code;
 276         u32 vm_entry_instruction_len;
 277         u32 tpr_threshold;
 278         u32 secondary_vm_exec_control;
 279         u32 vm_instruction_error;
 280         u32 vm_exit_reason;
 281         u32 vm_exit_intr_info;
 282         u32 vm_exit_intr_error_code;
 283         u32 idt_vectoring_info_field;
 284         u32 idt_vectoring_error_code;
 285         u32 vm_exit_instruction_len;
 286         u32 vmx_instruction_info;
 287         u32 guest_es_limit;
 288         u32 guest_cs_limit;
 289         u32 guest_ss_limit;
 290         u32 guest_ds_limit;
 291         u32 guest_fs_limit;
 292         u32 guest_gs_limit;
 293         u32 guest_ldtr_limit;
 294         u32 guest_tr_limit;
 295         u32 guest_gdtr_limit;
 296         u32 guest_idtr_limit;
 297         u32 guest_es_ar_bytes;
 298         u32 guest_cs_ar_bytes;
 299         u32 guest_ss_ar_bytes;
 300         u32 guest_ds_ar_bytes;
 301         u32 guest_fs_ar_bytes;
 302         u32 guest_gs_ar_bytes;
 303         u32 guest_ldtr_ar_bytes;
 304         u32 guest_tr_ar_bytes;
 305         u32 guest_interruptibility_info;
 306         u32 guest_activity_state;
 307         u32 guest_sysenter_cs;
 308         u32 host_ia32_sysenter_cs;
 309         u32 vmx_preemption_timer_value;
 310         u32 padding32[7]; /* room for future expansion */
 311         u16 virtual_processor_id;
 312         u16 guest_es_selector;
 313         u16 guest_cs_selector;
 314         u16 guest_ss_selector;
 315         u16 guest_ds_selector;
 316         u16 guest_fs_selector;
 317         u16 guest_gs_selector;
 318         u16 guest_ldtr_selector;
 319         u16 guest_tr_selector;
 320         u16 host_es_selector;
 321         u16 host_cs_selector;
 322         u16 host_ss_selector;
 323         u16 host_ds_selector;
 324         u16 host_fs_selector;
 325         u16 host_gs_selector;
 326         u16 host_tr_selector;
 327 };
 328
 329 /*
 330  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 331  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 332  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 333  */
 334 #define VMCS12_REVISION 0x11e57ed0
 335
 336 /*
 337  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 338  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 339  * current implementation, 4K are reserved to avoid future complications.
 340  */
 341 #define VMCS12_SIZE 0x1000
 342
 343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 344 struct vmcs02_list {
 345         struct list_head list;
 346         gpa_t vmptr;
 347         struct loaded_vmcs vmcs02;
 348 };
 349
 350 /*
 351  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 352  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 353  */
 354 struct nested_vmx {
 355         /* Has the level1 guest done vmxon? */
 356         bool vmxon;
 357
 358         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 359         gpa_t current_vmptr;
 360         /* The host-usable pointer to the above */
 361         struct page *current_vmcs12_page;
 362         struct vmcs12 *current_vmcs12;
 363         struct vmcs *current_shadow_vmcs;
 364         /*
 365          * Indicates if the shadow vmcs must be updated with the
 366          * data hold by vmcs12
 367          */
 368         bool sync_shadow_vmcs;
 369
 370         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 371         struct list_head vmcs02_pool;
 372         int vmcs02_num;
 373         u64 vmcs01_tsc_offset;
 374         /* L2 must run next, and mustn't decide to exit to L1. */
 375         bool nested_run_pending;
 376         /*
 377          * Guest pages referred to in vmcs02 with host-physical pointers, so
 378          * we must keep them pinned while L2 runs.
 379          */
 380         struct page *apic_access_page;
 381         u64 msr_ia32_feature_control;
 382
 383         struct hrtimer preemption_timer;
 384         bool preemption_timer_expired;
 385 };
 386
 387 #define POSTED_INTR_ON  0
 388 /* Posted-Interrupt Descriptor */
 389 struct pi_desc {
 390         u32 pir[8];     /* Posted interrupt requested */
 391         u32 control;    /* bit 0 of control is outstanding notification bit */
 392         u32 rsvd[7];
 393 } __aligned(64);
 394
 395 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 396 {
 397         return test_and_set_bit(POSTED_INTR_ON,
 398                         (unsigned long *)&pi_desc->control);
 399 }
 400
 401 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 402 {
 403         return test_and_clear_bit(POSTED_INTR_ON,
 404                         (unsigned long *)&pi_desc->control);
 405 }
 406
 407 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 408 {
 409         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 410 }
 411
 412 struct vcpu_vmx {
 413         struct kvm_vcpu       vcpu;
 414         unsigned long         host_rsp;
 415         u8                    fail;
 416         u8                    cpl;
 417         bool                  nmi_known_unmasked;
 418         u32                   exit_intr_info;
 419         u32                   idt_vectoring_info;
 420         ulong                 rflags;
 421         struct shared_msr_entry *guest_msrs;
 422         int                   nmsrs;
 423         int                   save_nmsrs;
 424         unsigned long         host_idt_base;
 425 #ifdef CONFIG_X86_64
 426         u64                   msr_host_kernel_gs_base;
 427         u64                   msr_guest_kernel_gs_base;
 428 #endif
 429         u32 vm_entry_controls_shadow;
 430         u32 vm_exit_controls_shadow;
 431         /*
 432          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 433          * non-nested (L1) guest, it always points to vmcs01. For a nested
 434          * guest (L2), it points to a different VMCS.
 435          */
 436         struct loaded_vmcs    vmcs01;
 437         struct loaded_vmcs   *loaded_vmcs;
 438         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 439         struct msr_autoload {
 440                 unsigned nr;
 441                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 442                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 443         } msr_autoload;
 444         struct {
 445                 int           loaded;
 446                 u16           fs_sel, gs_sel, ldt_sel;
 447 #ifdef CONFIG_X86_64
 448                 u16           ds_sel, es_sel;
 449 #endif
 450                 int           gs_ldt_reload_needed;
 451                 int           fs_reload_needed;
 452                 u64           msr_host_bndcfgs;
 453         } host_state;
 454         struct {
 455                 int vm86_active;
 456                 ulong save_rflags;
 457                 struct kvm_segment segs[8];
 458         } rmode;
 459         struct {
 460                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 461                 struct kvm_save_segment {
 462                         u16 selector;
 463                         unsigned long base;
 464                         u32 limit;
 465                         u32 ar;
 466                 } seg[8];
 467         } segment_cache;
 468         int vpid;
 469         bool emulation_required;
 470
 471         /* Support for vnmi-less CPUs */
 472         int soft_vnmi_blocked;
 473         ktime_t entry_time;
 474         s64 vnmi_blocked_time;
 475         u32 exit_reason;
 476
 477         bool rdtscp_enabled;
 478
 479         /* Posted interrupt descriptor */
 480         struct pi_desc pi_desc;
 481
 482         /* Support for a guest hypervisor (nested VMX) */
 483         struct nested_vmx nested;
 484 };
 485
 486 enum segment_cache_field {
 487         SEG_FIELD_SEL = 0,
 488         SEG_FIELD_BASE = 1,
 489         SEG_FIELD_LIMIT = 2,
 490         SEG_FIELD_AR = 3,
 491
 492         SEG_FIELD_NR = 4
 493 };
 494
 495 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 496 {
 497         return container_of(vcpu, struct vcpu_vmx, vcpu);
 498 }
 499
 500 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 501 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 502 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 503                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 504
 505
 506 static const unsigned long shadow_read_only_fields[] = {
 507         /*
 508          * We do NOT shadow fields that are modified when L0
 509          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 510          * VMXON...) executed by L1.
 511          * For example, VM_INSTRUCTION_ERROR is read
 512          * by L1 if a vmx instruction fails (part of the error path).
 513          * Note the code assumes this logic. If for some reason
 514          * we start shadowing these fields then we need to
 515          * force a shadow sync when L0 emulates vmx instructions
 516          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 517          * by nested_vmx_failValid)
 518          */
 519         VM_EXIT_REASON,
 520         VM_EXIT_INTR_INFO,
 521         VM_EXIT_INSTRUCTION_LEN,
 522         IDT_VECTORING_INFO_FIELD,
 523         IDT_VECTORING_ERROR_CODE,
 524         VM_EXIT_INTR_ERROR_CODE,
 525         EXIT_QUALIFICATION,
 526         GUEST_LINEAR_ADDRESS,
 527         GUEST_PHYSICAL_ADDRESS
 528 };
 529 static const int max_shadow_read_only_fields =
 530         ARRAY_SIZE(shadow_read_only_fields);
 531
 532 static const unsigned long shadow_read_write_fields[] = {
 533         GUEST_RIP,
 534         GUEST_RSP,
 535         GUEST_CR0,
 536         GUEST_CR3,
 537         GUEST_CR4,
 538         GUEST_INTERRUPTIBILITY_INFO,
 539         GUEST_RFLAGS,
 540         GUEST_CS_SELECTOR,
 541         GUEST_CS_AR_BYTES,
 542         GUEST_CS_LIMIT,
 543         GUEST_CS_BASE,
 544         GUEST_ES_BASE,
 545         GUEST_BNDCFGS,
 546         CR0_GUEST_HOST_MASK,
 547         CR0_READ_SHADOW,
 548         CR4_READ_SHADOW,
 549         TSC_OFFSET,
 550         EXCEPTION_BITMAP,
 551         CPU_BASED_VM_EXEC_CONTROL,
 552         VM_ENTRY_EXCEPTION_ERROR_CODE,
 553         VM_ENTRY_INTR_INFO_FIELD,
 554         VM_ENTRY_INSTRUCTION_LEN,
 555         VM_ENTRY_EXCEPTION_ERROR_CODE,
 556         HOST_FS_BASE,
 557         HOST_GS_BASE,
 558         HOST_FS_SELECTOR,
 559         HOST_GS_SELECTOR
 560 };
 561 static const int max_shadow_read_write_fields =
 562         ARRAY_SIZE(shadow_read_write_fields);
 563
 564 static const unsigned short vmcs_field_to_offset_table[] = {
 565         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 566         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 567         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 568         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 569         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 570         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 571         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 572         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 573         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 574         FIELD(HOST_ES_SELECTOR, host_es_selector),
 575         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 576         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 577         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 578         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 579         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 580         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 581         FIELD64(IO_BITMAP_A, io_bitmap_a),
 582         FIELD64(IO_BITMAP_B, io_bitmap_b),
 583         FIELD64(MSR_BITMAP, msr_bitmap),
 584         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 585         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 586         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 587         FIELD64(TSC_OFFSET, tsc_offset),
 588         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 589         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 590         FIELD64(EPT_POINTER, ept_pointer),
 591         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 592         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 593         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 594         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 595         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 596         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 597         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 598         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 599         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 600         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 601         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 602         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 603         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 604         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 605         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 606         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 607         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 608         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 609         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 610         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 611         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 612         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 613         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 614         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 615         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 616         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 617         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 618         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 619         FIELD(TPR_THRESHOLD, tpr_threshold),
 620         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 621         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 622         FIELD(VM_EXIT_REASON, vm_exit_reason),
 623         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 624         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 625         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 626         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 627         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 628         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 629         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 630         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 631         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 632         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 633         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 634         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 635         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 636         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 637         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 638         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 639         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 640         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 641         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 642         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 643         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 644         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 645         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 646         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 647         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 648         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 649         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 650         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 651         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 652         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 653         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 654         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 655         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 656         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 657         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 658         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 659         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 660         FIELD(EXIT_QUALIFICATION, exit_qualification),
 661         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 662         FIELD(GUEST_CR0, guest_cr0),
 663         FIELD(GUEST_CR3, guest_cr3),
 664         FIELD(GUEST_CR4, guest_cr4),
 665         FIELD(GUEST_ES_BASE, guest_es_base),
 666         FIELD(GUEST_CS_BASE, guest_cs_base),
 667         FIELD(GUEST_SS_BASE, guest_ss_base),
 668         FIELD(GUEST_DS_BASE, guest_ds_base),
 669         FIELD(GUEST_FS_BASE, guest_fs_base),
 670         FIELD(GUEST_GS_BASE, guest_gs_base),
 671         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 672         FIELD(GUEST_TR_BASE, guest_tr_base),
 673         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 674         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 675         FIELD(GUEST_DR7, guest_dr7),
 676         FIELD(GUEST_RSP, guest_rsp),
 677         FIELD(GUEST_RIP, guest_rip),
 678         FIELD(GUEST_RFLAGS, guest_rflags),
 679         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 680         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 681         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 682         FIELD(HOST_CR0, host_cr0),
 683         FIELD(HOST_CR3, host_cr3),
 684         FIELD(HOST_CR4, host_cr4),
 685         FIELD(HOST_FS_BASE, host_fs_base),
 686         FIELD(HOST_GS_BASE, host_gs_base),
 687         FIELD(HOST_TR_BASE, host_tr_base),
 688         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 689         FIELD(HOST_IDTR_BASE, host_idtr_base),
 690         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 691         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 692         FIELD(HOST_RSP, host_rsp),
 693         FIELD(HOST_RIP, host_rip),
 694 };
 695 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 696
 697 static inline short vmcs_field_to_offset(unsigned long field)
 698 {
 699         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 700                 return -1;
 701         return vmcs_field_to_offset_table[field];
 702 }
 703
 704 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 705 {
 706         return to_vmx(vcpu)->nested.current_vmcs12;
 707 }
 708
 709 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 710 {
 711         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 712         if (is_error_page(page))
 713                 return NULL;
 714
 715         return page;
 716 }
 717
 718 static void nested_release_page(struct page *page)
 719 {
 720         kvm_release_page_dirty(page);
 721 }
 722
 723 static void nested_release_page_clean(struct page *page)
 724 {
 725         kvm_release_page_clean(page);
 726 }
 727
 728 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 729 static u64 construct_eptp(unsigned long root_hpa);
 730 static void kvm_cpu_vmxon(u64 addr);
 731 static void kvm_cpu_vmxoff(void);
 732 static bool vmx_mpx_supported(void);
 733 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 734 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 735                             struct kvm_segment *var, int seg);
 736 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 737                             struct kvm_segment *var, int seg);
 738 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 739 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 740 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 741 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 742 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 743 static bool vmx_mpx_supported(void);
 744
 745 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 746 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 747 /*
 748  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 749  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 750  */
 751 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 752 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 753
 754 static unsigned long *vmx_io_bitmap_a;
 755 static unsigned long *vmx_io_bitmap_b;
 756 static unsigned long *vmx_msr_bitmap_legacy;
 757 static unsigned long *vmx_msr_bitmap_longmode;
 758 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 759 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 760 static unsigned long *vmx_vmread_bitmap;
 761 static unsigned long *vmx_vmwrite_bitmap;
 762
 763 static bool cpu_has_load_ia32_efer;
 764 static bool cpu_has_load_perf_global_ctrl;
 765
 766 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 767 static DEFINE_SPINLOCK(vmx_vpid_lock);
 768
 769 static struct vmcs_config {
 770         int size;
 771         int order;
 772         u32 revision_id;
 773         u32 pin_based_exec_ctrl;
 774         u32 cpu_based_exec_ctrl;
 775         u32 cpu_based_2nd_exec_ctrl;
 776         u32 vmexit_ctrl;
 777         u32 vmentry_ctrl;
 778 } vmcs_config;
 779
 780 static struct vmx_capability {
 781         u32 ept;
 782         u32 vpid;
 783 } vmx_capability;
 784
 785 #define VMX_SEGMENT_FIELD(seg)                                  \
 786         [VCPU_SREG_##seg] = {                                   \
 787                 .selector = GUEST_##seg##_SELECTOR,             \
 788                 .base = GUEST_##seg##_BASE,                     \
 789                 .limit = GUEST_##seg##_LIMIT,                   \
 790                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 791         }
 792
 793 static const struct kvm_vmx_segment_field {
 794         unsigned selector;
 795         unsigned base;
 796         unsigned limit;
 797         unsigned ar_bytes;
 798 } kvm_vmx_segment_fields[] = {
 799         VMX_SEGMENT_FIELD(CS),
 800         VMX_SEGMENT_FIELD(DS),
 801         VMX_SEGMENT_FIELD(ES),
 802         VMX_SEGMENT_FIELD(FS),
 803         VMX_SEGMENT_FIELD(GS),
 804         VMX_SEGMENT_FIELD(SS),
 805         VMX_SEGMENT_FIELD(TR),
 806         VMX_SEGMENT_FIELD(LDTR),
 807 };
 808
 809 static u64 host_efer;
 810
 811 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 812
 813 /*
 814  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 815  * away by decrementing the array size.
 816  */
 817 static const u32 vmx_msr_index[] = {
 818 #ifdef CONFIG_X86_64
 819         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 820 #endif
 821         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 822 };
 823 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 824
 825 static inline bool is_page_fault(u32 intr_info)
 826 {
 827         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 828                              INTR_INFO_VALID_MASK)) ==
 829                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 830 }
 831
 832 static inline bool is_no_device(u32 intr_info)
 833 {
 834         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 835                              INTR_INFO_VALID_MASK)) ==
 836                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 837 }
 838
 839 static inline bool is_invalid_opcode(u32 intr_info)
 840 {
 841         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 842                              INTR_INFO_VALID_MASK)) ==
 843                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 844 }
 845
 846 static inline bool is_external_interrupt(u32 intr_info)
 847 {
 848         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 849                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 850 }
 851
 852 static inline bool is_machine_check(u32 intr_info)
 853 {
 854         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 855                              INTR_INFO_VALID_MASK)) ==
 856                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 857 }
 858
 859 static inline bool cpu_has_vmx_msr_bitmap(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 862 }
 863
 864 static inline bool cpu_has_vmx_tpr_shadow(void)
 865 {
 866         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 867 }
 868
 869 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 870 {
 871         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 872 }
 873
 874 static inline bool cpu_has_secondary_exec_ctrls(void)
 875 {
 876         return vmcs_config.cpu_based_exec_ctrl &
 877                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 878 }
 879
 880 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 881 {
 882         return vmcs_config.cpu_based_2nd_exec_ctrl &
 883                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 884 }
 885
 886 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 887 {
 888         return vmcs_config.cpu_based_2nd_exec_ctrl &
 889                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 890 }
 891
 892 static inline bool cpu_has_vmx_apic_register_virt(void)
 893 {
 894         return vmcs_config.cpu_based_2nd_exec_ctrl &
 895                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 896 }
 897
 898 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 899 {
 900         return vmcs_config.cpu_based_2nd_exec_ctrl &
 901                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 902 }
 903
 904 static inline bool cpu_has_vmx_posted_intr(void)
 905 {
 906         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 907 }
 908
 909 static inline bool cpu_has_vmx_apicv(void)
 910 {
 911         return cpu_has_vmx_apic_register_virt() &&
 912                 cpu_has_vmx_virtual_intr_delivery() &&
 913                 cpu_has_vmx_posted_intr();
 914 }
 915
 916 static inline bool cpu_has_vmx_flexpriority(void)
 917 {
 918         return cpu_has_vmx_tpr_shadow() &&
 919                 cpu_has_vmx_virtualize_apic_accesses();
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_execute_only(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 928 {
 929         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_eptp_writeback(void)
 933 {
 934         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_2m_page(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_ept_1g_page(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_ept_4levels(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_ept_ad_bits(void)
 953 {
 954         return vmx_capability.ept & VMX_EPT_AD_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invept_context(void)
 958 {
 959         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_invept_global(void)
 963 {
 964         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 965 }
 966
 967 static inline bool cpu_has_vmx_invvpid_single(void)
 968 {
 969         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 970 }
 971
 972 static inline bool cpu_has_vmx_invvpid_global(void)
 973 {
 974         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 975 }
 976
 977 static inline bool cpu_has_vmx_ept(void)
 978 {
 979         return vmcs_config.cpu_based_2nd_exec_ctrl &
 980                 SECONDARY_EXEC_ENABLE_EPT;
 981 }
 982
 983 static inline bool cpu_has_vmx_unrestricted_guest(void)
 984 {
 985         return vmcs_config.cpu_based_2nd_exec_ctrl &
 986                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 987 }
 988
 989 static inline bool cpu_has_vmx_ple(void)
 990 {
 991         return vmcs_config.cpu_based_2nd_exec_ctrl &
 992                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 993 }
 994
 995 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 996 {
 997         return flexpriority_enabled && irqchip_in_kernel(kvm);
 998 }
 999
1000 static inline bool cpu_has_vmx_vpid(void)
1001 {
1002         return vmcs_config.cpu_based_2nd_exec_ctrl &
1003                 SECONDARY_EXEC_ENABLE_VPID;
1004 }
1005
1006 static inline bool cpu_has_vmx_rdtscp(void)
1007 {
1008         return vmcs_config.cpu_based_2nd_exec_ctrl &
1009                 SECONDARY_EXEC_RDTSCP;
1010 }
1011
1012 static inline bool cpu_has_vmx_invpcid(void)
1013 {
1014         return vmcs_config.cpu_based_2nd_exec_ctrl &
1015                 SECONDARY_EXEC_ENABLE_INVPCID;
1016 }
1017
1018 static inline bool cpu_has_virtual_nmis(void)
1019 {
1020         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021 }
1022
1023 static inline bool cpu_has_vmx_wbinvd_exit(void)
1024 {
1025         return vmcs_config.cpu_based_2nd_exec_ctrl &
1026                 SECONDARY_EXEC_WBINVD_EXITING;
1027 }
1028
1029 static inline bool cpu_has_vmx_shadow_vmcs(void)
1030 {
1031         u64 vmx_msr;
1032         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033         /* check if the cpu supports writing r/o exit information fields */
1034         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035                 return false;
1036
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_SHADOW_VMCS;
1039 }
1040
1041 static inline bool report_flexpriority(void)
1042 {
1043         return flexpriority_enabled;
1044 }
1045
1046 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047 {
1048         return vmcs12->cpu_based_vm_exec_control & bit;
1049 }
1050
1051 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052 {
1053         return (vmcs12->cpu_based_vm_exec_control &
1054                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055                 (vmcs12->secondary_vm_exec_control & bit);
1056 }
1057
1058 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1059 {
1060         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061 }
1062
1063 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064 {
1065         return vmcs12->pin_based_vm_exec_control &
1066                 PIN_BASED_VMX_PREEMPTION_TIMER;
1067 }
1068
1069 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070 {
1071         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072 }
1073
1074 static inline bool is_exception(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081                               u32 exit_intr_info,
1082                               unsigned long exit_qualification);
1083 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084                         struct vmcs12 *vmcs12,
1085                         u32 reason, unsigned long qualification);
1086
1087 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1088 {
1089         int i;
1090
1091         for (i = 0; i < vmx->nmsrs; ++i)
1092                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1093                         return i;
1094         return -1;
1095 }
1096
1097 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098 {
1099     struct {
1100         u64 vpid : 16;
1101         u64 rsvd : 48;
1102         u64 gva;
1103     } operand = { vpid, 0, gva };
1104
1105     asm volatile (__ex(ASM_VMX_INVVPID)
1106                   /* CF==1 or ZF==1 --> rc = -1 */
1107                   "; ja 1f ; ud2 ; 1:"
1108                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1109 }
1110
1111 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112 {
1113         struct {
1114                 u64 eptp, gpa;
1115         } operand = {eptp, gpa};
1116
1117         asm volatile (__ex(ASM_VMX_INVEPT)
1118                         /* CF==1 or ZF==1 --> rc = -1 */
1119                         "; ja 1f ; ud2 ; 1:\n"
1120                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1121 }
1122
1123 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1124 {
1125         int i;
1126
1127         i = __find_msr_index(vmx, msr);
1128         if (i >= 0)
1129                 return &vmx->guest_msrs[i];
1130         return NULL;
1131 }
1132
1133 static void vmcs_clear(struct vmcs *vmcs)
1134 {
1135         u64 phys_addr = __pa(vmcs);
1136         u8 error;
1137
1138         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1139                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1140                       : "cc", "memory");
1141         if (error)
1142                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143                        vmcs, phys_addr);
1144 }
1145
1146 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147 {
1148         vmcs_clear(loaded_vmcs->vmcs);
1149         loaded_vmcs->cpu = -1;
1150         loaded_vmcs->launched = 0;
1151 }
1152
1153 static void vmcs_load(struct vmcs *vmcs)
1154 {
1155         u64 phys_addr = __pa(vmcs);
1156         u8 error;
1157
1158         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1159                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1160                         : "cc", "memory");
1161         if (error)
1162                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1163                        vmcs, phys_addr);
1164 }
1165
1166 #ifdef CONFIG_KEXEC
1167 /*
1168  * This bitmap is used to indicate whether the vmclear
1169  * operation is enabled on all cpus. All disabled by
1170  * default.
1171  */
1172 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174 static inline void crash_enable_local_vmclear(int cpu)
1175 {
1176         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177 }
1178
1179 static inline void crash_disable_local_vmclear(int cpu)
1180 {
1181         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182 }
1183
1184 static inline int crash_local_vmclear_enabled(int cpu)
1185 {
1186         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187 }
1188
1189 static void crash_vmclear_local_loaded_vmcss(void)
1190 {
1191         int cpu = raw_smp_processor_id();
1192         struct loaded_vmcs *v;
1193
1194         if (!crash_local_vmclear_enabled(cpu))
1195                 return;
1196
1197         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198                             loaded_vmcss_on_cpu_link)
1199                 vmcs_clear(v->vmcs);
1200 }
1201 #else
1202 static inline void crash_enable_local_vmclear(int cpu) { }
1203 static inline void crash_disable_local_vmclear(int cpu) { }
1204 #endif /* CONFIG_KEXEC */
1205
1206 static void __loaded_vmcs_clear(void *arg)
1207 {
1208         struct loaded_vmcs *loaded_vmcs = arg;
1209         int cpu = raw_smp_processor_id();
1210
1211         if (loaded_vmcs->cpu != cpu)
1212                 return; /* vcpu migration can race with cpu offline */
1213         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1214                 per_cpu(current_vmcs, cpu) = NULL;
1215         crash_disable_local_vmclear(cpu);
1216         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1217
1218         /*
1219          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220          * is before setting loaded_vmcs->vcpu to -1 which is done in
1221          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222          * then adds the vmcs into percpu list before it is deleted.
1223          */
1224         smp_wmb();
1225
1226         loaded_vmcs_init(loaded_vmcs);
1227         crash_enable_local_vmclear(cpu);
1228 }
1229
1230 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1231 {
1232         int cpu = loaded_vmcs->cpu;
1233
1234         if (cpu != -1)
1235                 smp_call_function_single(cpu,
1236                          __loaded_vmcs_clear, loaded_vmcs, 1);
1237 }
1238
1239 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1240 {
1241         if (vmx->vpid == 0)
1242                 return;
1243
1244         if (cpu_has_vmx_invvpid_single())
1245                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1246 }
1247
1248 static inline void vpid_sync_vcpu_global(void)
1249 {
1250         if (cpu_has_vmx_invvpid_global())
1251                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252 }
1253
1254 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255 {
1256         if (cpu_has_vmx_invvpid_single())
1257                 vpid_sync_vcpu_single(vmx);
1258         else
1259                 vpid_sync_vcpu_global();
1260 }
1261
1262 static inline void ept_sync_global(void)
1263 {
1264         if (cpu_has_vmx_invept_global())
1265                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266 }
1267
1268 static inline void ept_sync_context(u64 eptp)
1269 {
1270         if (enable_ept) {
1271                 if (cpu_has_vmx_invept_context())
1272                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273                 else
1274                         ept_sync_global();
1275         }
1276 }
1277
1278 static __always_inline unsigned long vmcs_readl(unsigned long field)
1279 {
1280         unsigned long value;
1281
1282         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283                       : "=a"(value) : "d"(field) : "cc");
1284         return value;
1285 }
1286
1287 static __always_inline u16 vmcs_read16(unsigned long field)
1288 {
1289         return vmcs_readl(field);
1290 }
1291
1292 static __always_inline u32 vmcs_read32(unsigned long field)
1293 {
1294         return vmcs_readl(field);
1295 }
1296
1297 static __always_inline u64 vmcs_read64(unsigned long field)
1298 {
1299 #ifdef CONFIG_X86_64
1300         return vmcs_readl(field);
1301 #else
1302         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303 #endif
1304 }
1305
1306 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307 {
1308         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310         dump_stack();
1311 }
1312
1313 static void vmcs_writel(unsigned long field, unsigned long value)
1314 {
1315         u8 error;
1316
1317         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1318                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1319         if (unlikely(error))
1320                 vmwrite_error(field, value);
1321 }
1322
1323 static void vmcs_write16(unsigned long field, u16 value)
1324 {
1325         vmcs_writel(field, value);
1326 }
1327
1328 static void vmcs_write32(unsigned long field, u32 value)
1329 {
1330         vmcs_writel(field, value);
1331 }
1332
1333 static void vmcs_write64(unsigned long field, u64 value)
1334 {
1335         vmcs_writel(field, value);
1336 #ifndef CONFIG_X86_64
1337         asm volatile ("");
1338         vmcs_writel(field+1, value >> 32);
1339 #endif
1340 }
1341
1342 static void vmcs_clear_bits(unsigned long field, u32 mask)
1343 {
1344         vmcs_writel(field, vmcs_readl(field) & ~mask);
1345 }
1346
1347 static void vmcs_set_bits(unsigned long field, u32 mask)
1348 {
1349         vmcs_writel(field, vmcs_readl(field) | mask);
1350 }
1351
1352 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353 {
1354         vmcs_write32(VM_ENTRY_CONTROLS, val);
1355         vmx->vm_entry_controls_shadow = val;
1356 }
1357
1358 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359 {
1360         if (vmx->vm_entry_controls_shadow != val)
1361                 vm_entry_controls_init(vmx, val);
1362 }
1363
1364 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365 {
1366         return vmx->vm_entry_controls_shadow;
1367 }
1368
1369
1370 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371 {
1372         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373 }
1374
1375 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376 {
1377         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378 }
1379
1380 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381 {
1382         vmcs_write32(VM_EXIT_CONTROLS, val);
1383         vmx->vm_exit_controls_shadow = val;
1384 }
1385
1386 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387 {
1388         if (vmx->vm_exit_controls_shadow != val)
1389                 vm_exit_controls_init(vmx, val);
1390 }
1391
1392 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393 {
1394         return vmx->vm_exit_controls_shadow;
1395 }
1396
1397
1398 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399 {
1400         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401 }
1402
1403 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404 {
1405         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406 }
1407
1408 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409 {
1410         vmx->segment_cache.bitmask = 0;
1411 }
1412
1413 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414                                        unsigned field)
1415 {
1416         bool ret;
1417         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421                 vmx->segment_cache.bitmask = 0;
1422         }
1423         ret = vmx->segment_cache.bitmask & mask;
1424         vmx->segment_cache.bitmask |= mask;
1425         return ret;
1426 }
1427
1428 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429 {
1430         u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434         return *p;
1435 }
1436
1437 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438 {
1439         ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443         return *p;
1444 }
1445
1446 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447 {
1448         u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452         return *p;
1453 }
1454
1455 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456 {
1457         u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461         return *p;
1462 }
1463
1464 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465 {
1466         u32 eb;
1467
1468         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470         if ((vcpu->guest_debug &
1471              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473                 eb |= 1u << BP_VECTOR;
1474         if (to_vmx(vcpu)->rmode.vm86_active)
1475                 eb = ~0;
1476         if (enable_ept)
1477                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1478         if (vcpu->fpu_active)
1479                 eb &= ~(1u << NM_VECTOR);
1480
1481         /* When we are running a nested L2 guest and L1 specified for it a
1482          * certain exception bitmap, we must trap the same exceptions and pass
1483          * them to L1. When running L2, we will only handle the exceptions
1484          * specified above if L1 did not want them.
1485          */
1486         if (is_guest_mode(vcpu))
1487                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
1489         vmcs_write32(EXCEPTION_BITMAP, eb);
1490 }
1491
1492 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493                 unsigned long entry, unsigned long exit)
1494 {
1495         vm_entry_controls_clearbit(vmx, entry);
1496         vm_exit_controls_clearbit(vmx, exit);
1497 }
1498
1499 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500 {
1501         unsigned i;
1502         struct msr_autoload *m = &vmx->msr_autoload;
1503
1504         switch (msr) {
1505         case MSR_EFER:
1506                 if (cpu_has_load_ia32_efer) {
1507                         clear_atomic_switch_msr_special(vmx,
1508                                         VM_ENTRY_LOAD_IA32_EFER,
1509                                         VM_EXIT_LOAD_IA32_EFER);
1510                         return;
1511                 }
1512                 break;
1513         case MSR_CORE_PERF_GLOBAL_CTRL:
1514                 if (cpu_has_load_perf_global_ctrl) {
1515                         clear_atomic_switch_msr_special(vmx,
1516                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518                         return;
1519                 }
1520                 break;
1521         }
1522
1523         for (i = 0; i < m->nr; ++i)
1524                 if (m->guest[i].index == msr)
1525                         break;
1526
1527         if (i == m->nr)
1528                 return;
1529         --m->nr;
1530         m->guest[i] = m->guest[m->nr];
1531         m->host[i] = m->host[m->nr];
1532         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534 }
1535
1536 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537                 unsigned long entry, unsigned long exit,
1538                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539                 u64 guest_val, u64 host_val)
1540 {
1541         vmcs_write64(guest_val_vmcs, guest_val);
1542         vmcs_write64(host_val_vmcs, host_val);
1543         vm_entry_controls_setbit(vmx, entry);
1544         vm_exit_controls_setbit(vmx, exit);
1545 }
1546
1547 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548                                   u64 guest_val, u64 host_val)
1549 {
1550         unsigned i;
1551         struct msr_autoload *m = &vmx->msr_autoload;
1552
1553         switch (msr) {
1554         case MSR_EFER:
1555                 if (cpu_has_load_ia32_efer) {
1556                         add_atomic_switch_msr_special(vmx,
1557                                         VM_ENTRY_LOAD_IA32_EFER,
1558                                         VM_EXIT_LOAD_IA32_EFER,
1559                                         GUEST_IA32_EFER,
1560                                         HOST_IA32_EFER,
1561                                         guest_val, host_val);
1562                         return;
1563                 }
1564                 break;
1565         case MSR_CORE_PERF_GLOBAL_CTRL:
1566                 if (cpu_has_load_perf_global_ctrl) {
1567                         add_atomic_switch_msr_special(vmx,
1568                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1571                                         HOST_IA32_PERF_GLOBAL_CTRL,
1572                                         guest_val, host_val);
1573                         return;
1574                 }
1575                 break;
1576         }
1577
1578         for (i = 0; i < m->nr; ++i)
1579                 if (m->guest[i].index == msr)
1580                         break;
1581
1582         if (i == NR_AUTOLOAD_MSRS) {
1583                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1584                                 "Can't add msr %x\n", msr);
1585                 return;
1586         } else if (i == m->nr) {
1587                 ++m->nr;
1588                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590         }
1591
1592         m->guest[i].index = msr;
1593         m->guest[i].value = guest_val;
1594         m->host[i].index = msr;
1595         m->host[i].value = host_val;
1596 }
1597
1598 static void reload_tss(void)
1599 {
1600         /*
1601          * VT restores TR but not its size.  Useless.
1602          */
1603         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1604         struct desc_struct *descs;
1605
1606         descs = (void *)gdt->address;
1607         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608         load_TR_desc();
1609 }
1610
1611 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1612 {
1613         u64 guest_efer;
1614         u64 ignore_bits;
1615
1616         guest_efer = vmx->vcpu.arch.efer;
1617
1618         /*
1619          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1620          * outside long mode
1621          */
1622         ignore_bits = EFER_NX | EFER_SCE;
1623 #ifdef CONFIG_X86_64
1624         ignore_bits |= EFER_LMA | EFER_LME;
1625         /* SCE is meaningful only in long mode on Intel */
1626         if (guest_efer & EFER_LMA)
1627                 ignore_bits &= ~(u64)EFER_SCE;
1628 #endif
1629         guest_efer &= ~ignore_bits;
1630         guest_efer |= host_efer & ignore_bits;
1631         vmx->guest_msrs[efer_offset].data = guest_efer;
1632         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1633
1634         clear_atomic_switch_msr(vmx, MSR_EFER);
1635         /* On ept, can't emulate nx, and must switch nx atomically */
1636         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637                 guest_efer = vmx->vcpu.arch.efer;
1638                 if (!(guest_efer & EFER_LMA))
1639                         guest_efer &= ~EFER_LME;
1640                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641                 return false;
1642         }
1643
1644         return true;
1645 }
1646
1647 static unsigned long segment_base(u16 selector)
1648 {
1649         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1650         struct desc_struct *d;
1651         unsigned long table_base;
1652         unsigned long v;
1653
1654         if (!(selector & ~3))
1655                 return 0;
1656
1657         table_base = gdt->address;
1658
1659         if (selector & 4) {           /* from ldt */
1660                 u16 ldt_selector = kvm_read_ldt();
1661
1662                 if (!(ldt_selector & ~3))
1663                         return 0;
1664
1665                 table_base = segment_base(ldt_selector);
1666         }
1667         d = (struct desc_struct *)(table_base + (selector & ~7));
1668         v = get_desc_base(d);
1669 #ifdef CONFIG_X86_64
1670        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672 #endif
1673         return v;
1674 }
1675
1676 static inline unsigned long kvm_read_tr_base(void)
1677 {
1678         u16 tr;
1679         asm("str %0" : "=g"(tr));
1680         return segment_base(tr);
1681 }
1682
1683 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1684 {
1685         struct vcpu_vmx *vmx = to_vmx(vcpu);
1686         int i;
1687
1688         if (vmx->host_state.loaded)
1689                 return;
1690
1691         vmx->host_state.loaded = 1;
1692         /*
1693          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1694          * allow segment selectors with cpl > 0 or ti == 1.
1695          */
1696         vmx->host_state.ldt_sel = kvm_read_ldt();
1697         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1698         savesegment(fs, vmx->host_state.fs_sel);
1699         if (!(vmx->host_state.fs_sel & 7)) {
1700                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1701                 vmx->host_state.fs_reload_needed = 0;
1702         } else {
1703                 vmcs_write16(HOST_FS_SELECTOR, 0);
1704                 vmx->host_state.fs_reload_needed = 1;
1705         }
1706         savesegment(gs, vmx->host_state.gs_sel);
1707         if (!(vmx->host_state.gs_sel & 7))
1708                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1709         else {
1710                 vmcs_write16(HOST_GS_SELECTOR, 0);
1711                 vmx->host_state.gs_ldt_reload_needed = 1;
1712         }
1713
1714 #ifdef CONFIG_X86_64
1715         savesegment(ds, vmx->host_state.ds_sel);
1716         savesegment(es, vmx->host_state.es_sel);
1717 #endif
1718
1719 #ifdef CONFIG_X86_64
1720         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722 #else
1723         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1725 #endif
1726
1727 #ifdef CONFIG_X86_64
1728         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729         if (is_long_mode(&vmx->vcpu))
1730                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1731 #endif
1732         if (boot_cpu_has(X86_FEATURE_MPX))
1733                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1734         for (i = 0; i < vmx->save_nmsrs; ++i)
1735                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1736                                    vmx->guest_msrs[i].data,
1737                                    vmx->guest_msrs[i].mask);
1738 }
1739
1740 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1741 {
1742         if (!vmx->host_state.loaded)
1743                 return;
1744
1745         ++vmx->vcpu.stat.host_state_reload;
1746         vmx->host_state.loaded = 0;
1747 #ifdef CONFIG_X86_64
1748         if (is_long_mode(&vmx->vcpu))
1749                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750 #endif
1751         if (vmx->host_state.gs_ldt_reload_needed) {
1752                 kvm_load_ldt(vmx->host_state.ldt_sel);
1753 #ifdef CONFIG_X86_64
1754                 load_gs_index(vmx->host_state.gs_sel);
1755 #else
1756                 loadsegment(gs, vmx->host_state.gs_sel);
1757 #endif
1758         }
1759         if (vmx->host_state.fs_reload_needed)
1760                 loadsegment(fs, vmx->host_state.fs_sel);
1761 #ifdef CONFIG_X86_64
1762         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763                 loadsegment(ds, vmx->host_state.ds_sel);
1764                 loadsegment(es, vmx->host_state.es_sel);
1765         }
1766 #endif
1767         reload_tss();
1768 #ifdef CONFIG_X86_64
1769         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1770 #endif
1771         if (vmx->host_state.msr_host_bndcfgs)
1772                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1773         /*
1774          * If the FPU is not active (through the host task or
1775          * the guest vcpu), then restore the cr0.TS bit.
1776          */
1777         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778                 stts();
1779         load_gdt(&__get_cpu_var(host_gdt));
1780 }
1781
1782 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783 {
1784         preempt_disable();
1785         __vmx_load_host_state(vmx);
1786         preempt_enable();
1787 }
1788
1789 /*
1790  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791  * vcpu mutex is already taken.
1792  */
1793 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1794 {
1795         struct vcpu_vmx *vmx = to_vmx(vcpu);
1796         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1797
1798         if (!vmm_exclusive)
1799                 kvm_cpu_vmxon(phys_addr);
1800         else if (vmx->loaded_vmcs->cpu != cpu)
1801                 loaded_vmcs_clear(vmx->loaded_vmcs);
1802
1803         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805                 vmcs_load(vmx->loaded_vmcs->vmcs);
1806         }
1807
1808         if (vmx->loaded_vmcs->cpu != cpu) {
1809                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1810                 unsigned long sysenter_esp;
1811
1812                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1813                 local_irq_disable();
1814                 crash_disable_local_vmclear(cpu);
1815
1816                 /*
1817                  * Read loaded_vmcs->cpu should be before fetching
1818                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819                  * See the comments in __loaded_vmcs_clear().
1820                  */
1821                 smp_rmb();
1822
1823                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1825                 crash_enable_local_vmclear(cpu);
1826                 local_irq_enable();
1827
1828                 /*
1829                  * Linux uses per-cpu TSS and GDT, so set these when switching
1830                  * processors.
1831                  */
1832                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1833                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1834
1835                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1837                 vmx->loaded_vmcs->cpu = cpu;
1838         }
1839 }
1840
1841 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842 {
1843         __vmx_load_host_state(to_vmx(vcpu));
1844         if (!vmm_exclusive) {
1845                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846                 vcpu->cpu = -1;
1847                 kvm_cpu_vmxoff();
1848         }
1849 }
1850
1851 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852 {
1853         ulong cr0;
1854
1855         if (vcpu->fpu_active)
1856                 return;
1857         vcpu->fpu_active = 1;
1858         cr0 = vmcs_readl(GUEST_CR0);
1859         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861         vmcs_writel(GUEST_CR0, cr0);
1862         update_exception_bitmap(vcpu);
1863         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1864         if (is_guest_mode(vcpu))
1865                 vcpu->arch.cr0_guest_owned_bits &=
1866                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1867         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1868 }
1869
1870 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
1872 /*
1873  * Return the cr0 value that a nested guest would read. This is a combination
1874  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875  * its hypervisor (cr0_read_shadow).
1876  */
1877 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878 {
1879         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881 }
1882 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883 {
1884         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886 }
1887
1888 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889 {
1890         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891          * set this *before* calling this function.
1892          */
1893         vmx_decache_cr0_guest_bits(vcpu);
1894         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1895         update_exception_bitmap(vcpu);
1896         vcpu->arch.cr0_guest_owned_bits = 0;
1897         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1898         if (is_guest_mode(vcpu)) {
1899                 /*
1900                  * L1's specified read shadow might not contain the TS bit,
1901                  * so now that we turned on shadowing of this bit, we need to
1902                  * set this bit of the shadow. Like in nested_vmx_run we need
1903                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904                  * up-to-date here because we just decached cr0.TS (and we'll
1905                  * only update vmcs12->guest_cr0 on nested exit).
1906                  */
1907                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909                         (vcpu->arch.cr0 & X86_CR0_TS);
1910                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911         } else
1912                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1913 }
1914
1915 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916 {
1917         unsigned long rflags, save_rflags;
1918
1919         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921                 rflags = vmcs_readl(GUEST_RFLAGS);
1922                 if (to_vmx(vcpu)->rmode.vm86_active) {
1923                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926                 }
1927                 to_vmx(vcpu)->rflags = rflags;
1928         }
1929         return to_vmx(vcpu)->rflags;
1930 }
1931
1932 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933 {
1934         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935         to_vmx(vcpu)->rflags = rflags;
1936         if (to_vmx(vcpu)->rmode.vm86_active) {
1937                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1938                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1939         }
1940         vmcs_writel(GUEST_RFLAGS, rflags);
1941 }
1942
1943 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944 {
1945         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946         int ret = 0;
1947
1948         if (interruptibility & GUEST_INTR_STATE_STI)
1949                 ret |= KVM_X86_SHADOW_INT_STI;
1950         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1951                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1952
1953         return ret & mask;
1954 }
1955
1956 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957 {
1958         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959         u32 interruptibility = interruptibility_old;
1960
1961         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
1963         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1964                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1965         else if (mask & KVM_X86_SHADOW_INT_STI)
1966                 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968         if ((interruptibility != interruptibility_old))
1969                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970 }
1971
1972 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973 {
1974         unsigned long rip;
1975
1976         rip = kvm_rip_read(vcpu);
1977         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1978         kvm_rip_write(vcpu, rip);
1979
1980         /* skipping an emulated instruction also counts */
1981         vmx_set_interrupt_shadow(vcpu, 0);
1982 }
1983
1984 /*
1985  * KVM wants to inject page-faults which it got to the guest. This function
1986  * checks whether in a nested guest, we need to inject them to L1 or L2.
1987  */
1988 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1989 {
1990         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
1992         if (!(vmcs12->exception_bitmap & (1u << nr)))
1993                 return 0;
1994
1995         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996                           vmcs_read32(VM_EXIT_INTR_INFO),
1997                           vmcs_readl(EXIT_QUALIFICATION));
1998         return 1;
1999 }
2000
2001 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2002                                 bool has_error_code, u32 error_code,
2003                                 bool reinject)
2004 {
2005         struct vcpu_vmx *vmx = to_vmx(vcpu);
2006         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2007
2008         if (!reinject && is_guest_mode(vcpu) &&
2009             nested_vmx_check_exception(vcpu, nr))
2010                 return;
2011
2012         if (has_error_code) {
2013                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2014                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015         }
2016
2017         if (vmx->rmode.vm86_active) {
2018                 int inc_eip = 0;
2019                 if (kvm_exception_is_soft(nr))
2020                         inc_eip = vcpu->arch.event_exit_inst_len;
2021                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2022                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2023                 return;
2024         }
2025
2026         if (kvm_exception_is_soft(nr)) {
2027                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028                              vmx->vcpu.arch.event_exit_inst_len);
2029                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030         } else
2031                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2034 }
2035
2036 static bool vmx_rdtscp_supported(void)
2037 {
2038         return cpu_has_vmx_rdtscp();
2039 }
2040
2041 static bool vmx_invpcid_supported(void)
2042 {
2043         return cpu_has_vmx_invpcid() && enable_ept;
2044 }
2045
2046 /*
2047  * Swap MSR entry in host/guest MSR entry array.
2048  */
2049 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2050 {
2051         struct shared_msr_entry tmp;
2052
2053         tmp = vmx->guest_msrs[to];
2054         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055         vmx->guest_msrs[from] = tmp;
2056 }
2057
2058 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059 {
2060         unsigned long *msr_bitmap;
2061
2062         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063                 if (is_long_mode(vcpu))
2064                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065                 else
2066                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067         } else {
2068                 if (is_long_mode(vcpu))
2069                         msr_bitmap = vmx_msr_bitmap_longmode;
2070                 else
2071                         msr_bitmap = vmx_msr_bitmap_legacy;
2072         }
2073
2074         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075 }
2076
2077 /*
2078  * Set up the vmcs to automatically save and restore system
2079  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2080  * mode, as fiddling with msrs is very expensive.
2081  */
2082 static void setup_msrs(struct vcpu_vmx *vmx)
2083 {
2084         int save_nmsrs, index;
2085
2086         save_nmsrs = 0;
2087 #ifdef CONFIG_X86_64
2088         if (is_long_mode(&vmx->vcpu)) {
2089                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2090                 if (index >= 0)
2091                         move_msr_up(vmx, index, save_nmsrs++);
2092                 index = __find_msr_index(vmx, MSR_LSTAR);
2093                 if (index >= 0)
2094                         move_msr_up(vmx, index, save_nmsrs++);
2095                 index = __find_msr_index(vmx, MSR_CSTAR);
2096                 if (index >= 0)
2097                         move_msr_up(vmx, index, save_nmsrs++);
2098                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099                 if (index >= 0 && vmx->rdtscp_enabled)
2100                         move_msr_up(vmx, index, save_nmsrs++);
2101                 /*
2102                  * MSR_STAR is only needed on long mode guests, and only
2103                  * if efer.sce is enabled.
2104                  */
2105                 index = __find_msr_index(vmx, MSR_STAR);
2106                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2107                         move_msr_up(vmx, index, save_nmsrs++);
2108         }
2109 #endif
2110         index = __find_msr_index(vmx, MSR_EFER);
2111         if (index >= 0 && update_transition_efer(vmx, index))
2112                 move_msr_up(vmx, index, save_nmsrs++);
2113
2114         vmx->save_nmsrs = save_nmsrs;
2115
2116         if (cpu_has_vmx_msr_bitmap())
2117                 vmx_set_msr_bitmap(&vmx->vcpu);
2118 }
2119
2120 /*
2121  * reads and returns guest's timestamp counter "register"
2122  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2123  */
2124 static u64 guest_read_tsc(void)
2125 {
2126         u64 host_tsc, tsc_offset;
2127
2128         rdtscll(host_tsc);
2129         tsc_offset = vmcs_read64(TSC_OFFSET);
2130         return host_tsc + tsc_offset;
2131 }
2132
2133 /*
2134  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135  * counter, even if a nested guest (L2) is currently running.
2136  */
2137 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2138 {
2139         u64 tsc_offset;
2140
2141         tsc_offset = is_guest_mode(vcpu) ?
2142                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143                 vmcs_read64(TSC_OFFSET);
2144         return host_tsc + tsc_offset;
2145 }
2146
2147 /*
2148  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2149  * software catchup for faster rates on slower CPUs.
2150  */
2151 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2152 {
2153         if (!scale)
2154                 return;
2155
2156         if (user_tsc_khz > tsc_khz) {
2157                 vcpu->arch.tsc_catchup = 1;
2158                 vcpu->arch.tsc_always_catchup = 1;
2159         } else
2160                 WARN(1, "user requested TSC rate below hardware speed\n");
2161 }
2162
2163 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164 {
2165         return vmcs_read64(TSC_OFFSET);
2166 }
2167
2168 /*
2169  * writes 'offset' into guest's timestamp counter offset register
2170  */
2171 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2172 {
2173         if (is_guest_mode(vcpu)) {
2174                 /*
2175                  * We're here if L1 chose not to trap WRMSR to TSC. According
2176                  * to the spec, this should set L1's TSC; The offset that L1
2177                  * set for L2 remains unchanged, and still needs to be added
2178                  * to the newly set TSC to get L2's TSC.
2179                  */
2180                 struct vmcs12 *vmcs12;
2181                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182                 /* recalculate vmcs02.TSC_OFFSET: */
2183                 vmcs12 = get_vmcs12(vcpu);
2184                 vmcs_write64(TSC_OFFSET, offset +
2185                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186                          vmcs12->tsc_offset : 0));
2187         } else {
2188                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189                                            vmcs_read64(TSC_OFFSET), offset);
2190                 vmcs_write64(TSC_OFFSET, offset);
2191         }
2192 }
2193
2194 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2195 {
2196         u64 offset = vmcs_read64(TSC_OFFSET);
2197
2198         vmcs_write64(TSC_OFFSET, offset + adjustment);
2199         if (is_guest_mode(vcpu)) {
2200                 /* Even when running L2, the adjustment needs to apply to L1 */
2201                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2202         } else
2203                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204                                            offset + adjustment);
2205 }
2206
2207 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208 {
2209         return target_tsc - native_read_tsc();
2210 }
2211
2212 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213 {
2214         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216 }
2217
2218 /*
2219  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221  * all guests if the "nested" module option is off, and can also be disabled
2222  * for a single guest by disabling its VMX cpuid bit.
2223  */
2224 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225 {
2226         return nested && guest_cpuid_has_vmx(vcpu);
2227 }
2228
2229 /*
2230  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231  * returned for the various VMX controls MSRs when nested VMX is enabled.
2232  * The same values should also be used to verify that vmcs12 control fields are
2233  * valid during nested entry from L1 to L2.
2234  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236  * bit in the high half is on if the corresponding bit in the control field
2237  * may be on. See also vmx_control_verify().
2238  * TODO: allow these variables to be modified (downgraded) by module options
2239  * or other means.
2240  */
2241 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2242 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2243 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2244 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2245 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2246 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2247 static u32 nested_vmx_ept_caps;
2248 static __init void nested_vmx_setup_ctls_msrs(void)
2249 {
2250         /*
2251          * Note that as a general rule, the high half of the MSRs (bits in
2252          * the control fields which may be 1) should be initialized by the
2253          * intersection of the underlying hardware's MSR (i.e., features which
2254          * can be supported) and the list of features we want to expose -
2255          * because they are known to be properly supported in our code.
2256          * Also, usually, the low half of the MSRs (bits which must be 1) can
2257          * be set to 0, meaning that L1 may turn off any of these bits. The
2258          * reason is that if one of these bits is necessary, it will appear
2259          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260          * fields of vmcs01 and vmcs02, will turn these bits off - and
2261          * nested_vmx_exit_handled() will not pass related exits to L1.
2262          * These rules have exceptions below.
2263          */
2264
2265         /* pin-based controls */
2266         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2267               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2268         /*
2269          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2271          */
2272         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2273         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2274                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2275         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2276                 PIN_BASED_VMX_PREEMPTION_TIMER;
2277
2278         /*
2279          * Exit controls
2280          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2281          * 17 must be 1.
2282          */
2283         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2285         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2286         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2287         nested_vmx_exit_ctls_high &=
2288 #ifdef CONFIG_X86_64
2289                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2290 #endif
2291                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2294                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2295         if (vmx_mpx_supported())
2296                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2297
2298         /* entry controls */
2299         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2300                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2301         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2302         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2303         nested_vmx_entry_ctls_high &=
2304 #ifdef CONFIG_X86_64
2305                 VM_ENTRY_IA32E_MODE |
2306 #endif
2307                 VM_ENTRY_LOAD_IA32_PAT;
2308         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2309                                        VM_ENTRY_LOAD_IA32_EFER);
2310         if (vmx_mpx_supported())
2311                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2312
2313         /* cpu-based controls */
2314         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2315                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2316         nested_vmx_procbased_ctls_low = 0;
2317         nested_vmx_procbased_ctls_high &=
2318                 CPU_BASED_VIRTUAL_INTR_PENDING |
2319                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2320                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2321                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2322                 CPU_BASED_CR3_STORE_EXITING |
2323 #ifdef CONFIG_X86_64
2324                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2325 #endif
2326                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2327                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2328                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2329                 CPU_BASED_PAUSE_EXITING |
2330                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2331         /*
2332          * We can allow some features even when not supported by the
2333          * hardware. For example, L1 can specify an MSR bitmap - and we
2334          * can use it to avoid exits to L1 - even when L0 runs L2
2335          * without MSR bitmaps.
2336          */
2337         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2338
2339         /* secondary cpu-based controls */
2340         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2341                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2342         nested_vmx_secondary_ctls_low = 0;
2343         nested_vmx_secondary_ctls_high &=
2344                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2345                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2346                 SECONDARY_EXEC_WBINVD_EXITING;
2347
2348         if (enable_ept) {
2349                 /* nested EPT: emulate EPT also to L1 */
2350                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2351                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2352                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2353                          VMX_EPT_INVEPT_BIT;
2354                 nested_vmx_ept_caps &= vmx_capability.ept;
2355                 /*
2356                  * Since invept is completely emulated we support both global
2357                  * and context invalidation independent of what host cpu
2358                  * supports
2359                  */
2360                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2361                         VMX_EPT_EXTENT_CONTEXT_BIT;
2362         } else
2363                 nested_vmx_ept_caps = 0;
2364
2365         /* miscellaneous data */
2366         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2367         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2368         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2369                 VMX_MISC_ACTIVITY_HLT;
2370         nested_vmx_misc_high = 0;
2371 }
2372
2373 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2374 {
2375         /*
2376          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2377          */
2378         return ((control & high) | low) == control;
2379 }
2380
2381 static inline u64 vmx_control_msr(u32 low, u32 high)
2382 {
2383         return low | ((u64)high << 32);
2384 }
2385
2386 /* Returns 0 on success, non-0 otherwise. */
2387 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2388 {
2389         switch (msr_index) {
2390         case MSR_IA32_VMX_BASIC:
2391                 /*
2392                  * This MSR reports some information about VMX support. We
2393                  * should return information about the VMX we emulate for the
2394                  * guest, and the VMCS structure we give it - not about the
2395                  * VMX support of the underlying hardware.
2396                  */
2397                 *pdata = VMCS12_REVISION |
2398                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2399                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2400                 break;
2401         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2402         case MSR_IA32_VMX_PINBASED_CTLS:
2403                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2404                                         nested_vmx_pinbased_ctls_high);
2405                 break;
2406         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2407         case MSR_IA32_VMX_PROCBASED_CTLS:
2408                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2409                                         nested_vmx_procbased_ctls_high);
2410                 break;
2411         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2412         case MSR_IA32_VMX_EXIT_CTLS:
2413                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2414                                         nested_vmx_exit_ctls_high);
2415                 break;
2416         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2417         case MSR_IA32_VMX_ENTRY_CTLS:
2418                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2419                                         nested_vmx_entry_ctls_high);
2420                 break;
2421         case MSR_IA32_VMX_MISC:
2422                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2423                                          nested_vmx_misc_high);
2424                 break;
2425         /*
2426          * These MSRs specify bits which the guest must keep fixed (on or off)
2427          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428          * We picked the standard core2 setting.
2429          */
2430 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2432         case MSR_IA32_VMX_CR0_FIXED0:
2433                 *pdata = VMXON_CR0_ALWAYSON;
2434                 break;
2435         case MSR_IA32_VMX_CR0_FIXED1:
2436                 *pdata = -1ULL;
2437                 break;
2438         case MSR_IA32_VMX_CR4_FIXED0:
2439                 *pdata = VMXON_CR4_ALWAYSON;
2440                 break;
2441         case MSR_IA32_VMX_CR4_FIXED1:
2442                 *pdata = -1ULL;
2443                 break;
2444         case MSR_IA32_VMX_VMCS_ENUM:
2445                 *pdata = 0x1f;
2446                 break;
2447         case MSR_IA32_VMX_PROCBASED_CTLS2:
2448                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2449                                         nested_vmx_secondary_ctls_high);
2450                 break;
2451         case MSR_IA32_VMX_EPT_VPID_CAP:
2452                 /* Currently, no nested vpid support */
2453                 *pdata = nested_vmx_ept_caps;
2454                 break;
2455         default:
2456                 return 1;
2457         }
2458
2459         return 0;
2460 }
2461
2462 /*
2463  * Reads an msr value (of 'msr_index') into 'pdata'.
2464  * Returns 0 on success, non-0 otherwise.
2465  * Assumes vcpu_load() was already called.
2466  */
2467 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2468 {
2469         u64 data;
2470         struct shared_msr_entry *msr;
2471
2472         if (!pdata) {
2473                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2474                 return -EINVAL;
2475         }
2476
2477         switch (msr_index) {
2478 #ifdef CONFIG_X86_64
2479         case MSR_FS_BASE:
2480                 data = vmcs_readl(GUEST_FS_BASE);
2481                 break;
2482         case MSR_GS_BASE:
2483                 data = vmcs_readl(GUEST_GS_BASE);
2484                 break;
2485         case MSR_KERNEL_GS_BASE:
2486                 vmx_load_host_state(to_vmx(vcpu));
2487                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2488                 break;
2489 #endif
2490         case MSR_EFER:
2491                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2492         case MSR_IA32_TSC:
2493                 data = guest_read_tsc();
2494                 break;
2495         case MSR_IA32_SYSENTER_CS:
2496                 data = vmcs_read32(GUEST_SYSENTER_CS);
2497                 break;
2498         case MSR_IA32_SYSENTER_EIP:
2499                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2500                 break;
2501         case MSR_IA32_SYSENTER_ESP:
2502                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2503                 break;
2504         case MSR_IA32_BNDCFGS:
2505                 if (!vmx_mpx_supported())
2506                         return 1;
2507                 data = vmcs_read64(GUEST_BNDCFGS);
2508                 break;
2509         case MSR_IA32_FEATURE_CONTROL:
2510                 if (!nested_vmx_allowed(vcpu))
2511                         return 1;
2512                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2513                 break;
2514         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2515                 if (!nested_vmx_allowed(vcpu))
2516                         return 1;
2517                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2518         case MSR_TSC_AUX:
2519                 if (!to_vmx(vcpu)->rdtscp_enabled)
2520                         return 1;
2521                 /* Otherwise falls through */
2522         default:
2523                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2524                 if (msr) {
2525                         data = msr->data;
2526                         break;
2527                 }
2528                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2529         }
2530
2531         *pdata = data;
2532         return 0;
2533 }
2534
2535 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2536
2537 /*
2538  * Writes msr value into into the appropriate "register".
2539  * Returns 0 on success, non-0 otherwise.
2540  * Assumes vcpu_load() was already called.
2541  */
2542 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2543 {
2544         struct vcpu_vmx *vmx = to_vmx(vcpu);
2545         struct shared_msr_entry *msr;
2546         int ret = 0;
2547         u32 msr_index = msr_info->index;
2548         u64 data = msr_info->data;
2549
2550         switch (msr_index) {
2551         case MSR_EFER:
2552                 ret = kvm_set_msr_common(vcpu, msr_info);
2553                 break;
2554 #ifdef CONFIG_X86_64
2555         case MSR_FS_BASE:
2556                 vmx_segment_cache_clear(vmx);
2557                 vmcs_writel(GUEST_FS_BASE, data);
2558                 break;
2559         case MSR_GS_BASE:
2560                 vmx_segment_cache_clear(vmx);
2561                 vmcs_writel(GUEST_GS_BASE, data);
2562                 break;
2563         case MSR_KERNEL_GS_BASE:
2564                 vmx_load_host_state(vmx);
2565                 vmx->msr_guest_kernel_gs_base = data;
2566                 break;
2567 #endif
2568         case MSR_IA32_SYSENTER_CS:
2569                 vmcs_write32(GUEST_SYSENTER_CS, data);
2570                 break;
2571         case MSR_IA32_SYSENTER_EIP:
2572                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2573                 break;
2574         case MSR_IA32_SYSENTER_ESP:
2575                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2576                 break;
2577         case MSR_IA32_BNDCFGS:
2578                 if (!vmx_mpx_supported())
2579                         return 1;
2580                 vmcs_write64(GUEST_BNDCFGS, data);
2581                 break;
2582         case MSR_IA32_TSC:
2583                 kvm_write_tsc(vcpu, msr_info);
2584                 break;
2585         case MSR_IA32_CR_PAT:
2586                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2587                         vmcs_write64(GUEST_IA32_PAT, data);
2588                         vcpu->arch.pat = data;
2589                         break;
2590                 }
2591                 ret = kvm_set_msr_common(vcpu, msr_info);
2592                 break;
2593         case MSR_IA32_TSC_ADJUST:
2594                 ret = kvm_set_msr_common(vcpu, msr_info);
2595                 break;
2596         case MSR_IA32_FEATURE_CONTROL:
2597                 if (!nested_vmx_allowed(vcpu) ||
2598                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2599                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2600                         return 1;
2601                 vmx->nested.msr_ia32_feature_control = data;
2602                 if (msr_info->host_initiated && data == 0)
2603                         vmx_leave_nested(vcpu);
2604                 break;
2605         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2606                 return 1; /* they are read-only */
2607         case MSR_TSC_AUX:
2608                 if (!vmx->rdtscp_enabled)
2609                         return 1;
2610                 /* Check reserved bit, higher 32 bits should be zero */
2611                 if ((data >> 32) != 0)
2612                         return 1;
2613                 /* Otherwise falls through */
2614         default:
2615                 msr = find_msr_entry(vmx, msr_index);
2616                 if (msr) {
2617                         msr->data = data;
2618                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2619                                 preempt_disable();
2620                                 kvm_set_shared_msr(msr->index, msr->data,
2621                                                    msr->mask);
2622                                 preempt_enable();
2623                         }
2624                         break;
2625                 }
2626                 ret = kvm_set_msr_common(vcpu, msr_info);
2627         }
2628
2629         return ret;
2630 }
2631
2632 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2633 {
2634         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2635         switch (reg) {
2636         case VCPU_REGS_RSP:
2637                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2638                 break;
2639         case VCPU_REGS_RIP:
2640                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2641                 break;
2642         case VCPU_EXREG_PDPTR:
2643                 if (enable_ept)
2644                         ept_save_pdptrs(vcpu);
2645                 break;
2646         default:
2647                 break;
2648         }
2649 }
2650
2651 static __init int cpu_has_kvm_support(void)
2652 {
2653         return cpu_has_vmx();
2654 }
2655
2656 static __init int vmx_disabled_by_bios(void)
2657 {
2658         u64 msr;
2659
2660         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2661         if (msr & FEATURE_CONTROL_LOCKED) {
2662                 /* launched w/ TXT and VMX disabled */
2663                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2664                         && tboot_enabled())
2665                         return 1;
2666                 /* launched w/o TXT and VMX only enabled w/ TXT */
2667                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2668                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2669                         && !tboot_enabled()) {
2670                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2671                                 "activate TXT before enabling KVM\n");
2672                         return 1;
2673                 }
2674                 /* launched w/o TXT and VMX disabled */
2675                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2676                         && !tboot_enabled())
2677                         return 1;
2678         }
2679
2680         return 0;
2681 }
2682
2683 static void kvm_cpu_vmxon(u64 addr)
2684 {
2685         asm volatile (ASM_VMX_VMXON_RAX
2686                         : : "a"(&addr), "m"(addr)
2687                         : "memory", "cc");
2688 }
2689
2690 static int hardware_enable(void *garbage)
2691 {
2692         int cpu = raw_smp_processor_id();
2693         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2694         u64 old, test_bits;
2695
2696         if (read_cr4() & X86_CR4_VMXE)
2697                 return -EBUSY;
2698
2699         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2700
2701         /*
2702          * Now we can enable the vmclear operation in kdump
2703          * since the loaded_vmcss_on_cpu list on this cpu
2704          * has been initialized.
2705          *
2706          * Though the cpu is not in VMX operation now, there
2707          * is no problem to enable the vmclear operation
2708          * for the loaded_vmcss_on_cpu list is empty!
2709          */
2710         crash_enable_local_vmclear(cpu);
2711
2712         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2713
2714         test_bits = FEATURE_CONTROL_LOCKED;
2715         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2716         if (tboot_enabled())
2717                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2718
2719         if ((old & test_bits) != test_bits) {
2720                 /* enable and lock */
2721                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2722         }
2723         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2724
2725         if (vmm_exclusive) {
2726                 kvm_cpu_vmxon(phys_addr);
2727                 ept_sync_global();
2728         }
2729
2730         native_store_gdt(&__get_cpu_var(host_gdt));
2731
2732         return 0;
2733 }
2734
2735 static void vmclear_local_loaded_vmcss(void)
2736 {
2737         int cpu = raw_smp_processor_id();
2738         struct loaded_vmcs *v, *n;
2739
2740         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2741                                  loaded_vmcss_on_cpu_link)
2742                 __loaded_vmcs_clear(v);
2743 }
2744
2745
2746 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2747  * tricks.
2748  */
2749 static void kvm_cpu_vmxoff(void)
2750 {
2751         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2752 }
2753
2754 static void hardware_disable(void *garbage)
2755 {
2756         if (vmm_exclusive) {
2757                 vmclear_local_loaded_vmcss();
2758                 kvm_cpu_vmxoff();
2759         }
2760         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2761 }
2762
2763 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2764                                       u32 msr, u32 *result)
2765 {
2766         u32 vmx_msr_low, vmx_msr_high;
2767         u32 ctl = ctl_min | ctl_opt;
2768
2769         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2770
2771         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2772         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2773
2774         /* Ensure minimum (required) set of control bits are supported. */
2775         if (ctl_min & ~ctl)
2776                 return -EIO;
2777
2778         *result = ctl;
2779         return 0;
2780 }
2781
2782 static __init bool allow_1_setting(u32 msr, u32 ctl)
2783 {
2784         u32 vmx_msr_low, vmx_msr_high;
2785
2786         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2787         return vmx_msr_high & ctl;
2788 }
2789
2790 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2791 {
2792         u32 vmx_msr_low, vmx_msr_high;
2793         u32 min, opt, min2, opt2;
2794         u32 _pin_based_exec_control = 0;
2795         u32 _cpu_based_exec_control = 0;
2796         u32 _cpu_based_2nd_exec_control = 0;
2797         u32 _vmexit_control = 0;
2798         u32 _vmentry_control = 0;
2799
2800         min = CPU_BASED_HLT_EXITING |
2801 #ifdef CONFIG_X86_64
2802               CPU_BASED_CR8_LOAD_EXITING |
2803               CPU_BASED_CR8_STORE_EXITING |
2804 #endif
2805               CPU_BASED_CR3_LOAD_EXITING |
2806               CPU_BASED_CR3_STORE_EXITING |
2807               CPU_BASED_USE_IO_BITMAPS |
2808               CPU_BASED_MOV_DR_EXITING |
2809               CPU_BASED_USE_TSC_OFFSETING |
2810               CPU_BASED_MWAIT_EXITING |
2811               CPU_BASED_MONITOR_EXITING |
2812               CPU_BASED_INVLPG_EXITING |
2813               CPU_BASED_RDPMC_EXITING;
2814
2815         opt = CPU_BASED_TPR_SHADOW |
2816               CPU_BASED_USE_MSR_BITMAPS |
2817               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2818         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2819                                 &_cpu_based_exec_control) < 0)
2820                 return -EIO;
2821 #ifdef CONFIG_X86_64
2822         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2823                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2824                                            ~CPU_BASED_CR8_STORE_EXITING;
2825 #endif
2826         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2827                 min2 = 0;
2828                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2829                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2830                         SECONDARY_EXEC_WBINVD_EXITING |
2831                         SECONDARY_EXEC_ENABLE_VPID |
2832                         SECONDARY_EXEC_ENABLE_EPT |
2833                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2834                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2835                         SECONDARY_EXEC_RDTSCP |
2836                         SECONDARY_EXEC_ENABLE_INVPCID |
2837                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2838                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2839                         SECONDARY_EXEC_SHADOW_VMCS;
2840                 if (adjust_vmx_controls(min2, opt2,
2841                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2842                                         &_cpu_based_2nd_exec_control) < 0)
2843                         return -EIO;
2844         }
2845 #ifndef CONFIG_X86_64
2846         if (!(_cpu_based_2nd_exec_control &
2847                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2848                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2849 #endif
2850
2851         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2852                 _cpu_based_2nd_exec_control &= ~(
2853                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2854                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2855                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2856
2857         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2858                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2859                    enabled */
2860                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2861                                              CPU_BASED_CR3_STORE_EXITING |
2862                                              CPU_BASED_INVLPG_EXITING);
2863                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2864                       vmx_capability.ept, vmx_capability.vpid);
2865         }
2866
2867         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2868 #ifdef CONFIG_X86_64
2869         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2870 #endif
2871         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2872                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2873         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2874                                 &_vmexit_control) < 0)
2875                 return -EIO;
2876
2877         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2878         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2879         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2880                                 &_pin_based_exec_control) < 0)
2881                 return -EIO;
2882
2883         if (!(_cpu_based_2nd_exec_control &
2884                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2885                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2886                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2887
2888         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2889         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2890         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2891                                 &_vmentry_control) < 0)
2892                 return -EIO;
2893
2894         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2895
2896         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2897         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2898                 return -EIO;
2899
2900 #ifdef CONFIG_X86_64
2901         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2902         if (vmx_msr_high & (1u<<16))
2903                 return -EIO;
2904 #endif
2905
2906         /* Require Write-Back (WB) memory type for VMCS accesses. */
2907         if (((vmx_msr_high >> 18) & 15) != 6)
2908                 return -EIO;
2909
2910         vmcs_conf->size = vmx_msr_high & 0x1fff;
2911         vmcs_conf->order = get_order(vmcs_config.size);
2912         vmcs_conf->revision_id = vmx_msr_low;
2913
2914         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2915         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2916         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2917         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2918         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2919
2920         cpu_has_load_ia32_efer =
2921                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2922                                 VM_ENTRY_LOAD_IA32_EFER)
2923                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2924                                    VM_EXIT_LOAD_IA32_EFER);
2925
2926         cpu_has_load_perf_global_ctrl =
2927                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2928                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2929                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2930                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2931
2932         /*
2933          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2934          * but due to arrata below it can't be used. Workaround is to use
2935          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2936          *
2937          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2938          *
2939          * AAK155             (model 26)
2940          * AAP115             (model 30)
2941          * AAT100             (model 37)
2942          * BC86,AAY89,BD102   (model 44)
2943          * BA97               (model 46)
2944          *
2945          */
2946         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2947                 switch (boot_cpu_data.x86_model) {
2948                 case 26:
2949                 case 30:
2950                 case 37:
2951                 case 44:
2952                 case 46:
2953                         cpu_has_load_perf_global_ctrl = false;
2954                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2955                                         "does not work properly. Using workaround\n");
2956                         break;
2957                 default:
2958                         break;
2959                 }
2960         }
2961
2962         return 0;
2963 }
2964
2965 static struct vmcs *alloc_vmcs_cpu(int cpu)
2966 {
2967         int node = cpu_to_node(cpu);
2968         struct page *pages;
2969         struct vmcs *vmcs;
2970
2971         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2972         if (!pages)
2973                 return NULL;
2974         vmcs = page_address(pages);
2975         memset(vmcs, 0, vmcs_config.size);
2976         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2977         return vmcs;
2978 }
2979
2980 static struct vmcs *alloc_vmcs(void)
2981 {
2982         return alloc_vmcs_cpu(raw_smp_processor_id());
2983 }
2984
2985 static void free_vmcs(struct vmcs *vmcs)
2986 {
2987         free_pages((unsigned long)vmcs, vmcs_config.order);
2988 }
2989
2990 /*
2991  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2992  */
2993 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2994 {
2995         if (!loaded_vmcs->vmcs)
2996                 return;
2997         loaded_vmcs_clear(loaded_vmcs);
2998         free_vmcs(loaded_vmcs->vmcs);
2999         loaded_vmcs->vmcs = NULL;
3000 }
3001
3002 static void free_kvm_area(void)
3003 {
3004         int cpu;
3005
3006         for_each_possible_cpu(cpu) {
3007                 free_vmcs(per_cpu(vmxarea, cpu));
3008                 per_cpu(vmxarea, cpu) = NULL;
3009         }
3010 }
3011
3012 static __init int alloc_kvm_area(void)
3013 {
3014         int cpu;
3015
3016         for_each_possible_cpu(cpu) {
3017                 struct vmcs *vmcs;
3018
3019                 vmcs = alloc_vmcs_cpu(cpu);
3020                 if (!vmcs) {
3021                         free_kvm_area();
3022                         return -ENOMEM;
3023                 }
3024
3025                 per_cpu(vmxarea, cpu) = vmcs;
3026         }
3027         return 0;
3028 }
3029
3030 static __init int hardware_setup(void)
3031 {
3032         if (setup_vmcs_config(&vmcs_config) < 0)
3033                 return -EIO;
3034
3035         if (boot_cpu_has(X86_FEATURE_NX))
3036                 kvm_enable_efer_bits(EFER_NX);
3037
3038         if (!cpu_has_vmx_vpid())
3039                 enable_vpid = 0;
3040         if (!cpu_has_vmx_shadow_vmcs())
3041                 enable_shadow_vmcs = 0;
3042
3043         if (!cpu_has_vmx_ept() ||
3044             !cpu_has_vmx_ept_4levels()) {
3045                 enable_ept = 0;
3046                 enable_unrestricted_guest = 0;
3047                 enable_ept_ad_bits = 0;
3048         }
3049
3050         if (!cpu_has_vmx_ept_ad_bits())
3051                 enable_ept_ad_bits = 0;
3052
3053         if (!cpu_has_vmx_unrestricted_guest())
3054                 enable_unrestricted_guest = 0;
3055
3056         if (!cpu_has_vmx_flexpriority())
3057                 flexpriority_enabled = 0;
3058
3059         if (!cpu_has_vmx_tpr_shadow())
3060                 kvm_x86_ops->update_cr8_intercept = NULL;
3061
3062         if (enable_ept && !cpu_has_vmx_ept_2m_page())
3063                 kvm_disable_largepages();
3064
3065         if (!cpu_has_vmx_ple())
3066                 ple_gap = 0;
3067
3068         if (!cpu_has_vmx_apicv())
3069                 enable_apicv = 0;
3070
3071         if (enable_apicv)
3072                 kvm_x86_ops->update_cr8_intercept = NULL;
3073         else {
3074                 kvm_x86_ops->hwapic_irr_update = NULL;
3075                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3076                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3077         }
3078
3079         if (nested)
3080                 nested_vmx_setup_ctls_msrs();
3081
3082         return alloc_kvm_area();
3083 }
3084
3085 static __exit void hardware_unsetup(void)
3086 {
3087         free_kvm_area();
3088 }
3089
3090 static bool emulation_required(struct kvm_vcpu *vcpu)
3091 {
3092         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3093 }
3094
3095 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3096                 struct kvm_segment *save)
3097 {
3098         if (!emulate_invalid_guest_state) {
3099                 /*
3100                  * CS and SS RPL should be equal during guest entry according
3101                  * to VMX spec, but in reality it is not always so. Since vcpu
3102                  * is in the middle of the transition from real mode to
3103                  * protected mode it is safe to assume that RPL 0 is a good
3104                  * default value.
3105                  */
3106                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3107                         save->selector &= ~SELECTOR_RPL_MASK;
3108                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3109                 save->s = 1;
3110         }
3111         vmx_set_segment(vcpu, save, seg);
3112 }
3113
3114 static void enter_pmode(struct kvm_vcpu *vcpu)
3115 {
3116         unsigned long flags;
3117         struct vcpu_vmx *vmx = to_vmx(vcpu);
3118
3119         /*
3120          * Update real mode segment cache. It may be not up-to-date if sement
3121          * register was written while vcpu was in a guest mode.
3122          */
3123         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3124         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3125         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3126         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3127         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3128         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3129
3130         vmx->rmode.vm86_active = 0;
3131
3132         vmx_segment_cache_clear(vmx);
3133
3134         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3135
3136         flags = vmcs_readl(GUEST_RFLAGS);
3137         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3138         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3139         vmcs_writel(GUEST_RFLAGS, flags);
3140
3141         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3142                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3143
3144         update_exception_bitmap(vcpu);
3145
3146         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3147         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3148         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3149         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3150         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3151         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3152
3153         /* CPL is always 0 when CPU enters protected mode */
3154         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3155         vmx->cpl = 0;
3156 }
3157
3158 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3159 {
3160         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3161         struct kvm_segment var = *save;
3162
3163         var.dpl = 0x3;
3164         if (seg == VCPU_SREG_CS)
3165                 var.type = 0x3;
3166
3167         if (!emulate_invalid_guest_state) {
3168                 var.selector = var.base >> 4;
3169                 var.base = var.base & 0xffff0;
3170                 var.limit = 0xffff;
3171                 var.g = 0;
3172                 var.db = 0;
3173                 var.present = 1;
3174                 var.s = 1;
3175                 var.l = 0;
3176                 var.unusable = 0;
3177                 var.type = 0x3;
3178                 var.avl = 0;
3179                 if (save->base & 0xf)
3180                         printk_once(KERN_WARNING "kvm: segment base is not "
3181                                         "paragraph aligned when entering "
3182                                         "protected mode (seg=%d)", seg);
3183         }
3184
3185         vmcs_write16(sf->selector, var.selector);
3186         vmcs_write32(sf->base, var.base);
3187         vmcs_write32(sf->limit, var.limit);
3188         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3189 }
3190
3191 static void enter_rmode(struct kvm_vcpu *vcpu)
3192 {
3193         unsigned long flags;
3194         struct vcpu_vmx *vmx = to_vmx(vcpu);
3195
3196         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3197         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3198         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3199         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3200         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3201         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3202         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3203
3204         vmx->rmode.vm86_active = 1;
3205
3206         /*
3207          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3208          * vcpu. Warn the user that an update is overdue.
3209          */
3210         if (!vcpu->kvm->arch.tss_addr)
3211                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3212                              "called before entering vcpu\n");
3213
3214         vmx_segment_cache_clear(vmx);
3215
3216         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3217         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3218         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3219
3220         flags = vmcs_readl(GUEST_RFLAGS);
3221         vmx->rmode.save_rflags = flags;
3222
3223         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3224
3225         vmcs_writel(GUEST_RFLAGS, flags);
3226         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3227         update_exception_bitmap(vcpu);
3228
3229         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3230         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3231         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3232         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3233         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3234         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3235
3236         kvm_mmu_reset_context(vcpu);
3237 }
3238
3239 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3240 {
3241         struct vcpu_vmx *vmx = to_vmx(vcpu);
3242         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3243
3244         if (!msr)
3245                 return;
3246
3247         /*
3248          * Force kernel_gs_base reloading before EFER changes, as control
3249          * of this msr depends on is_long_mode().
3250          */
3251         vmx_load_host_state(to_vmx(vcpu));
3252         vcpu->arch.efer = efer;
3253         if (efer & EFER_LMA) {
3254                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3255                 msr->data = efer;
3256         } else {
3257                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3258
3259                 msr->data = efer & ~EFER_LME;
3260         }
3261         setup_msrs(vmx);
3262 }
3263
3264 #ifdef CONFIG_X86_64
3265
3266 static void enter_lmode(struct kvm_vcpu *vcpu)
3267 {
3268         u32 guest_tr_ar;
3269
3270         vmx_segment_cache_clear(to_vmx(vcpu));
3271
3272         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3273         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3274                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3275                                      __func__);
3276                 vmcs_write32(GUEST_TR_AR_BYTES,
3277                              (guest_tr_ar & ~AR_TYPE_MASK)
3278                              | AR_TYPE_BUSY_64_TSS);
3279         }
3280         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3281 }
3282
3283 static void exit_lmode(struct kvm_vcpu *vcpu)
3284 {
3285         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3286         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3287 }
3288
3289 #endif
3290
3291 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3292 {
3293         vpid_sync_context(to_vmx(vcpu));
3294         if (enable_ept) {
3295                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3296                         return;
3297                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3298         }
3299 }
3300
3301 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3302 {
3303         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3304
3305         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3306         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3307 }
3308
3309 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3310 {
3311         if (enable_ept && is_paging(vcpu))
3312                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3313         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3314 }
3315
3316 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3317 {
3318         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3319
3320         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3321         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3322 }
3323
3324 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3325 {
3326         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3327
3328         if (!test_bit(VCPU_EXREG_PDPTR,
3329                       (unsigned long *)&vcpu->arch.regs_dirty))
3330                 return;
3331
3332         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3333                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3334                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3335                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3336                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3337         }
3338 }
3339
3340 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3341 {
3342         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3343
3344         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3345                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3346                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3347                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3348                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3349         }
3350
3351         __set_bit(VCPU_EXREG_PDPTR,
3352                   (unsigned long *)&vcpu->arch.regs_avail);
3353         __set_bit(VCPU_EXREG_PDPTR,
3354                   (unsigned long *)&vcpu->arch.regs_dirty);
3355 }
3356
3357 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3358
3359 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3360                                         unsigned long cr0,
3361                                         struct kvm_vcpu *vcpu)
3362 {
3363         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3364                 vmx_decache_cr3(vcpu);
3365         if (!(cr0 & X86_CR0_PG)) {
3366                 /* From paging/starting to nonpaging */
3367                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3368                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3369                              (CPU_BASED_CR3_LOAD_EXITING |
3370                               CPU_BASED_CR3_STORE_EXITING));
3371                 vcpu->arch.cr0 = cr0;
3372                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3373         } else if (!is_paging(vcpu)) {
3374                 /* From nonpaging to paging */
3375                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3376                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3377                              ~(CPU_BASED_CR3_LOAD_EXITING |
3378                                CPU_BASED_CR3_STORE_EXITING));
3379                 vcpu->arch.cr0 = cr0;
3380                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3381         }
3382
3383         if (!(cr0 & X86_CR0_WP))
3384                 *hw_cr0 &= ~X86_CR0_WP;
3385 }
3386
3387 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3388 {
3389         struct vcpu_vmx *vmx = to_vmx(vcpu);
3390         unsigned long hw_cr0;
3391
3392         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3393         if (enable_unrestricted_guest)
3394                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3395         else {
3396                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3397
3398                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3399                         enter_pmode(vcpu);
3400
3401                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3402                         enter_rmode(vcpu);
3403         }
3404
3405 #ifdef CONFIG_X86_64
3406         if (vcpu->arch.efer & EFER_LME) {
3407                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3408                         enter_lmode(vcpu);
3409                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3410                         exit_lmode(vcpu);
3411         }
3412 #endif
3413
3414         if (enable_ept)
3415                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3416
3417         if (!vcpu->fpu_active)
3418                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3419
3420         vmcs_writel(CR0_READ_SHADOW, cr0);
3421         vmcs_writel(GUEST_CR0, hw_cr0);
3422         vcpu->arch.cr0 = cr0;
3423
3424         /* depends on vcpu->arch.cr0 to be set to a new value */
3425         vmx->emulation_required = emulation_required(vcpu);
3426 }
3427
3428 static u64 construct_eptp(unsigned long root_hpa)
3429 {
3430         u64 eptp;
3431
3432         /* TODO write the value reading from MSR */
3433         eptp = VMX_EPT_DEFAULT_MT |
3434                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3435         if (enable_ept_ad_bits)
3436                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3437         eptp |= (root_hpa & PAGE_MASK);
3438
3439         return eptp;
3440 }
3441
3442 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3443 {
3444         unsigned long guest_cr3;
3445         u64 eptp;
3446
3447         guest_cr3 = cr3;
3448         if (enable_ept) {
3449                 eptp = construct_eptp(cr3);
3450                 vmcs_write64(EPT_POINTER, eptp);
3451                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3452                         guest_cr3 = kvm_read_cr3(vcpu);
3453                 else
3454                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3455                 ept_load_pdptrs(vcpu);
3456         }
3457
3458         vmx_flush_tlb(vcpu);
3459         vmcs_writel(GUEST_CR3, guest_cr3);
3460 }
3461
3462 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3463 {
3464         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3465                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3466
3467         if (cr4 & X86_CR4_VMXE) {
3468                 /*
3469                  * To use VMXON (and later other VMX instructions), a guest
3470                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3471                  * So basically the check on whether to allow nested VMX
3472                  * is here.
3473                  */
3474                 if (!nested_vmx_allowed(vcpu))
3475                         return 1;
3476         }
3477         if (to_vmx(vcpu)->nested.vmxon &&
3478             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3479                 return 1;
3480
3481         vcpu->arch.cr4 = cr4;
3482         if (enable_ept) {
3483                 if (!is_paging(vcpu)) {
3484                         hw_cr4 &= ~X86_CR4_PAE;
3485                         hw_cr4 |= X86_CR4_PSE;
3486                         /*
3487                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3488                          * in hardware. However KVM always uses paging mode to
3489                          * emulate guest non-paging mode with TDP.
3490                          * To emulate this behavior, SMEP/SMAP needs to be
3491                          * manually disabled when guest switches to non-paging
3492                          * mode.
3493                          */
3494                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3495                 } else if (!(cr4 & X86_CR4_PAE)) {
3496                         hw_cr4 &= ~X86_CR4_PAE;
3497                 }
3498         }
3499
3500         vmcs_writel(CR4_READ_SHADOW, cr4);
3501         vmcs_writel(GUEST_CR4, hw_cr4);
3502         return 0;
3503 }
3504
3505 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3506                             struct kvm_segment *var, int seg)
3507 {
3508         struct vcpu_vmx *vmx = to_vmx(vcpu);
3509         u32 ar;
3510
3511         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3512                 *var = vmx->rmode.segs[seg];
3513                 if (seg == VCPU_SREG_TR
3514                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3515                         return;
3516                 var->base = vmx_read_guest_seg_base(vmx, seg);
3517                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3518                 return;
3519         }
3520         var->base = vmx_read_guest_seg_base(vmx, seg);
3521         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3522         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3523         ar = vmx_read_guest_seg_ar(vmx, seg);
3524         var->unusable = (ar >> 16) & 1;
3525         var->type = ar & 15;
3526         var->s = (ar >> 4) & 1;
3527         var->dpl = (ar >> 5) & 3;
3528         /*
3529          * Some userspaces do not preserve unusable property. Since usable
3530          * segment has to be present according to VMX spec we can use present
3531          * property to amend userspace bug by making unusable segment always
3532          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3533          * segment as unusable.
3534          */
3535         var->present = !var->unusable;
3536         var->avl = (ar >> 12) & 1;
3537         var->l = (ar >> 13) & 1;
3538         var->db = (ar >> 14) & 1;
3539         var->g = (ar >> 15) & 1;
3540 }
3541
3542 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3543 {
3544         struct kvm_segment s;
3545
3546         if (to_vmx(vcpu)->rmode.vm86_active) {
3547                 vmx_get_segment(vcpu, &s, seg);
3548                 return s.base;
3549         }
3550         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3551 }
3552
3553 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3554 {
3555         struct vcpu_vmx *vmx = to_vmx(vcpu);
3556
3557         if (!is_protmode(vcpu))
3558                 return 0;
3559
3560         if (!is_long_mode(vcpu)
3561             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3562                 return 3;
3563
3564         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3565                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3566                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3567         }
3568
3569         return vmx->cpl;
3570 }
3571
3572
3573 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3574 {
3575         u32 ar;
3576
3577         if (var->unusable || !var->present)
3578                 ar = 1 << 16;
3579         else {
3580                 ar = var->type & 15;
3581                 ar |= (var->s & 1) << 4;
3582                 ar |= (var->dpl & 3) << 5;
3583                 ar |= (var->present & 1) << 7;
3584                 ar |= (var->avl & 1) << 12;
3585                 ar |= (var->l & 1) << 13;
3586                 ar |= (var->db & 1) << 14;
3587                 ar |= (var->g & 1) << 15;
3588         }
3589
3590         return ar;
3591 }
3592
3593 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3594                             struct kvm_segment *var, int seg)
3595 {
3596         struct vcpu_vmx *vmx = to_vmx(vcpu);
3597         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3598
3599         vmx_segment_cache_clear(vmx);
3600         if (seg == VCPU_SREG_CS)
3601                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3602
3603         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3604                 vmx->rmode.segs[seg] = *var;
3605                 if (seg == VCPU_SREG_TR)
3606                         vmcs_write16(sf->selector, var->selector);
3607                 else if (var->s)
3608                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3609                 goto out;
3610         }
3611
3612         vmcs_writel(sf->base, var->base);
3613         vmcs_write32(sf->limit, var->limit);
3614         vmcs_write16(sf->selector, var->selector);
3615
3616         /*
3617          *   Fix the "Accessed" bit in AR field of segment registers for older
3618          * qemu binaries.
3619          *   IA32 arch specifies that at the time of processor reset the
3620          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3621          * is setting it to 0 in the userland code. This causes invalid guest
3622          * state vmexit when "unrestricted guest" mode is turned on.
3623          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3624          * tree. Newer qemu binaries with that qemu fix would not need this
3625          * kvm hack.
3626          */
3627         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3628                 var->type |= 0x1; /* Accessed */
3629
3630         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3631
3632 out:
3633         vmx->emulation_required |= emulation_required(vcpu);
3634 }
3635
3636 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3637 {
3638         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3639
3640         *db = (ar >> 14) & 1;
3641         *l = (ar >> 13) & 1;
3642 }
3643
3644 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3645 {
3646         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3647         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3648 }
3649
3650 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3651 {
3652         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3653         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3654 }
3655
3656 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3657 {
3658         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3659         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3660 }
3661
3662 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3663 {
3664         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3665         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3666 }
3667
3668 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3669 {
3670         struct kvm_segment var;
3671         u32 ar;
3672
3673         vmx_get_segment(vcpu, &var, seg);
3674         var.dpl = 0x3;
3675         if (seg == VCPU_SREG_CS)
3676                 var.type = 0x3;
3677         ar = vmx_segment_access_rights(&var);
3678
3679         if (var.base != (var.selector << 4))
3680                 return false;
3681         if (var.limit != 0xffff)
3682                 return false;
3683         if (ar != 0xf3)
3684                 return false;
3685
3686         return true;
3687 }
3688
3689 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3690 {
3691         struct kvm_segment cs;
3692         unsigned int cs_rpl;
3693
3694         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3695         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3696
3697         if (cs.unusable)
3698                 return false;
3699         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3700                 return false;
3701         if (!cs.s)
3702                 return false;
3703         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3704                 if (cs.dpl > cs_rpl)
3705                         return false;
3706         } else {
3707                 if (cs.dpl != cs_rpl)
3708                         return false;
3709         }
3710         if (!cs.present)
3711                 return false;
3712
3713         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3714         return true;
3715 }
3716
3717 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3718 {
3719         struct kvm_segment ss;
3720         unsigned int ss_rpl;
3721
3722         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3723         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3724
3725         if (ss.unusable)
3726                 return true;
3727         if (ss.type != 3 && ss.type != 7)
3728                 return false;
3729         if (!ss.s)
3730                 return false;
3731         if (ss.dpl != ss_rpl) /* DPL != RPL */
3732                 return false;
3733         if (!ss.present)
3734                 return false;
3735
3736         return true;
3737 }
3738
3739 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3740 {
3741         struct kvm_segment var;
3742         unsigned int rpl;
3743
3744         vmx_get_segment(vcpu, &var, seg);
3745         rpl = var.selector & SELECTOR_RPL_MASK;
3746
3747         if (var.unusable)
3748                 return true;
3749         if (!var.s)
3750                 return false;
3751         if (!var.present)
3752                 return false;
3753         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3754                 if (var.dpl < rpl) /* DPL < RPL */
3755                         return false;
3756         }
3757
3758         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3759          * rights flags
3760          */
3761         return true;
3762 }
3763
3764 static bool tr_valid(struct kvm_vcpu *vcpu)
3765 {
3766         struct kvm_segment tr;
3767
3768         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3769
3770         if (tr.unusable)
3771                 return false;
3772         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3773                 return false;
3774         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3775                 return false;
3776         if (!tr.present)
3777                 return false;
3778
3779         return true;
3780 }
3781
3782 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3783 {
3784         struct kvm_segment ldtr;
3785
3786         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3787
3788         if (ldtr.unusable)
3789                 return true;
3790         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3791                 return false;
3792         if (ldtr.type != 2)
3793                 return false;
3794         if (!ldtr.present)
3795                 return false;
3796
3797         return true;
3798 }
3799
3800 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3801 {
3802         struct kvm_segment cs, ss;
3803
3804         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3805         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3806
3807         return ((cs.selector & SELECTOR_RPL_MASK) ==
3808                  (ss.selector & SELECTOR_RPL_MASK));
3809 }
3810
3811 /*
3812  * Check if guest state is valid. Returns true if valid, false if
3813  * not.
3814  * We assume that registers are always usable
3815  */
3816 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3817 {
3818         if (enable_unrestricted_guest)
3819                 return true;
3820
3821         /* real mode guest state checks */
3822         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3823                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3824                         return false;
3825                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3826                         return false;
3827                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3828                         return false;
3829                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3830                         return false;
3831                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3832                         return false;
3833                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3834                         return false;
3835         } else {
3836         /* protected mode guest state checks */
3837                 if (!cs_ss_rpl_check(vcpu))
3838                         return false;
3839                 if (!code_segment_valid(vcpu))
3840                         return false;
3841                 if (!stack_segment_valid(vcpu))
3842                         return false;
3843                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3844                         return false;
3845                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3846                         return false;
3847                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3848                         return false;
3849                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3850                         return false;
3851                 if (!tr_valid(vcpu))
3852                         return false;
3853                 if (!ldtr_valid(vcpu))
3854                         return false;
3855         }
3856         /* TODO:
3857          * - Add checks on RIP
3858          * - Add checks on RFLAGS
3859          */
3860
3861         return true;
3862 }
3863
3864 static int init_rmode_tss(struct kvm *kvm)
3865 {
3866         gfn_t fn;
3867         u16 data = 0;
3868         int r, idx, ret = 0;
3869
3870         idx = srcu_read_lock(&kvm->srcu);
3871         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3872         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3873         if (r < 0)
3874                 goto out;
3875         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3876         r = kvm_write_guest_page(kvm, fn++, &data,
3877                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3878         if (r < 0)
3879                 goto out;
3880         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3881         if (r < 0)
3882                 goto out;
3883         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3884         if (r < 0)
3885                 goto out;
3886         data = ~0;
3887         r = kvm_write_guest_page(kvm, fn, &data,
3888                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3889                                  sizeof(u8));
3890         if (r < 0)
3891                 goto out;
3892
3893         ret = 1;
3894 out:
3895         srcu_read_unlock(&kvm->srcu, idx);
3896         return ret;
3897 }
3898
3899 static int init_rmode_identity_map(struct kvm *kvm)
3900 {
3901         int i, idx, r, ret;
3902         pfn_t identity_map_pfn;
3903         u32 tmp;
3904
3905         if (!enable_ept)
3906                 return 1;
3907         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3908                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3909                         "haven't been allocated!\n");
3910                 return 0;
3911         }
3912         if (likely(kvm->arch.ept_identity_pagetable_done))
3913                 return 1;
3914         ret = 0;
3915         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3916         idx = srcu_read_lock(&kvm->srcu);
3917         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3918         if (r < 0)
3919                 goto out;
3920         /* Set up identity-mapping pagetable for EPT in real mode */
3921         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3922                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3923                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3924                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3925                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3926                 if (r < 0)
3927                         goto out;
3928         }
3929         kvm->arch.ept_identity_pagetable_done = true;
3930         ret = 1;
3931 out:
3932         srcu_read_unlock(&kvm->srcu, idx);
3933         return ret;
3934 }
3935
3936 static void seg_setup(int seg)
3937 {
3938         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3939         unsigned int ar;
3940
3941         vmcs_write16(sf->selector, 0);
3942         vmcs_writel(sf->base, 0);
3943         vmcs_write32(sf->limit, 0xffff);
3944         ar = 0x93;
3945         if (seg == VCPU_SREG_CS)
3946                 ar |= 0x08; /* code segment */
3947
3948         vmcs_write32(sf->ar_bytes, ar);
3949 }
3950
3951 static int alloc_apic_access_page(struct kvm *kvm)
3952 {
3953         struct page *page;
3954         struct kvm_userspace_memory_region kvm_userspace_mem;
3955         int r = 0;
3956
3957         mutex_lock(&kvm->slots_lock);
3958         if (kvm->arch.apic_access_page)
3959                 goto out;
3960         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3961         kvm_userspace_mem.flags = 0;
3962         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3963         kvm_userspace_mem.memory_size = PAGE_SIZE;
3964         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3965         if (r)
3966                 goto out;
3967
3968         page = gfn_to_page(kvm, 0xfee00);
3969         if (is_error_page(page)) {
3970                 r = -EFAULT;
3971                 goto out;
3972         }
3973
3974         kvm->arch.apic_access_page = page;
3975 out:
3976         mutex_unlock(&kvm->slots_lock);
3977         return r;
3978 }
3979
3980 static int alloc_identity_pagetable(struct kvm *kvm)
3981 {
3982         struct page *page;
3983         struct kvm_userspace_memory_region kvm_userspace_mem;
3984         int r = 0;
3985
3986         mutex_lock(&kvm->slots_lock);
3987         if (kvm->arch.ept_identity_pagetable)
3988                 goto out;
3989         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3990         kvm_userspace_mem.flags = 0;
3991         kvm_userspace_mem.guest_phys_addr =
3992                 kvm->arch.ept_identity_map_addr;
3993         kvm_userspace_mem.memory_size = PAGE_SIZE;
3994         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3995         if (r)
3996                 goto out;
3997
3998         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3999         if (is_error_page(page)) {
4000                 r = -EFAULT;
4001                 goto out;
4002         }
4003
4004         kvm->arch.ept_identity_pagetable = page;
4005 out:
4006         mutex_unlock(&kvm->slots_lock);
4007         return r;
4008 }
4009
4010 static void allocate_vpid(struct vcpu_vmx *vmx)
4011 {
4012         int vpid;
4013
4014         vmx->vpid = 0;
4015         if (!enable_vpid)
4016                 return;
4017         spin_lock(&vmx_vpid_lock);
4018         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4019         if (vpid < VMX_NR_VPIDS) {
4020                 vmx->vpid = vpid;
4021                 __set_bit(vpid, vmx_vpid_bitmap);
4022         }
4023         spin_unlock(&vmx_vpid_lock);
4024 }
4025
4026 static void free_vpid(struct vcpu_vmx *vmx)
4027 {
4028         if (!enable_vpid)
4029                 return;
4030         spin_lock(&vmx_vpid_lock);
4031         if (vmx->vpid != 0)
4032                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4033         spin_unlock(&vmx_vpid_lock);
4034 }
4035
4036 #define MSR_TYPE_R      1
4037 #define MSR_TYPE_W      2
4038 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4039                                                 u32 msr, int type)
4040 {
4041         int f = sizeof(unsigned long);
4042
4043         if (!cpu_has_vmx_msr_bitmap())
4044                 return;
4045
4046         /*
4047          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4048          * have the write-low and read-high bitmap offsets the wrong way round.
4049          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4050          */
4051         if (msr <= 0x1fff) {
4052                 if (type & MSR_TYPE_R)
4053                         /* read-low */
4054                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4055
4056                 if (type & MSR_TYPE_W)
4057                         /* write-low */
4058                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4059
4060         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4061                 msr &= 0x1fff;
4062                 if (type & MSR_TYPE_R)
4063                         /* read-high */
4064                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4065
4066                 if (type & MSR_TYPE_W)
4067                         /* write-high */
4068                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4069
4070         }
4071 }
4072
4073 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4074                                                 u32 msr, int type)
4075 {
4076         int f = sizeof(unsigned long);
4077
4078         if (!cpu_has_vmx_msr_bitmap())
4079                 return;
4080
4081         /*
4082          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4083          * have the write-low and read-high bitmap offsets the wrong way round.
4084          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4085          */
4086         if (msr <= 0x1fff) {
4087                 if (type & MSR_TYPE_R)
4088                         /* read-low */
4089                         __set_bit(msr, msr_bitmap + 0x000 / f);
4090
4091                 if (type & MSR_TYPE_W)
4092                         /* write-low */
4093                         __set_bit(msr, msr_bitmap + 0x800 / f);
4094
4095         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4096                 msr &= 0x1fff;
4097                 if (type & MSR_TYPE_R)
4098                         /* read-high */
4099                         __set_bit(msr, msr_bitmap + 0x400 / f);
4100
4101                 if (type & MSR_TYPE_W)
4102                         /* write-high */
4103                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4104
4105         }
4106 }
4107
4108 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4109 {
4110         if (!longmode_only)
4111                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4112                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4113         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4114                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4115 }
4116
4117 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4118 {
4119         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4120                         msr, MSR_TYPE_R);
4121         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4122                         msr, MSR_TYPE_R);
4123 }
4124
4125 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4126 {
4127         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4128                         msr, MSR_TYPE_R);
4129         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4130                         msr, MSR_TYPE_R);
4131 }
4132
4133 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4134 {
4135         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4136                         msr, MSR_TYPE_W);
4137         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4138                         msr, MSR_TYPE_W);
4139 }
4140
4141 static int vmx_vm_has_apicv(struct kvm *kvm)
4142 {
4143         return enable_apicv && irqchip_in_kernel(kvm);
4144 }
4145
4146 /*
4147  * Send interrupt to vcpu via posted interrupt way.
4148  * 1. If target vcpu is running(non-root mode), send posted interrupt
4149  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4150  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4151  * interrupt from PIR in next vmentry.
4152  */
4153 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4154 {
4155         struct vcpu_vmx *vmx = to_vmx(vcpu);
4156         int r;
4157
4158         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4159                 return;
4160
4161         r = pi_test_and_set_on(&vmx->pi_desc);
4162         kvm_make_request(KVM_REQ_EVENT, vcpu);
4163 #ifdef CONFIG_SMP
4164         if (!r && (vcpu->mode == IN_GUEST_MODE))
4165                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4166                                 POSTED_INTR_VECTOR);
4167         else
4168 #endif
4169                 kvm_vcpu_kick(vcpu);
4170 }
4171
4172 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4173 {
4174         struct vcpu_vmx *vmx = to_vmx(vcpu);
4175
4176         if (!pi_test_and_clear_on(&vmx->pi_desc))
4177                 return;
4178
4179         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4180 }
4181
4182 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4183 {
4184         return;
4185 }
4186
4187 /*
4188  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4189  * will not change in the lifetime of the guest.
4190  * Note that host-state that does change is set elsewhere. E.g., host-state
4191  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4192  */
4193 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4194 {
4195         u32 low32, high32;
4196         unsigned long tmpl;
4197         struct desc_ptr dt;
4198
4199         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4200         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4201         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4202
4203         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4204 #ifdef CONFIG_X86_64
4205         /*
4206          * Load null selectors, so we can avoid reloading them in
4207          * __vmx_load_host_state(), in case userspace uses the null selectors
4208          * too (the expected case).
4209          */
4210         vmcs_write16(HOST_DS_SELECTOR, 0);
4211         vmcs_write16(HOST_ES_SELECTOR, 0);
4212 #else
4213         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4214         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4215 #endif
4216         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4217         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4218
4219         native_store_idt(&dt);
4220         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4221         vmx->host_idt_base = dt.address;
4222
4223         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4224
4225         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4226         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4227         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4228         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4229
4230         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4231                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4232                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4233         }
4234 }
4235
4236 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4237 {
4238         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4239         if (enable_ept)
4240                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4241         if (is_guest_mode(&vmx->vcpu))
4242                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4243                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4244         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4245 }
4246
4247 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4248 {
4249         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4250
4251         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4252                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4253         return pin_based_exec_ctrl;
4254 }
4255
4256 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4257 {
4258         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4259
4260         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4261                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4262
4263         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4264                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4265 #ifdef CONFIG_X86_64
4266                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4267                                 CPU_BASED_CR8_LOAD_EXITING;
4268 #endif
4269         }
4270         if (!enable_ept)
4271                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4272                                 CPU_BASED_CR3_LOAD_EXITING  |
4273                                 CPU_BASED_INVLPG_EXITING;
4274         return exec_control;
4275 }
4276
4277 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4278 {
4279         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4280         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4281                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4282         if (vmx->vpid == 0)
4283                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4284         if (!enable_ept) {
4285                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4286                 enable_unrestricted_guest = 0;
4287                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4288                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4289         }
4290         if (!enable_unrestricted_guest)
4291                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4292         if (!ple_gap)
4293                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4294         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4295                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4296                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4297         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4298         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4299            (handle_vmptrld).
4300            We can NOT enable shadow_vmcs here because we don't have yet
4301            a current VMCS12
4302         */
4303         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4304         return exec_control;
4305 }
4306
4307 static void ept_set_mmio_spte_mask(void)
4308 {
4309         /*
4310          * EPT Misconfigurations can be generated if the value of bits 2:0
4311          * of an EPT paging-structure entry is 110b (write/execute).
4312          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4313          * spte.
4314          */
4315         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4316 }
4317
4318 /*
4319  * Sets up the vmcs for emulated real mode.
4320  */
4321 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4322 {
4323 #ifdef CONFIG_X86_64
4324         unsigned long a;
4325 #endif
4326         int i;
4327
4328         /* I/O */
4329         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4330         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4331
4332         if (enable_shadow_vmcs) {
4333                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4334                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4335         }
4336         if (cpu_has_vmx_msr_bitmap())
4337                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4338
4339         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4340
4341         /* Control */
4342         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4343
4344         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4345
4346         if (cpu_has_secondary_exec_ctrls()) {
4347                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4348                                 vmx_secondary_exec_control(vmx));
4349         }
4350
4351         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4352                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4353                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4354                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4355                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4356
4357                 vmcs_write16(GUEST_INTR_STATUS, 0);
4358
4359                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4360                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4361         }
4362
4363         if (ple_gap) {
4364                 vmcs_write32(PLE_GAP, ple_gap);
4365                 vmcs_write32(PLE_WINDOW, ple_window);
4366         }
4367
4368         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4369         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4370         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4371
4372         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4373         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4374         vmx_set_constant_host_state(vmx);
4375 #ifdef CONFIG_X86_64
4376         rdmsrl(MSR_FS_BASE, a);
4377         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4378         rdmsrl(MSR_GS_BASE, a);
4379         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4380 #else
4381         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4382         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4383 #endif
4384
4385         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4386         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4387         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4388         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4389         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4390
4391         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4392                 u32 msr_low, msr_high;
4393                 u64 host_pat;
4394                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4395                 host_pat = msr_low | ((u64) msr_high << 32);
4396                 /* Write the default value follow host pat */
4397                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4398                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4399                 vmx->vcpu.arch.pat = host_pat;
4400         }
4401
4402         for (i = 0; i < NR_VMX_MSR; ++i) {
4403                 u32 index = vmx_msr_index[i];
4404                 u32 data_low, data_high;
4405                 int j = vmx->nmsrs;
4406
4407                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4408                         continue;
4409                 if (wrmsr_safe(index, data_low, data_high) < 0)
4410                         continue;
4411                 vmx->guest_msrs[j].index = i;
4412                 vmx->guest_msrs[j].data = 0;
4413                 vmx->guest_msrs[j].mask = -1ull;
4414                 ++vmx->nmsrs;
4415         }
4416
4417
4418         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4419
4420         /* 22.2.1, 20.8.1 */
4421         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4422
4423         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4424         set_cr4_guest_host_mask(vmx);
4425
4426         return 0;
4427 }
4428
4429 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4430 {
4431         struct vcpu_vmx *vmx = to_vmx(vcpu);
4432         struct msr_data apic_base_msr;
4433
4434         vmx->rmode.vm86_active = 0;
4435
4436         vmx->soft_vnmi_blocked = 0;
4437
4438         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4439         kvm_set_cr8(&vmx->vcpu, 0);
4440         apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4441         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4442                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4443         apic_base_msr.host_initiated = true;
4444         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4445
4446         vmx_segment_cache_clear(vmx);
4447
4448         seg_setup(VCPU_SREG_CS);
4449         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4450         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4451
4452         seg_setup(VCPU_SREG_DS);
4453         seg_setup(VCPU_SREG_ES);
4454         seg_setup(VCPU_SREG_FS);
4455         seg_setup(VCPU_SREG_GS);
4456         seg_setup(VCPU_SREG_SS);
4457
4458         vmcs_write16(GUEST_TR_SELECTOR, 0);
4459         vmcs_writel(GUEST_TR_BASE, 0);
4460         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4461         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4462
4463         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4464         vmcs_writel(GUEST_LDTR_BASE, 0);
4465         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4466         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4467
4468         vmcs_write32(GUEST_SYSENTER_CS, 0);
4469         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4470         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4471
4472         vmcs_writel(GUEST_RFLAGS, 0x02);
4473         kvm_rip_write(vcpu, 0xfff0);
4474
4475         vmcs_writel(GUEST_GDTR_BASE, 0);
4476         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4477
4478         vmcs_writel(GUEST_IDTR_BASE, 0);
4479         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4480
4481         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4482         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4483         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4484
4485         /* Special registers */
4486         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4487
4488         setup_msrs(vmx);
4489
4490         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4491
4492         if (cpu_has_vmx_tpr_shadow()) {
4493                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4494                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4495                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4496                                      __pa(vmx->vcpu.arch.apic->regs));
4497                 vmcs_write32(TPR_THRESHOLD, 0);
4498         }
4499
4500         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4501                 vmcs_write64(APIC_ACCESS_ADDR,
4502                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4503
4504         if (vmx_vm_has_apicv(vcpu->kvm))
4505                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4506
4507         if (vmx->vpid != 0)
4508                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4509
4510         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4511         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4512         vmx_set_cr4(&vmx->vcpu, 0);
4513         vmx_set_efer(&vmx->vcpu, 0);
4514         vmx_fpu_activate(&vmx->vcpu);
4515         update_exception_bitmap(&vmx->vcpu);
4516
4517         vpid_sync_context(vmx);
4518 }
4519
4520 /*
4521  * In nested virtualization, check if L1 asked to exit on external interrupts.
4522  * For most existing hypervisors, this will always return true.
4523  */
4524 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4525 {
4526         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4527                 PIN_BASED_EXT_INTR_MASK;
4528 }
4529
4530 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4531 {
4532         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4533                 PIN_BASED_NMI_EXITING;
4534 }
4535
4536 static void enable_irq_window(struct kvm_vcpu *vcpu)
4537 {
4538         u32 cpu_based_vm_exec_control;
4539
4540         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4541         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4542         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4543 }
4544
4545 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4546 {
4547         u32 cpu_based_vm_exec_control;
4548
4549         if (!cpu_has_virtual_nmis() ||
4550             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4551                 enable_irq_window(vcpu);
4552                 return;
4553         }
4554
4555         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4556         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4557         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4558 }
4559
4560 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4561 {
4562         struct vcpu_vmx *vmx = to_vmx(vcpu);
4563         uint32_t intr;
4564         int irq = vcpu->arch.interrupt.nr;
4565
4566         trace_kvm_inj_virq(irq);
4567
4568         ++vcpu->stat.irq_injections;
4569         if (vmx->rmode.vm86_active) {
4570                 int inc_eip = 0;
4571                 if (vcpu->arch.interrupt.soft)
4572                         inc_eip = vcpu->arch.event_exit_inst_len;
4573                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4574                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4575                 return;
4576         }
4577         intr = irq | INTR_INFO_VALID_MASK;
4578         if (vcpu->arch.interrupt.soft) {
4579                 intr |= INTR_TYPE_SOFT_INTR;
4580                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4581                              vmx->vcpu.arch.event_exit_inst_len);
4582         } else
4583                 intr |= INTR_TYPE_EXT_INTR;
4584         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4585 }
4586
4587 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4588 {
4589         struct vcpu_vmx *vmx = to_vmx(vcpu);
4590
4591         if (is_guest_mode(vcpu))
4592                 return;
4593
4594         if (!cpu_has_virtual_nmis()) {
4595                 /*
4596                  * Tracking the NMI-blocked state in software is built upon
4597                  * finding the next open IRQ window. This, in turn, depends on
4598                  * well-behaving guests: They have to keep IRQs disabled at
4599                  * least as long as the NMI handler runs. Otherwise we may
4600                  * cause NMI nesting, maybe breaking the guest. But as this is
4601                  * highly unlikely, we can live with the residual risk.
4602                  */
4603                 vmx->soft_vnmi_blocked = 1;
4604                 vmx->vnmi_blocked_time = 0;
4605         }
4606
4607         ++vcpu->stat.nmi_injections;
4608         vmx->nmi_known_unmasked = false;
4609         if (vmx->rmode.vm86_active) {
4610                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4611                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4612                 return;
4613         }
4614         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4615                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4616 }
4617
4618 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4619 {
4620         if (!cpu_has_virtual_nmis())
4621                 return to_vmx(vcpu)->soft_vnmi_blocked;
4622         if (to_vmx(vcpu)->nmi_known_unmasked)
4623                 return false;
4624         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4625 }
4626
4627 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4628 {
4629         struct vcpu_vmx *vmx = to_vmx(vcpu);
4630
4631         if (!cpu_has_virtual_nmis()) {
4632                 if (vmx->soft_vnmi_blocked != masked) {
4633                         vmx->soft_vnmi_blocked = masked;
4634                         vmx->vnmi_blocked_time = 0;
4635                 }
4636         } else {
4637                 vmx->nmi_known_unmasked = !masked;
4638                 if (masked)
4639                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4640                                       GUEST_INTR_STATE_NMI);
4641                 else
4642                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4643                                         GUEST_INTR_STATE_NMI);
4644         }
4645 }
4646
4647 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4648 {
4649         if (to_vmx(vcpu)->nested.nested_run_pending)
4650                 return 0;
4651
4652         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4653                 return 0;
4654
4655         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4656                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4657                    | GUEST_INTR_STATE_NMI));
4658 }
4659
4660 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4661 {
4662         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4663                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4664                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4665                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4666 }
4667
4668 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4669 {
4670         int ret;
4671         struct kvm_userspace_memory_region tss_mem = {
4672                 .slot = TSS_PRIVATE_MEMSLOT,
4673                 .guest_phys_addr = addr,
4674                 .memory_size = PAGE_SIZE * 3,
4675                 .flags = 0,
4676         };
4677
4678         ret = kvm_set_memory_region(kvm, &tss_mem);
4679         if (ret)
4680                 return ret;
4681         kvm->arch.tss_addr = addr;
4682         if (!init_rmode_tss(kvm))
4683                 return  -ENOMEM;
4684
4685         return 0;
4686 }
4687
4688 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4689 {
4690         switch (vec) {
4691         case BP_VECTOR:
4692                 /*
4693                  * Update instruction length as we may reinject the exception
4694                  * from user space while in guest debugging mode.
4695                  */
4696                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4697                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4698                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4699                         return false;
4700                 /* fall through */
4701         case DB_VECTOR:
4702                 if (vcpu->guest_debug &
4703                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4704                         return false;
4705                 /* fall through */
4706         case DE_VECTOR:
4707         case OF_VECTOR:
4708         case BR_VECTOR:
4709         case UD_VECTOR:
4710         case DF_VECTOR:
4711         case SS_VECTOR:
4712         case GP_VECTOR:
4713         case MF_VECTOR:
4714                 return true;
4715         break;
4716         }
4717         return false;
4718 }
4719
4720 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4721                                   int vec, u32 err_code)
4722 {
4723         /*
4724          * Instruction with address size override prefix opcode 0x67
4725          * Cause the #SS fault with 0 error code in VM86 mode.
4726          */
4727         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4728                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4729                         if (vcpu->arch.halt_request) {
4730                                 vcpu->arch.halt_request = 0;
4731                                 return kvm_emulate_halt(vcpu);
4732                         }
4733                         return 1;
4734                 }
4735                 return 0;
4736         }
4737
4738         /*
4739          * Forward all other exceptions that are valid in real mode.
4740          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4741          *        the required debugging infrastructure rework.
4742          */
4743         kvm_queue_exception(vcpu, vec);
4744         return 1;
4745 }
4746
4747 /*
4748  * Trigger machine check on the host. We assume all the MSRs are already set up
4749  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4750  * We pass a fake environment to the machine check handler because we want
4751  * the guest to be always treated like user space, no matter what context
4752  * it used internally.
4753  */
4754 static void kvm_machine_check(void)
4755 {
4756 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4757         struct pt_regs regs = {
4758                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4759                 .flags = X86_EFLAGS_IF,
4760         };
4761
4762         do_machine_check(&regs, 0);
4763 #endif
4764 }
4765
4766 static int handle_machine_check(struct kvm_vcpu *vcpu)
4767 {
4768         /* already handled by vcpu_run */
4769         return 1;
4770 }
4771
4772 static int handle_exception(struct kvm_vcpu *vcpu)
4773 {
4774         struct vcpu_vmx *vmx = to_vmx(vcpu);
4775         struct kvm_run *kvm_run = vcpu->run;
4776         u32 intr_info, ex_no, error_code;
4777         unsigned long cr2, rip, dr6;
4778         u32 vect_info;
4779         enum emulation_result er;
4780
4781         vect_info = vmx->idt_vectoring_info;
4782         intr_info = vmx->exit_intr_info;
4783
4784         if (is_machine_check(intr_info))
4785                 return handle_machine_check(vcpu);
4786
4787         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4788                 return 1;  /* already handled by vmx_vcpu_run() */
4789
4790         if (is_no_device(intr_info)) {
4791                 vmx_fpu_activate(vcpu);
4792                 return 1;
4793         }
4794
4795         if (is_invalid_opcode(intr_info)) {
4796                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4797                 if (er != EMULATE_DONE)
4798                         kvm_queue_exception(vcpu, UD_VECTOR);
4799                 return 1;
4800         }
4801
4802         error_code = 0;
4803         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4804                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4805
4806         /*
4807          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4808          * MMIO, it is better to report an internal error.
4809          * See the comments in vmx_handle_exit.
4810          */
4811         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4812             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4813                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4814                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4815                 vcpu->run->internal.ndata = 2;
4816                 vcpu->run->internal.data[0] = vect_info;
4817                 vcpu->run->internal.data[1] = intr_info;
4818                 return 0;
4819         }
4820
4821         if (is_page_fault(intr_info)) {
4822                 /* EPT won't cause page fault directly */
4823                 BUG_ON(enable_ept);
4824                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4825                 trace_kvm_page_fault(cr2, error_code);
4826
4827                 if (kvm_event_needs_reinjection(vcpu))
4828                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4829                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4830         }
4831
4832         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4833
4834         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4835                 return handle_rmode_exception(vcpu, ex_no, error_code);
4836
4837         switch (ex_no) {
4838         case DB_VECTOR:
4839                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4840                 if (!(vcpu->guest_debug &
4841                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4842                         vcpu->arch.dr6 &= ~15;
4843                         vcpu->arch.dr6 |= dr6;
4844                         kvm_queue_exception(vcpu, DB_VECTOR);
4845                         return 1;
4846                 }
4847                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4848                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4849                 /* fall through */
4850         case BP_VECTOR:
4851                 /*
4852                  * Update instruction length as we may reinject #BP from
4853                  * user space while in guest debugging mode. Reading it for
4854                  * #DB as well causes no harm, it is not used in that case.
4855                  */
4856                 vmx->vcpu.arch.event_exit_inst_len =
4857                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4858                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4859                 rip = kvm_rip_read(vcpu);
4860                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4861                 kvm_run->debug.arch.exception = ex_no;
4862                 break;
4863         default:
4864                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4865                 kvm_run->ex.exception = ex_no;
4866                 kvm_run->ex.error_code = error_code;
4867                 break;
4868         }
4869         return 0;
4870 }
4871
4872 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4873 {
4874         ++vcpu->stat.irq_exits;
4875         return 1;
4876 }
4877
4878 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4879 {
4880         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4881         return 0;
4882 }
4883
4884 static int handle_io(struct kvm_vcpu *vcpu)
4885 {
4886         unsigned long exit_qualification;
4887         int size, in, string;
4888         unsigned port;
4889
4890         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4891         string = (exit_qualification & 16) != 0;
4892         in = (exit_qualification & 8) != 0;
4893
4894         ++vcpu->stat.io_exits;
4895
4896         if (string || in)
4897                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4898
4899         port = exit_qualification >> 16;
4900         size = (exit_qualification & 7) + 1;
4901         skip_emulated_instruction(vcpu);
4902
4903         return kvm_fast_pio_out(vcpu, size, port);
4904 }
4905
4906 static void
4907 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4908 {
4909         /*
4910          * Patch in the VMCALL instruction:
4911          */
4912         hypercall[0] = 0x0f;
4913         hypercall[1] = 0x01;
4914         hypercall[2] = 0xc1;
4915 }
4916
4917 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4918 {
4919         unsigned long always_on = VMXON_CR0_ALWAYSON;
4920
4921         if (nested_vmx_secondary_ctls_high &
4922                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4923             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4924                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4925         return (val & always_on) == always_on;
4926 }
4927
4928 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4929 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4930 {
4931         if (is_guest_mode(vcpu)) {
4932                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4933                 unsigned long orig_val = val;
4934
4935                 /*
4936                  * We get here when L2 changed cr0 in a way that did not change
4937                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4938                  * but did change L0 shadowed bits. So we first calculate the
4939                  * effective cr0 value that L1 would like to write into the
4940                  * hardware. It consists of the L2-owned bits from the new
4941                  * value combined with the L1-owned bits from L1's guest_cr0.
4942                  */
4943                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4944                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4945
4946                 if (!nested_cr0_valid(vmcs12, val))
4947                         return 1;
4948
4949                 if (kvm_set_cr0(vcpu, val))
4950                         return 1;
4951                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4952                 return 0;
4953         } else {
4954                 if (to_vmx(vcpu)->nested.vmxon &&
4955                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4956                         return 1;
4957                 return kvm_set_cr0(vcpu, val);
4958         }
4959 }
4960
4961 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4962 {
4963         if (is_guest_mode(vcpu)) {
4964                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4965                 unsigned long orig_val = val;
4966
4967                 /* analogously to handle_set_cr0 */
4968                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4969                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4970                 if (kvm_set_cr4(vcpu, val))
4971                         return 1;
4972                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4973                 return 0;
4974         } else
4975                 return kvm_set_cr4(vcpu, val);
4976 }
4977
4978 /* called to set cr0 as approriate for clts instruction exit. */
4979 static void handle_clts(struct kvm_vcpu *vcpu)
4980 {
4981         if (is_guest_mode(vcpu)) {
4982                 /*
4983                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4984                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4985                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4986                  */
4987                 vmcs_writel(CR0_READ_SHADOW,
4988                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4989                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4990         } else
4991                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4992 }
4993
4994 static int handle_cr(struct kvm_vcpu *vcpu)
4995 {
4996         unsigned long exit_qualification, val;
4997         int cr;
4998         int reg;
4999         int err;
5000
5001         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5002         cr = exit_qualification & 15;
5003         reg = (exit_qualification >> 8) & 15;
5004         switch ((exit_qualification >> 4) & 3) {
5005         case 0: /* mov to cr */
5006                 val = kvm_register_read(vcpu, reg);
5007                 trace_kvm_cr_write(cr, val);
5008                 switch (cr) {
5009                 case 0:
5010                         err = handle_set_cr0(vcpu, val);
5011                         kvm_complete_insn_gp(vcpu, err);
5012                         return 1;
5013                 case 3:
5014                         err = kvm_set_cr3(vcpu, val);
5015                         kvm_complete_insn_gp(vcpu, err);
5016                         return 1;
5017                 case 4:
5018                         err = handle_set_cr4(vcpu, val);
5019                         kvm_complete_insn_gp(vcpu, err);
5020                         return 1;
5021                 case 8: {
5022                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5023                                 u8 cr8 = kvm_register_read(vcpu, reg);
5024                                 err = kvm_set_cr8(vcpu, cr8);
5025                                 kvm_complete_insn_gp(vcpu, err);
5026                                 if (irqchip_in_kernel(vcpu->kvm))
5027                                         return 1;
5028                                 if (cr8_prev <= cr8)
5029                                         return 1;
5030                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5031                                 return 0;
5032                         }
5033                 }
5034                 break;
5035         case 2: /* clts */
5036                 handle_clts(vcpu);
5037                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5038                 skip_emulated_instruction(vcpu);
5039                 vmx_fpu_activate(vcpu);
5040                 return 1;
5041         case 1: /*mov from cr*/
5042                 switch (cr) {
5043                 case 3:
5044                         val = kvm_read_cr3(vcpu);
5045                         kvm_register_write(vcpu, reg, val);
5046                         trace_kvm_cr_read(cr, val);
5047                         skip_emulated_instruction(vcpu);
5048                         return 1;
5049                 case 8:
5050                         val = kvm_get_cr8(vcpu);
5051                         kvm_register_write(vcpu, reg, val);
5052                         trace_kvm_cr_read(cr, val);
5053                         skip_emulated_instruction(vcpu);
5054                         return 1;
5055                 }
5056                 break;
5057         case 3: /* lmsw */
5058                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5059                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5060                 kvm_lmsw(vcpu, val);
5061
5062                 skip_emulated_instruction(vcpu);
5063                 return 1;
5064         default:
5065                 break;
5066         }
5067         vcpu->run->exit_reason = 0;
5068         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5069                (int)(exit_qualification >> 4) & 3, cr);
5070         return 0;
5071 }
5072
5073 static int handle_dr(struct kvm_vcpu *vcpu)
5074 {
5075         unsigned long exit_qualification;
5076         int dr, reg;
5077
5078         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5079         if (!kvm_require_cpl(vcpu, 0))
5080                 return 1;
5081         dr = vmcs_readl(GUEST_DR7);
5082         if (dr & DR7_GD) {
5083                 /*
5084                  * As the vm-exit takes precedence over the debug trap, we
5085                  * need to emulate the latter, either for the host or the
5086                  * guest debugging itself.
5087                  */
5088                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5089                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5090                         vcpu->run->debug.arch.dr7 = dr;
5091                         vcpu->run->debug.arch.pc =
5092                                 vmcs_readl(GUEST_CS_BASE) +
5093                                 vmcs_readl(GUEST_RIP);
5094                         vcpu->run->debug.arch.exception = DB_VECTOR;
5095                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5096                         return 0;
5097                 } else {
5098                         vcpu->arch.dr7 &= ~DR7_GD;
5099                         vcpu->arch.dr6 |= DR6_BD;
5100                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5101                         kvm_queue_exception(vcpu, DB_VECTOR);
5102                         return 1;
5103                 }
5104         }
5105
5106         if (vcpu->guest_debug == 0) {
5107                 u32 cpu_based_vm_exec_control;
5108
5109                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5110                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5111                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5112
5113                 /*
5114                  * No more DR vmexits; force a reload of the debug registers
5115                  * and reenter on this instruction.  The next vmexit will
5116                  * retrieve the full state of the debug registers.
5117                  */
5118                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5119                 return 1;
5120         }
5121
5122         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5123         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5124         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5125         if (exit_qualification & TYPE_MOV_FROM_DR) {
5126                 unsigned long val;
5127
5128                 if (kvm_get_dr(vcpu, dr, &val))
5129                         return 1;
5130                 kvm_register_write(vcpu, reg, val);
5131         } else
5132                 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5133                         return 1;
5134
5135         skip_emulated_instruction(vcpu);
5136         return 1;
5137 }
5138
5139 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5140 {
5141         return vcpu->arch.dr6;
5142 }
5143
5144 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5145 {
5146 }
5147
5148 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5149 {
5150         u32 cpu_based_vm_exec_control;
5151
5152         get_debugreg(vcpu->arch.db[0], 0);
5153         get_debugreg(vcpu->arch.db[1], 1);
5154         get_debugreg(vcpu->arch.db[2], 2);
5155         get_debugreg(vcpu->arch.db[3], 3);
5156         get_debugreg(vcpu->arch.dr6, 6);
5157         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5158
5159         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5160
5161         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5162         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5163         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5164 }
5165
5166 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5167 {
5168         vmcs_writel(GUEST_DR7, val);
5169 }
5170
5171 static int handle_cpuid(struct kvm_vcpu *vcpu)
5172 {
5173         kvm_emulate_cpuid(vcpu);
5174         return 1;
5175 }
5176
5177 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5178 {
5179         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5180         u64 data;
5181
5182         if (vmx_get_msr(vcpu, ecx, &data)) {
5183                 trace_kvm_msr_read_ex(ecx);
5184                 kvm_inject_gp(vcpu, 0);
5185                 return 1;
5186         }
5187
5188         trace_kvm_msr_read(ecx, data);
5189
5190         /* FIXME: handling of bits 32:63 of rax, rdx */
5191         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5192         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5193         skip_emulated_instruction(vcpu);
5194         return 1;
5195 }
5196
5197 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5198 {
5199         struct msr_data msr;
5200         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5201         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5202                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5203
5204         msr.data = data;
5205         msr.index = ecx;
5206         msr.host_initiated = false;
5207         if (vmx_set_msr(vcpu, &msr) != 0) {
5208                 trace_kvm_msr_write_ex(ecx, data);
5209                 kvm_inject_gp(vcpu, 0);
5210                 return 1;
5211         }
5212
5213         trace_kvm_msr_write(ecx, data);
5214         skip_emulated_instruction(vcpu);
5215         return 1;
5216 }
5217
5218 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5219 {
5220         kvm_make_request(KVM_REQ_EVENT, vcpu);
5221         return 1;
5222 }
5223
5224 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5225 {
5226         u32 cpu_based_vm_exec_control;
5227
5228         /* clear pending irq */
5229         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5230         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5231         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5232
5233         kvm_make_request(KVM_REQ_EVENT, vcpu);
5234
5235         ++vcpu->stat.irq_window_exits;
5236
5237         /*
5238          * If the user space waits to inject interrupts, exit as soon as
5239          * possible
5240          */
5241         if (!irqchip_in_kernel(vcpu->kvm) &&
5242             vcpu->run->request_interrupt_window &&
5243             !kvm_cpu_has_interrupt(vcpu)) {
5244                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5245                 return 0;
5246         }
5247         return 1;
5248 }
5249
5250 static int handle_halt(struct kvm_vcpu *vcpu)
5251 {
5252         skip_emulated_instruction(vcpu);
5253         return kvm_emulate_halt(vcpu);
5254 }
5255
5256 static int handle_vmcall(struct kvm_vcpu *vcpu)
5257 {
5258         skip_emulated_instruction(vcpu);
5259         kvm_emulate_hypercall(vcpu);
5260         return 1;
5261 }
5262
5263 static int handle_invd(struct kvm_vcpu *vcpu)
5264 {
5265         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5266 }
5267
5268 static int handle_invlpg(struct kvm_vcpu *vcpu)
5269 {
5270         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5271
5272         kvm_mmu_invlpg(vcpu, exit_qualification);
5273         skip_emulated_instruction(vcpu);
5274         return 1;
5275 }
5276
5277 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5278 {
5279         int err;
5280
5281         err = kvm_rdpmc(vcpu);
5282         kvm_complete_insn_gp(vcpu, err);
5283
5284         return 1;
5285 }
5286
5287 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5288 {
5289         skip_emulated_instruction(vcpu);
5290         kvm_emulate_wbinvd(vcpu);
5291         return 1;
5292 }
5293
5294 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5295 {
5296         u64 new_bv = kvm_read_edx_eax(vcpu);
5297         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5298
5299         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5300                 skip_emulated_instruction(vcpu);
5301         return 1;
5302 }
5303
5304 static int handle_apic_access(struct kvm_vcpu *vcpu)
5305 {
5306         if (likely(fasteoi)) {
5307                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5308                 int access_type, offset;
5309
5310                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5311                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5312                 /*
5313                  * Sane guest uses MOV to write EOI, with written value
5314                  * not cared. So make a short-circuit here by avoiding
5315                  * heavy instruction emulation.
5316                  */
5317                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5318                     (offset == APIC_EOI)) {
5319                         kvm_lapic_set_eoi(vcpu);
5320                         skip_emulated_instruction(vcpu);
5321                         return 1;
5322                 }
5323         }
5324         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5325 }
5326
5327 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5328 {
5329         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5330         int vector = exit_qualification & 0xff;
5331
5332         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5333         kvm_apic_set_eoi_accelerated(vcpu, vector);
5334         return 1;
5335 }
5336
5337 static int handle_apic_write(struct kvm_vcpu *vcpu)
5338 {
5339         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5340         u32 offset = exit_qualification & 0xfff;
5341
5342         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5343         kvm_apic_write_nodecode(vcpu, offset);
5344         return 1;
5345 }
5346
5347 static int handle_task_switch(struct kvm_vcpu *vcpu)
5348 {
5349         struct vcpu_vmx *vmx = to_vmx(vcpu);
5350         unsigned long exit_qualification;
5351         bool has_error_code = false;
5352         u32 error_code = 0;
5353         u16 tss_selector;
5354         int reason, type, idt_v, idt_index;
5355
5356         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5357         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5358         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5359
5360         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5361
5362         reason = (u32)exit_qualification >> 30;
5363         if (reason == TASK_SWITCH_GATE && idt_v) {
5364                 switch (type) {
5365                 case INTR_TYPE_NMI_INTR:
5366                         vcpu->arch.nmi_injected = false;
5367                         vmx_set_nmi_mask(vcpu, true);
5368                         break;
5369                 case INTR_TYPE_EXT_INTR:
5370                 case INTR_TYPE_SOFT_INTR:
5371                         kvm_clear_interrupt_queue(vcpu);
5372                         break;
5373                 case INTR_TYPE_HARD_EXCEPTION:
5374                         if (vmx->idt_vectoring_info &
5375                             VECTORING_INFO_DELIVER_CODE_MASK) {
5376                                 has_error_code = true;
5377                                 error_code =
5378                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5379                         }
5380                         /* fall through */
5381                 case INTR_TYPE_SOFT_EXCEPTION:
5382                         kvm_clear_exception_queue(vcpu);
5383                         break;
5384                 default:
5385                         break;
5386                 }
5387         }
5388         tss_selector = exit_qualification;
5389
5390         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5391                        type != INTR_TYPE_EXT_INTR &&
5392                        type != INTR_TYPE_NMI_INTR))
5393                 skip_emulated_instruction(vcpu);
5394
5395         if (kvm_task_switch(vcpu, tss_selector,
5396                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5397                             has_error_code, error_code) == EMULATE_FAIL) {
5398                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5399                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5400                 vcpu->run->internal.ndata = 0;
5401                 return 0;
5402         }
5403
5404         /* clear all local breakpoint enable flags */
5405         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5406
5407         /*
5408          * TODO: What about debug traps on tss switch?
5409          *       Are we supposed to inject them and update dr6?
5410          */
5411
5412         return 1;
5413 }
5414
5415 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5416 {
5417         unsigned long exit_qualification;
5418         gpa_t gpa;
5419         u32 error_code;
5420         int gla_validity;
5421
5422         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5423
5424         gla_validity = (exit_qualification >> 7) & 0x3;
5425         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5426                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5427                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5428                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5429                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5430                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5431                         (long unsigned int)exit_qualification);
5432                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5433                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5434                 return 0;
5435         }
5436
5437         /*
5438          * EPT violation happened while executing iret from NMI,
5439          * "blocked by NMI" bit has to be set before next VM entry.
5440          * There are errata that may cause this bit to not be set:
5441          * AAK134, BY25.
5442          */
5443         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5444                         cpu_has_virtual_nmis() &&
5445                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5446                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5447
5448         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5449         trace_kvm_page_fault(gpa, exit_qualification);
5450
5451         /* It is a write fault? */
5452         error_code = exit_qualification & (1U << 1);
5453         /* It is a fetch fault? */
5454         error_code |= (exit_qualification & (1U << 2)) << 2;
5455         /* ept page table is present? */
5456         error_code |= (exit_qualification >> 3) & 0x1;
5457
5458         vcpu->arch.exit_qualification = exit_qualification;
5459
5460         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5461 }
5462
5463 static u64 ept_rsvd_mask(u64 spte, int level)
5464 {
5465         int i;
5466         u64 mask = 0;
5467
5468         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5469                 mask |= (1ULL << i);
5470
5471         if (level > 2)
5472                 /* bits 7:3 reserved */
5473                 mask |= 0xf8;
5474         else if (level == 2) {
5475                 if (spte & (1ULL << 7))
5476                         /* 2MB ref, bits 20:12 reserved */
5477                         mask |= 0x1ff000;
5478                 else
5479                         /* bits 6:3 reserved */
5480                         mask |= 0x78;
5481         }
5482
5483         return mask;
5484 }
5485
5486 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5487                                        int level)
5488 {
5489         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5490
5491         /* 010b (write-only) */
5492         WARN_ON((spte & 0x7) == 0x2);
5493
5494         /* 110b (write/execute) */
5495         WARN_ON((spte & 0x7) == 0x6);
5496
5497         /* 100b (execute-only) and value not supported by logical processor */
5498         if (!cpu_has_vmx_ept_execute_only())
5499                 WARN_ON((spte & 0x7) == 0x4);
5500
5501         /* not 000b */
5502         if ((spte & 0x7)) {
5503                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5504
5505                 if (rsvd_bits != 0) {
5506                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5507                                          __func__, rsvd_bits);
5508                         WARN_ON(1);
5509                 }
5510
5511                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5512                         u64 ept_mem_type = (spte & 0x38) >> 3;
5513
5514                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5515                             ept_mem_type == 7) {
5516                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5517                                                 __func__, ept_mem_type);
5518                                 WARN_ON(1);
5519                         }
5520                 }
5521         }
5522 }
5523
5524 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5525 {
5526         u64 sptes[4];
5527         int nr_sptes, i, ret;
5528         gpa_t gpa;
5529
5530         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5531
5532         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5533         if (likely(ret == RET_MMIO_PF_EMULATE))
5534                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5535                                               EMULATE_DONE;
5536
5537         if (unlikely(ret == RET_MMIO_PF_INVALID))
5538                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5539
5540         if (unlikely(ret == RET_MMIO_PF_RETRY))
5541                 return 1;
5542
5543         /* It is the real ept misconfig */
5544         printk(KERN_ERR "EPT: Misconfiguration.\n");
5545         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5546
5547         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5548
5549         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5550                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5551
5552         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5553         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5554
5555         return 0;
5556 }
5557
5558 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5559 {
5560         u32 cpu_based_vm_exec_control;
5561
5562         /* clear pending NMI */
5563         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5564         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5565         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5566         ++vcpu->stat.nmi_window_exits;
5567         kvm_make_request(KVM_REQ_EVENT, vcpu);
5568
5569         return 1;
5570 }
5571
5572 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5573 {
5574         struct vcpu_vmx *vmx = to_vmx(vcpu);
5575         enum emulation_result err = EMULATE_DONE;
5576         int ret = 1;
5577         u32 cpu_exec_ctrl;
5578         bool intr_window_requested;
5579         unsigned count = 130;
5580
5581         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5582         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5583
5584         while (!guest_state_valid(vcpu) && count-- != 0) {
5585                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5586                         return handle_interrupt_window(&vmx->vcpu);
5587
5588                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5589                         return 1;
5590
5591                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5592
5593                 if (err == EMULATE_USER_EXIT) {
5594                         ++vcpu->stat.mmio_exits;
5595                         ret = 0;
5596                         goto out;
5597                 }
5598
5599                 if (err != EMULATE_DONE) {
5600                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5601                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5602                         vcpu->run->internal.ndata = 0;
5603                         return 0;
5604                 }
5605
5606                 if (vcpu->arch.halt_request) {
5607                         vcpu->arch.halt_request = 0;
5608                         ret = kvm_emulate_halt(vcpu);
5609                         goto out;
5610                 }
5611
5612                 if (signal_pending(current))
5613                         goto out;
5614                 if (need_resched())
5615                         schedule();
5616         }
5617
5618         vmx->emulation_required = emulation_required(vcpu);
5619 out:
5620         return ret;
5621 }
5622
5623 /*
5624  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5625  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5626  */
5627 static int handle_pause(struct kvm_vcpu *vcpu)
5628 {
5629         skip_emulated_instruction(vcpu);
5630         kvm_vcpu_on_spin(vcpu);
5631
5632         return 1;
5633 }
5634
5635 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5636 {
5637         kvm_queue_exception(vcpu, UD_VECTOR);
5638         return 1;
5639 }
5640
5641 /*
5642  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5643  * We could reuse a single VMCS for all the L2 guests, but we also want the
5644  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5645  * allows keeping them loaded on the processor, and in the future will allow
5646  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5647  * every entry if they never change.
5648  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5649  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5650  *
5651  * The following functions allocate and free a vmcs02 in this pool.
5652  */
5653
5654 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5655 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5656 {
5657         struct vmcs02_list *item;
5658         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5659                 if (item->vmptr == vmx->nested.current_vmptr) {
5660                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5661                         return &item->vmcs02;
5662                 }
5663
5664         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5665                 /* Recycle the least recently used VMCS. */
5666                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5667                         struct vmcs02_list, list);
5668                 item->vmptr = vmx->nested.current_vmptr;
5669                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5670                 return &item->vmcs02;
5671         }
5672
5673         /* Create a new VMCS */
5674         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5675         if (!item)
5676                 return NULL;
5677         item->vmcs02.vmcs = alloc_vmcs();
5678         if (!item->vmcs02.vmcs) {
5679                 kfree(item);
5680                 return NULL;
5681         }
5682         loaded_vmcs_init(&item->vmcs02);
5683         item->vmptr = vmx->nested.current_vmptr;
5684         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5685         vmx->nested.vmcs02_num++;
5686         return &item->vmcs02;
5687 }
5688
5689 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5690 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5691 {
5692         struct vmcs02_list *item;
5693         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5694                 if (item->vmptr == vmptr) {
5695                         free_loaded_vmcs(&item->vmcs02);
5696                         list_del(&item->list);
5697                         kfree(item);
5698                         vmx->nested.vmcs02_num--;
5699                         return;
5700                 }
5701 }
5702
5703 /*
5704  * Free all VMCSs saved for this vcpu, except the one pointed by
5705  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5706  * currently used, if running L2), and vmcs01 when running L2.
5707  */
5708 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5709 {
5710         struct vmcs02_list *item, *n;
5711         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5712                 if (vmx->loaded_vmcs != &item->vmcs02)
5713                         free_loaded_vmcs(&item->vmcs02);
5714                 list_del(&item->list);
5715                 kfree(item);
5716         }
5717         vmx->nested.vmcs02_num = 0;
5718
5719         if (vmx->loaded_vmcs != &vmx->vmcs01)
5720                 free_loaded_vmcs(&vmx->vmcs01);
5721 }
5722
5723 /*
5724  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5725  * set the success or error code of an emulated VMX instruction, as specified
5726  * by Vol 2B, VMX Instruction Reference, "Conventions".
5727  */
5728 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5729 {
5730         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5731                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5732                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5733 }
5734
5735 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5736 {
5737         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5738                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5739                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5740                         | X86_EFLAGS_CF);
5741 }
5742
5743 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5744                                         u32 vm_instruction_error)
5745 {
5746         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5747                 /*
5748                  * failValid writes the error number to the current VMCS, which
5749                  * can't be done there isn't a current VMCS.
5750                  */
5751                 nested_vmx_failInvalid(vcpu);
5752                 return;
5753         }
5754         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5755                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5756                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5757                         | X86_EFLAGS_ZF);
5758         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5759         /*
5760          * We don't need to force a shadow sync because
5761          * VM_INSTRUCTION_ERROR is not shadowed
5762          */
5763 }
5764
5765 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5766 {
5767         struct vcpu_vmx *vmx =
5768                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5769
5770         vmx->nested.preemption_timer_expired = true;
5771         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5772         kvm_vcpu_kick(&vmx->vcpu);
5773
5774         return HRTIMER_NORESTART;
5775 }
5776
5777 /*
5778  * Emulate the VMXON instruction.
5779  * Currently, we just remember that VMX is active, and do not save or even
5780  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5781  * do not currently need to store anything in that guest-allocated memory
5782  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5783  * argument is different from the VMXON pointer (which the spec says they do).
5784  */
5785 static int handle_vmon(struct kvm_vcpu *vcpu)
5786 {
5787         struct kvm_segment cs;
5788         struct vcpu_vmx *vmx = to_vmx(vcpu);
5789         struct vmcs *shadow_vmcs;
5790         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5791                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5792
5793         /* The Intel VMX Instruction Reference lists a bunch of bits that
5794          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5795          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5796          * Otherwise, we should fail with #UD. We test these now:
5797          */
5798         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5799             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5800             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5801                 kvm_queue_exception(vcpu, UD_VECTOR);
5802                 return 1;
5803         }
5804
5805         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5806         if (is_long_mode(vcpu) && !cs.l) {
5807                 kvm_queue_exception(vcpu, UD_VECTOR);
5808                 return 1;
5809         }
5810
5811         if (vmx_get_cpl(vcpu)) {
5812                 kvm_inject_gp(vcpu, 0);
5813                 return 1;
5814         }
5815         if (vmx->nested.vmxon) {
5816                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5817                 skip_emulated_instruction(vcpu);
5818                 return 1;
5819         }
5820
5821         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5822                         != VMXON_NEEDED_FEATURES) {
5823                 kvm_inject_gp(vcpu, 0);
5824                 return 1;
5825         }
5826
5827         if (enable_shadow_vmcs) {
5828                 shadow_vmcs = alloc_vmcs();
5829                 if (!shadow_vmcs)
5830                         return -ENOMEM;
5831                 /* mark vmcs as shadow */
5832                 shadow_vmcs->revision_id |= (1u << 31);
5833                 /* init shadow vmcs */
5834                 vmcs_clear(shadow_vmcs);
5835                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5836         }
5837
5838         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5839         vmx->nested.vmcs02_num = 0;
5840
5841         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5842                      HRTIMER_MODE_REL);
5843         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5844
5845         vmx->nested.vmxon = true;
5846
5847         skip_emulated_instruction(vcpu);
5848         nested_vmx_succeed(vcpu);
5849         return 1;
5850 }
5851
5852 /*
5853  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5854  * for running VMX instructions (except VMXON, whose prerequisites are
5855  * slightly different). It also specifies what exception to inject otherwise.
5856  */
5857 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5858 {
5859         struct kvm_segment cs;
5860         struct vcpu_vmx *vmx = to_vmx(vcpu);
5861
5862         if (!vmx->nested.vmxon) {
5863                 kvm_queue_exception(vcpu, UD_VECTOR);
5864                 return 0;
5865         }
5866
5867         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5868         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5869             (is_long_mode(vcpu) && !cs.l)) {
5870                 kvm_queue_exception(vcpu, UD_VECTOR);
5871                 return 0;
5872         }
5873
5874         if (vmx_get_cpl(vcpu)) {
5875                 kvm_inject_gp(vcpu, 0);
5876                 return 0;
5877         }
5878
5879         return 1;
5880 }
5881
5882 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5883 {
5884         u32 exec_control;
5885         if (enable_shadow_vmcs) {
5886                 if (vmx->nested.current_vmcs12 != NULL) {
5887                         /* copy to memory all shadowed fields in case
5888                            they were modified */
5889                         copy_shadow_to_vmcs12(vmx);
5890                         vmx->nested.sync_shadow_vmcs = false;
5891                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5892                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5893                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5894                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5895                 }
5896         }
5897         kunmap(vmx->nested.current_vmcs12_page);
5898         nested_release_page(vmx->nested.current_vmcs12_page);
5899 }
5900
5901 /*
5902  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5903  * just stops using VMX.
5904  */
5905 static void free_nested(struct vcpu_vmx *vmx)
5906 {
5907         if (!vmx->nested.vmxon)
5908                 return;
5909         vmx->nested.vmxon = false;
5910         if (vmx->nested.current_vmptr != -1ull) {
5911                 nested_release_vmcs12(vmx);
5912                 vmx->nested.current_vmptr = -1ull;
5913                 vmx->nested.current_vmcs12 = NULL;
5914         }
5915         if (enable_shadow_vmcs)
5916                 free_vmcs(vmx->nested.current_shadow_vmcs);
5917         /* Unpin physical memory we referred to in current vmcs02 */
5918         if (vmx->nested.apic_access_page) {
5919                 nested_release_page(vmx->nested.apic_access_page);
5920                 vmx->nested.apic_access_page = 0;
5921         }
5922
5923         nested_free_all_saved_vmcss(vmx);
5924 }
5925
5926 /* Emulate the VMXOFF instruction */
5927 static int handle_vmoff(struct kvm_vcpu *vcpu)
5928 {
5929         if (!nested_vmx_check_permission(vcpu))
5930                 return 1;
5931         free_nested(to_vmx(vcpu));
5932         skip_emulated_instruction(vcpu);
5933         nested_vmx_succeed(vcpu);
5934         return 1;
5935 }
5936
5937 /*
5938  * Decode the memory-address operand of a vmx instruction, as recorded on an
5939  * exit caused by such an instruction (run by a guest hypervisor).
5940  * On success, returns 0. When the operand is invalid, returns 1 and throws
5941  * #UD or #GP.
5942  */
5943 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5944                                  unsigned long exit_qualification,
5945                                  u32 vmx_instruction_info, gva_t *ret)
5946 {
5947         /*
5948          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5949          * Execution", on an exit, vmx_instruction_info holds most of the
5950          * addressing components of the operand. Only the displacement part
5951          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5952          * For how an actual address is calculated from all these components,
5953          * refer to Vol. 1, "Operand Addressing".
5954          */
5955         int  scaling = vmx_instruction_info & 3;
5956         int  addr_size = (vmx_instruction_info >> 7) & 7;
5957         bool is_reg = vmx_instruction_info & (1u << 10);
5958         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5959         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5960         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5961         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5962         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5963
5964         if (is_reg) {
5965                 kvm_queue_exception(vcpu, UD_VECTOR);
5966                 return 1;
5967         }
5968
5969         /* Addr = segment_base + offset */
5970         /* offset = base + [index * scale] + displacement */
5971         *ret = vmx_get_segment_base(vcpu, seg_reg);
5972         if (base_is_valid)
5973                 *ret += kvm_register_read(vcpu, base_reg);
5974         if (index_is_valid)
5975                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5976         *ret += exit_qualification; /* holds the displacement */
5977
5978         if (addr_size == 1) /* 32 bit */
5979                 *ret &= 0xffffffff;
5980
5981         /*
5982          * TODO: throw #GP (and return 1) in various cases that the VM*
5983          * instructions require it - e.g., offset beyond segment limit,
5984          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5985          * address, and so on. Currently these are not checked.
5986          */
5987         return 0;
5988 }
5989
5990 /* Emulate the VMCLEAR instruction */
5991 static int handle_vmclear(struct kvm_vcpu *vcpu)
5992 {
5993         struct vcpu_vmx *vmx = to_vmx(vcpu);
5994         gva_t gva;
5995         gpa_t vmptr;
5996         struct vmcs12 *vmcs12;
5997         struct page *page;
5998         struct x86_exception e;
5999
6000         if (!nested_vmx_check_permission(vcpu))
6001                 return 1;
6002
6003         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6004                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6005                 return 1;
6006
6007         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6008                                 sizeof(vmptr), &e)) {
6009                 kvm_inject_page_fault(vcpu, &e);
6010                 return 1;
6011         }
6012
6013         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6014                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6015                 skip_emulated_instruction(vcpu);
6016                 return 1;
6017         }
6018
6019         if (vmptr == vmx->nested.current_vmptr) {
6020                 nested_release_vmcs12(vmx);
6021                 vmx->nested.current_vmptr = -1ull;
6022                 vmx->nested.current_vmcs12 = NULL;
6023         }
6024
6025         page = nested_get_page(vcpu, vmptr);
6026         if (page == NULL) {
6027                 /*
6028                  * For accurate processor emulation, VMCLEAR beyond available
6029                  * physical memory should do nothing at all. However, it is
6030                  * possible that a nested vmx bug, not a guest hypervisor bug,
6031                  * resulted in this case, so let's shut down before doing any
6032                  * more damage:
6033                  */
6034                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6035                 return 1;
6036         }
6037         vmcs12 = kmap(page);
6038         vmcs12->launch_state = 0;
6039         kunmap(page);
6040         nested_release_page(page);
6041
6042         nested_free_vmcs02(vmx, vmptr);
6043
6044         skip_emulated_instruction(vcpu);
6045         nested_vmx_succeed(vcpu);
6046         return 1;
6047 }
6048
6049 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6050
6051 /* Emulate the VMLAUNCH instruction */
6052 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6053 {
6054         return nested_vmx_run(vcpu, true);
6055 }
6056
6057 /* Emulate the VMRESUME instruction */
6058 static int handle_vmresume(struct kvm_vcpu *vcpu)
6059 {
6060
6061         return nested_vmx_run(vcpu, false);
6062 }
6063
6064 enum vmcs_field_type {
6065         VMCS_FIELD_TYPE_U16 = 0,
6066         VMCS_FIELD_TYPE_U64 = 1,
6067         VMCS_FIELD_TYPE_U32 = 2,
6068         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6069 };
6070
6071 static inline int vmcs_field_type(unsigned long field)
6072 {
6073         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6074                 return VMCS_FIELD_TYPE_U32;
6075         return (field >> 13) & 0x3 ;
6076 }
6077
6078 static inline int vmcs_field_readonly(unsigned long field)
6079 {
6080         return (((field >> 10) & 0x3) == 1);
6081 }
6082
6083 /*
6084  * Read a vmcs12 field. Since these can have varying lengths and we return
6085  * one type, we chose the biggest type (u64) and zero-extend the return value
6086  * to that size. Note that the caller, handle_vmread, might need to use only
6087  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6088  * 64-bit fields are to be returned).
6089  */
6090 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6091                                         unsigned long field, u64 *ret)
6092 {
6093         short offset = vmcs_field_to_offset(field);
6094         char *p;
6095
6096         if (offset < 0)
6097                 return 0;
6098
6099         p = ((char *)(get_vmcs12(vcpu))) + offset;
6100
6101         switch (vmcs_field_type(field)) {
6102         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6103                 *ret = *((natural_width *)p);
6104                 return 1;
6105         case VMCS_FIELD_TYPE_U16:
6106                 *ret = *((u16 *)p);
6107                 return 1;
6108         case VMCS_FIELD_TYPE_U32:
6109                 *ret = *((u32 *)p);
6110                 return 1;
6111         case VMCS_FIELD_TYPE_U64:
6112                 *ret = *((u64 *)p);
6113                 return 1;
6114         default:
6115                 return 0; /* can never happen. */
6116         }
6117 }
6118
6119
6120 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6121                                     unsigned long field, u64 field_value){
6122         short offset = vmcs_field_to_offset(field);
6123         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6124         if (offset < 0)
6125                 return false;
6126
6127         switch (vmcs_field_type(field)) {
6128         case VMCS_FIELD_TYPE_U16:
6129                 *(u16 *)p = field_value;
6130                 return true;
6131         case VMCS_FIELD_TYPE_U32:
6132                 *(u32 *)p = field_value;
6133                 return true;
6134         case VMCS_FIELD_TYPE_U64:
6135                 *(u64 *)p = field_value;
6136                 return true;
6137         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6138                 *(natural_width *)p = field_value;
6139                 return true;
6140         default:
6141                 return false; /* can never happen. */
6142         }
6143
6144 }
6145
6146 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6147 {
6148         int i;
6149         unsigned long field;
6150         u64 field_value;
6151         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6152         const unsigned long *fields = shadow_read_write_fields;
6153         const int num_fields = max_shadow_read_write_fields;
6154
6155         vmcs_load(shadow_vmcs);
6156
6157         for (i = 0; i < num_fields; i++) {
6158                 field = fields[i];
6159                 switch (vmcs_field_type(field)) {
6160                 case VMCS_FIELD_TYPE_U16:
6161                         field_value = vmcs_read16(field);
6162                         break;
6163                 case VMCS_FIELD_TYPE_U32:
6164                         field_value = vmcs_read32(field);
6165                         break;
6166                 case VMCS_FIELD_TYPE_U64:
6167                         field_value = vmcs_read64(field);
6168                         break;
6169                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6170                         field_value = vmcs_readl(field);
6171                         break;
6172                 }
6173                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6174         }
6175
6176         vmcs_clear(shadow_vmcs);
6177         vmcs_load(vmx->loaded_vmcs->vmcs);
6178 }
6179
6180 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6181 {
6182         const unsigned long *fields[] = {
6183                 shadow_read_write_fields,
6184                 shadow_read_only_fields
6185         };
6186         const int max_fields[] = {
6187                 max_shadow_read_write_fields,
6188                 max_shadow_read_only_fields
6189         };
6190         int i, q;
6191         unsigned long field;
6192         u64 field_value = 0;
6193         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6194
6195         vmcs_load(shadow_vmcs);
6196
6197         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6198                 for (i = 0; i < max_fields[q]; i++) {
6199                         field = fields[q][i];
6200                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6201
6202                         switch (vmcs_field_type(field)) {
6203                         case VMCS_FIELD_TYPE_U16:
6204                                 vmcs_write16(field, (u16)field_value);
6205                                 break;
6206                         case VMCS_FIELD_TYPE_U32:
6207                                 vmcs_write32(field, (u32)field_value);
6208                                 break;
6209                         case VMCS_FIELD_TYPE_U64:
6210                                 vmcs_write64(field, (u64)field_value);
6211                                 break;
6212                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6213                                 vmcs_writel(field, (long)field_value);
6214                                 break;
6215                         }
6216                 }
6217         }
6218
6219         vmcs_clear(shadow_vmcs);
6220         vmcs_load(vmx->loaded_vmcs->vmcs);
6221 }
6222
6223 /*
6224  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6225  * used before) all generate the same failure when it is missing.
6226  */
6227 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6228 {
6229         struct vcpu_vmx *vmx = to_vmx(vcpu);
6230         if (vmx->nested.current_vmptr == -1ull) {
6231                 nested_vmx_failInvalid(vcpu);
6232                 skip_emulated_instruction(vcpu);
6233                 return 0;
6234         }
6235         return 1;
6236 }
6237
6238 static int handle_vmread(struct kvm_vcpu *vcpu)
6239 {
6240         unsigned long field;
6241         u64 field_value;
6242         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6243         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6244         gva_t gva = 0;
6245
6246         if (!nested_vmx_check_permission(vcpu) ||
6247             !nested_vmx_check_vmcs12(vcpu))
6248                 return 1;
6249
6250         /* Decode instruction info and find the field to read */
6251         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6252         /* Read the field, zero-extended to a u64 field_value */
6253         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6254                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6255                 skip_emulated_instruction(vcpu);
6256                 return 1;
6257         }
6258         /*
6259          * Now copy part of this value to register or memory, as requested.
6260          * Note that the number of bits actually copied is 32 or 64 depending
6261          * on the guest's mode (32 or 64 bit), not on the given field's length.
6262          */
6263         if (vmx_instruction_info & (1u << 10)) {
6264                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6265                         field_value);
6266         } else {
6267                 if (get_vmx_mem_address(vcpu, exit_qualification,
6268                                 vmx_instruction_info, &gva))
6269                         return 1;
6270                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6271                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6272                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6273         }
6274
6275         nested_vmx_succeed(vcpu);
6276         skip_emulated_instruction(vcpu);
6277         return 1;
6278 }
6279
6280
6281 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6282 {
6283         unsigned long field;
6284         gva_t gva;
6285         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6286         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6287         /* The value to write might be 32 or 64 bits, depending on L1's long
6288          * mode, and eventually we need to write that into a field of several
6289          * possible lengths. The code below first zero-extends the value to 64
6290          * bit (field_value), and then copies only the approriate number of
6291          * bits into the vmcs12 field.
6292          */
6293         u64 field_value = 0;
6294         struct x86_exception e;
6295
6296         if (!nested_vmx_check_permission(vcpu) ||
6297             !nested_vmx_check_vmcs12(vcpu))
6298                 return 1;
6299
6300         if (vmx_instruction_info & (1u << 10))
6301                 field_value = kvm_register_read(vcpu,
6302                         (((vmx_instruction_info) >> 3) & 0xf));
6303         else {
6304                 if (get_vmx_mem_address(vcpu, exit_qualification,
6305                                 vmx_instruction_info, &gva))
6306                         return 1;
6307                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6308                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6309                         kvm_inject_page_fault(vcpu, &e);
6310                         return 1;
6311                 }
6312         }
6313
6314
6315         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6316         if (vmcs_field_readonly(field)) {
6317                 nested_vmx_failValid(vcpu,
6318                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6319                 skip_emulated_instruction(vcpu);
6320                 return 1;
6321         }
6322
6323         if (!vmcs12_write_any(vcpu, field, field_value)) {
6324                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6325                 skip_emulated_instruction(vcpu);
6326                 return 1;
6327         }
6328
6329         nested_vmx_succeed(vcpu);
6330         skip_emulated_instruction(vcpu);
6331         return 1;
6332 }
6333
6334 /* Emulate the VMPTRLD instruction */
6335 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6336 {
6337         struct vcpu_vmx *vmx = to_vmx(vcpu);
6338         gva_t gva;
6339         gpa_t vmptr;
6340         struct x86_exception e;
6341         u32 exec_control;
6342
6343         if (!nested_vmx_check_permission(vcpu))
6344                 return 1;
6345
6346         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6347                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6348                 return 1;
6349
6350         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6351                                 sizeof(vmptr), &e)) {
6352                 kvm_inject_page_fault(vcpu, &e);
6353                 return 1;
6354         }
6355
6356         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6357                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6358                 skip_emulated_instruction(vcpu);
6359                 return 1;
6360         }
6361
6362         if (vmx->nested.current_vmptr != vmptr) {
6363                 struct vmcs12 *new_vmcs12;
6364                 struct page *page;
6365                 page = nested_get_page(vcpu, vmptr);
6366                 if (page == NULL) {
6367                         nested_vmx_failInvalid(vcpu);
6368                         skip_emulated_instruction(vcpu);
6369                         return 1;
6370                 }
6371                 new_vmcs12 = kmap(page);
6372                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6373                         kunmap(page);
6374                         nested_release_page_clean(page);
6375                         nested_vmx_failValid(vcpu,
6376                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6377                         skip_emulated_instruction(vcpu);
6378                         return 1;
6379                 }
6380                 if (vmx->nested.current_vmptr != -1ull)
6381                         nested_release_vmcs12(vmx);
6382
6383                 vmx->nested.current_vmptr = vmptr;
6384                 vmx->nested.current_vmcs12 = new_vmcs12;
6385                 vmx->nested.current_vmcs12_page = page;
6386                 if (enable_shadow_vmcs) {
6387                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6388                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6389                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6390                         vmcs_write64(VMCS_LINK_POINTER,
6391                                      __pa(vmx->nested.current_shadow_vmcs));
6392                         vmx->nested.sync_shadow_vmcs = true;
6393                 }
6394         }
6395
6396         nested_vmx_succeed(vcpu);
6397         skip_emulated_instruction(vcpu);
6398         return 1;
6399 }
6400
6401 /* Emulate the VMPTRST instruction */
6402 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6403 {
6404         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6405         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6406         gva_t vmcs_gva;
6407         struct x86_exception e;
6408
6409         if (!nested_vmx_check_permission(vcpu))
6410                 return 1;
6411
6412         if (get_vmx_mem_address(vcpu, exit_qualification,
6413                         vmx_instruction_info, &vmcs_gva))
6414                 return 1;
6415         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6416         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6417                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6418                                  sizeof(u64), &e)) {
6419                 kvm_inject_page_fault(vcpu, &e);
6420                 return 1;
6421         }
6422         nested_vmx_succeed(vcpu);
6423         skip_emulated_instruction(vcpu);
6424         return 1;
6425 }
6426
6427 /* Emulate the INVEPT instruction */
6428 static int handle_invept(struct kvm_vcpu *vcpu)
6429 {
6430         u32 vmx_instruction_info, types;
6431         unsigned long type;
6432         gva_t gva;
6433         struct x86_exception e;
6434         struct {
6435                 u64 eptp, gpa;
6436         } operand;
6437         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6438
6439         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6440             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6441                 kvm_queue_exception(vcpu, UD_VECTOR);
6442                 return 1;
6443         }
6444
6445         if (!nested_vmx_check_permission(vcpu))
6446                 return 1;
6447
6448         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6449                 kvm_queue_exception(vcpu, UD_VECTOR);
6450                 return 1;
6451         }
6452
6453         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6454         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6455
6456         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6457
6458         if (!(types & (1UL << type))) {
6459                 nested_vmx_failValid(vcpu,
6460                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6461                 return 1;
6462         }
6463
6464         /* According to the Intel VMX instruction reference, the memory
6465          * operand is read even if it isn't needed (e.g., for type==global)
6466          */
6467         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6468                         vmx_instruction_info, &gva))
6469                 return 1;
6470         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6471                                 sizeof(operand), &e)) {
6472                 kvm_inject_page_fault(vcpu, &e);
6473                 return 1;
6474         }
6475
6476         switch (type) {
6477         case VMX_EPT_EXTENT_CONTEXT:
6478                 if ((operand.eptp & eptp_mask) !=
6479                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6480                         break;
6481         case VMX_EPT_EXTENT_GLOBAL:
6482                 kvm_mmu_sync_roots(vcpu);
6483                 kvm_mmu_flush_tlb(vcpu);
6484                 nested_vmx_succeed(vcpu);
6485                 break;
6486         default:
6487                 BUG_ON(1);
6488                 break;
6489         }
6490
6491         skip_emulated_instruction(vcpu);
6492         return 1;
6493 }
6494
6495 /*
6496  * The exit handlers return 1 if the exit was handled fully and guest execution
6497  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6498  * to be done to userspace and return 0.
6499  */
6500 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6501         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6502         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6503         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6504         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6505         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6506         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6507         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6508         [EXIT_REASON_CPUID]                   = handle_cpuid,
6509         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6510         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6511         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6512         [EXIT_REASON_HLT]                     = handle_halt,
6513         [EXIT_REASON_INVD]                    = handle_invd,
6514         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6515         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6516         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6517         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6518         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6519         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6520         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6521         [EXIT_REASON_VMREAD]                  = handle_vmread,
6522         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6523         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6524         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6525         [EXIT_REASON_VMON]                    = handle_vmon,
6526         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6527         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6528         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6529         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6530         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6531         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6532         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6533         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6534         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6535         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6536         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6537         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6538         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6539         [EXIT_REASON_INVEPT]                  = handle_invept,
6540 };
6541
6542 static const int kvm_vmx_max_exit_handlers =
6543         ARRAY_SIZE(kvm_vmx_exit_handlers);
6544
6545 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6546                                        struct vmcs12 *vmcs12)
6547 {
6548         unsigned long exit_qualification;
6549         gpa_t bitmap, last_bitmap;
6550         unsigned int port;
6551         int size;
6552         u8 b;
6553
6554         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6555                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6556
6557         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6558
6559         port = exit_qualification >> 16;
6560         size = (exit_qualification & 7) + 1;
6561
6562         last_bitmap = (gpa_t)-1;
6563         b = -1;
6564
6565         while (size > 0) {
6566                 if (port < 0x8000)
6567                         bitmap = vmcs12->io_bitmap_a;
6568                 else if (port < 0x10000)
6569                         bitmap = vmcs12->io_bitmap_b;
6570                 else
6571                         return 1;
6572                 bitmap += (port & 0x7fff) / 8;
6573
6574                 if (last_bitmap != bitmap)
6575                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6576                                 return 1;
6577                 if (b & (1 << (port & 7)))
6578                         return 1;
6579
6580                 port++;
6581                 size--;
6582                 last_bitmap = bitmap;
6583         }
6584
6585         return 0;
6586 }
6587
6588 /*
6589  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6590  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6591  * disinterest in the current event (read or write a specific MSR) by using an
6592  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6593  */
6594 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6595         struct vmcs12 *vmcs12, u32 exit_reason)
6596 {
6597         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6598         gpa_t bitmap;
6599
6600         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6601                 return 1;
6602
6603         /*
6604          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6605          * for the four combinations of read/write and low/high MSR numbers.
6606          * First we need to figure out which of the four to use:
6607          */
6608         bitmap = vmcs12->msr_bitmap;
6609         if (exit_reason == EXIT_REASON_MSR_WRITE)
6610                 bitmap += 2048;
6611         if (msr_index >= 0xc0000000) {
6612                 msr_index -= 0xc0000000;
6613                 bitmap += 1024;
6614         }
6615
6616         /* Then read the msr_index'th bit from this bitmap: */
6617         if (msr_index < 1024*8) {
6618                 unsigned char b;
6619                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6620                         return 1;
6621                 return 1 & (b >> (msr_index & 7));
6622         } else
6623                 return 1; /* let L1 handle the wrong parameter */
6624 }
6625
6626 /*
6627  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6628  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6629  * intercept (via guest_host_mask etc.) the current event.
6630  */
6631 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6632         struct vmcs12 *vmcs12)
6633 {
6634         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6635         int cr = exit_qualification & 15;
6636         int reg = (exit_qualification >> 8) & 15;
6637         unsigned long val = kvm_register_read(vcpu, reg);
6638
6639         switch ((exit_qualification >> 4) & 3) {
6640         case 0: /* mov to cr */
6641                 switch (cr) {
6642                 case 0:
6643                         if (vmcs12->cr0_guest_host_mask &
6644                             (val ^ vmcs12->cr0_read_shadow))
6645                                 return 1;
6646                         break;
6647                 case 3:
6648                         if ((vmcs12->cr3_target_count >= 1 &&
6649                                         vmcs12->cr3_target_value0 == val) ||
6650                                 (vmcs12->cr3_target_count >= 2 &&
6651                                         vmcs12->cr3_target_value1 == val) ||
6652                                 (vmcs12->cr3_target_count >= 3 &&
6653                                         vmcs12->cr3_target_value2 == val) ||
6654                                 (vmcs12->cr3_target_count >= 4 &&
6655                                         vmcs12->cr3_target_value3 == val))
6656                                 return 0;
6657                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6658                                 return 1;
6659                         break;
6660                 case 4:
6661                         if (vmcs12->cr4_guest_host_mask &
6662                             (vmcs12->cr4_read_shadow ^ val))
6663                                 return 1;
6664                         break;
6665                 case 8:
6666                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6667                                 return 1;
6668                         break;
6669                 }
6670                 break;
6671         case 2: /* clts */
6672                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6673                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6674                         return 1;
6675                 break;
6676         case 1: /* mov from cr */
6677                 switch (cr) {
6678                 case 3:
6679                         if (vmcs12->cpu_based_vm_exec_control &
6680                             CPU_BASED_CR3_STORE_EXITING)
6681                                 return 1;
6682                         break;
6683                 case 8:
6684                         if (vmcs12->cpu_based_vm_exec_control &
6685                             CPU_BASED_CR8_STORE_EXITING)
6686                                 return 1;
6687                         break;
6688                 }
6689                 break;
6690         case 3: /* lmsw */
6691                 /*
6692                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6693                  * cr0. Other attempted changes are ignored, with no exit.
6694                  */
6695                 if (vmcs12->cr0_guest_host_mask & 0xe &
6696                     (val ^ vmcs12->cr0_read_shadow))
6697                         return 1;
6698                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6699                     !(vmcs12->cr0_read_shadow & 0x1) &&
6700                     (val & 0x1))
6701                         return 1;
6702                 break;
6703         }
6704         return 0;
6705 }
6706
6707 /*
6708  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6709  * should handle it ourselves in L0 (and then continue L2). Only call this
6710  * when in is_guest_mode (L2).
6711  */
6712 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6713 {
6714         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6715         struct vcpu_vmx *vmx = to_vmx(vcpu);
6716         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6717         u32 exit_reason = vmx->exit_reason;
6718
6719         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6720                                 vmcs_readl(EXIT_QUALIFICATION),
6721                                 vmx->idt_vectoring_info,
6722                                 intr_info,
6723                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6724                                 KVM_ISA_VMX);
6725
6726         if (vmx->nested.nested_run_pending)
6727                 return 0;
6728
6729         if (unlikely(vmx->fail)) {
6730                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6731                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6732                 return 1;
6733         }
6734
6735         switch (exit_reason) {
6736         case EXIT_REASON_EXCEPTION_NMI:
6737                 if (!is_exception(intr_info))
6738                         return 0;
6739                 else if (is_page_fault(intr_info))
6740                         return enable_ept;
6741                 else if (is_no_device(intr_info) &&
6742                          !(vmcs12->guest_cr0 & X86_CR0_TS))
6743                         return 0;
6744                 return vmcs12->exception_bitmap &
6745                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6746         case EXIT_REASON_EXTERNAL_INTERRUPT:
6747                 return 0;
6748         case EXIT_REASON_TRIPLE_FAULT:
6749                 return 1;
6750         case EXIT_REASON_PENDING_INTERRUPT:
6751                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6752         case EXIT_REASON_NMI_WINDOW:
6753                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6754         case EXIT_REASON_TASK_SWITCH:
6755                 return 1;
6756         case EXIT_REASON_CPUID:
6757                 return 1;
6758         case EXIT_REASON_HLT:
6759                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6760         case EXIT_REASON_INVD:
6761                 return 1;
6762         case EXIT_REASON_INVLPG:
6763                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6764         case EXIT_REASON_RDPMC:
6765                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6766         case EXIT_REASON_RDTSC:
6767                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6768         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6769         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6770         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6771         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6772         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6773         case EXIT_REASON_INVEPT:
6774                 /*
6775                  * VMX instructions trap unconditionally. This allows L1 to
6776                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6777                  */
6778                 return 1;
6779         case EXIT_REASON_CR_ACCESS:
6780                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6781         case EXIT_REASON_DR_ACCESS:
6782                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6783         case EXIT_REASON_IO_INSTRUCTION:
6784                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6785         case EXIT_REASON_MSR_READ:
6786         case EXIT_REASON_MSR_WRITE:
6787                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6788         case EXIT_REASON_INVALID_STATE:
6789                 return 1;
6790         case EXIT_REASON_MWAIT_INSTRUCTION:
6791                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6792         case EXIT_REASON_MONITOR_INSTRUCTION:
6793                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6794         case EXIT_REASON_PAUSE_INSTRUCTION:
6795                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6796                         nested_cpu_has2(vmcs12,
6797                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6798         case EXIT_REASON_MCE_DURING_VMENTRY:
6799                 return 0;
6800         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6801                 return 1;
6802         case EXIT_REASON_APIC_ACCESS:
6803                 return nested_cpu_has2(vmcs12,
6804                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6805         case EXIT_REASON_EPT_VIOLATION:
6806                 /*
6807                  * L0 always deals with the EPT violation. If nested EPT is
6808                  * used, and the nested mmu code discovers that the address is
6809                  * missing in the guest EPT table (EPT12), the EPT violation
6810                  * will be injected with nested_ept_inject_page_fault()
6811                  */
6812                 return 0;
6813         case EXIT_REASON_EPT_MISCONFIG:
6814                 /*
6815                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6816                  * table (shadow on EPT) or a merged EPT table that L0 built
6817                  * (EPT on EPT). So any problems with the structure of the
6818                  * table is L0's fault.
6819                  */
6820                 return 0;
6821         case EXIT_REASON_WBINVD:
6822                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6823         case EXIT_REASON_XSETBV:
6824                 return 1;
6825         default:
6826                 return 1;
6827         }
6828 }
6829
6830 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6831 {
6832         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6833         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6834 }
6835
6836 /*
6837  * The guest has exited.  See if we can fix it or if we need userspace
6838  * assistance.
6839  */
6840 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6841 {
6842         struct vcpu_vmx *vmx = to_vmx(vcpu);
6843         u32 exit_reason = vmx->exit_reason;
6844         u32 vectoring_info = vmx->idt_vectoring_info;
6845
6846         /* If guest state is invalid, start emulating */
6847         if (vmx->emulation_required)
6848                 return handle_invalid_guest_state(vcpu);
6849
6850         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6851                 nested_vmx_vmexit(vcpu, exit_reason,
6852                                   vmcs_read32(VM_EXIT_INTR_INFO),
6853                                   vmcs_readl(EXIT_QUALIFICATION));
6854                 return 1;
6855         }
6856
6857         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6858                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6859                 vcpu->run->fail_entry.hardware_entry_failure_reason
6860                         = exit_reason;
6861                 return 0;
6862         }
6863
6864         if (unlikely(vmx->fail)) {
6865                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6866                 vcpu->run->fail_entry.hardware_entry_failure_reason
6867                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6868                 return 0;
6869         }
6870
6871         /*
6872          * Note:
6873          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6874          * delivery event since it indicates guest is accessing MMIO.
6875          * The vm-exit can be triggered again after return to guest that
6876          * will cause infinite loop.
6877          */
6878         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6879                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6880                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6881                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6882                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6883                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6884                 vcpu->run->internal.ndata = 2;
6885                 vcpu->run->internal.data[0] = vectoring_info;
6886                 vcpu->run->internal.data[1] = exit_reason;
6887                 return 0;
6888         }
6889
6890         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6891             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6892                                         get_vmcs12(vcpu))))) {
6893                 if (vmx_interrupt_allowed(vcpu)) {
6894                         vmx->soft_vnmi_blocked = 0;
6895                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6896                            vcpu->arch.nmi_pending) {
6897                         /*
6898                          * This CPU don't support us in finding the end of an
6899                          * NMI-blocked window if the guest runs with IRQs
6900                          * disabled. So we pull the trigger after 1 s of
6901                          * futile waiting, but inform the user about this.
6902                          */
6903                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6904                                "state on VCPU %d after 1 s timeout\n",
6905                                __func__, vcpu->vcpu_id);
6906                         vmx->soft_vnmi_blocked = 0;
6907                 }
6908         }
6909
6910         if (exit_reason < kvm_vmx_max_exit_handlers
6911             && kvm_vmx_exit_handlers[exit_reason])
6912                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6913         else {
6914                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6915                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6916         }
6917         return 0;
6918 }
6919
6920 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6921 {
6922         if (irr == -1 || tpr < irr) {
6923                 vmcs_write32(TPR_THRESHOLD, 0);
6924                 return;
6925         }
6926
6927         vmcs_write32(TPR_THRESHOLD, irr);
6928 }
6929
6930 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6931 {
6932         u32 sec_exec_control;
6933
6934         /*
6935          * There is not point to enable virtualize x2apic without enable
6936          * apicv
6937          */
6938         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6939                                 !vmx_vm_has_apicv(vcpu->kvm))
6940                 return;
6941
6942         if (!vm_need_tpr_shadow(vcpu->kvm))
6943                 return;
6944
6945         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6946
6947         if (set) {
6948                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6949                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6950         } else {
6951                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6952                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6953         }
6954         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6955
6956         vmx_set_msr_bitmap(vcpu);
6957 }
6958
6959 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6960 {
6961         u16 status;
6962         u8 old;
6963
6964         if (!vmx_vm_has_apicv(kvm))
6965                 return;
6966
6967         if (isr == -1)
6968                 isr = 0;
6969
6970         status = vmcs_read16(GUEST_INTR_STATUS);
6971         old = status >> 8;
6972         if (isr != old) {
6973                 status &= 0xff;
6974                 status |= isr << 8;
6975                 vmcs_write16(GUEST_INTR_STATUS, status);
6976         }
6977 }
6978
6979 static void vmx_set_rvi(int vector)
6980 {
6981         u16 status;
6982         u8 old;
6983
6984         status = vmcs_read16(GUEST_INTR_STATUS);
6985         old = (u8)status & 0xff;
6986         if ((u8)vector != old) {
6987                 status &= ~0xff;
6988                 status |= (u8)vector;
6989                 vmcs_write16(GUEST_INTR_STATUS, status);
6990         }
6991 }
6992
6993 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6994 {
6995         if (max_irr == -1)
6996                 return;
6997
6998         vmx_set_rvi(max_irr);
6999 }
7000
7001 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7002 {
7003         if (!vmx_vm_has_apicv(vcpu->kvm))
7004                 return;
7005
7006         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7007         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7008         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7009         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7010 }
7011
7012 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7013 {
7014         u32 exit_intr_info;
7015
7016         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7017               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7018                 return;
7019
7020         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7021         exit_intr_info = vmx->exit_intr_info;
7022
7023         /* Handle machine checks before interrupts are enabled */
7024         if (is_machine_check(exit_intr_info))
7025                 kvm_machine_check();
7026
7027         /* We need to handle NMIs before interrupts are enabled */
7028         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7029             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7030                 kvm_before_handle_nmi(&vmx->vcpu);
7031                 asm("int $2");
7032                 kvm_after_handle_nmi(&vmx->vcpu);
7033         }
7034 }
7035
7036 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7037 {
7038         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7039
7040         /*
7041          * If external interrupt exists, IF bit is set in rflags/eflags on the
7042          * interrupt stack frame, and interrupt will be enabled on a return
7043          * from interrupt handler.
7044          */
7045         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7046                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7047                 unsigned int vector;
7048                 unsigned long entry;
7049                 gate_desc *desc;
7050                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7051 #ifdef CONFIG_X86_64
7052                 unsigned long tmp;
7053 #endif
7054
7055                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7056                 desc = (gate_desc *)vmx->host_idt_base + vector;
7057                 entry = gate_offset(*desc);
7058                 asm volatile(
7059 #ifdef CONFIG_X86_64
7060                         "mov %%" _ASM_SP ", %[sp]\n\t"
7061                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7062                         "push $%c[ss]\n\t"
7063                         "push %[sp]\n\t"
7064 #endif
7065                         "pushf\n\t"
7066                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7067                         __ASM_SIZE(push) " $%c[cs]\n\t"
7068                         "call *%[entry]\n\t"
7069                         :
7070 #ifdef CONFIG_X86_64
7071                         [sp]"=&r"(tmp)
7072 #endif
7073                         :
7074                         [entry]"r"(entry),
7075                         [ss]"i"(__KERNEL_DS),
7076                         [cs]"i"(__KERNEL_CS)
7077                         );
7078         } else
7079                 local_irq_enable();
7080 }
7081
7082 static bool vmx_mpx_supported(void)
7083 {
7084         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7085                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7086 }
7087
7088 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7089 {
7090         u32 exit_intr_info;
7091         bool unblock_nmi;
7092         u8 vector;
7093         bool idtv_info_valid;
7094
7095         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7096
7097         if (cpu_has_virtual_nmis()) {
7098                 if (vmx->nmi_known_unmasked)
7099                         return;
7100                 /*
7101                  * Can't use vmx->exit_intr_info since we're not sure what
7102                  * the exit reason is.
7103                  */
7104                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7105                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7106                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7107                 /*
7108                  * SDM 3: 27.7.1.2 (September 2008)
7109                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7110                  * a guest IRET fault.
7111                  * SDM 3: 23.2.2 (September 2008)
7112                  * Bit 12 is undefined in any of the following cases:
7113                  *  If the VM exit sets the valid bit in the IDT-vectoring
7114                  *   information field.
7115                  *  If the VM exit is due to a double fault.
7116                  */
7117                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7118                     vector != DF_VECTOR && !idtv_info_valid)
7119                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7120                                       GUEST_INTR_STATE_NMI);
7121                 else
7122                         vmx->nmi_known_unmasked =
7123                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7124                                   & GUEST_INTR_STATE_NMI);
7125         } else if (unlikely(vmx->soft_vnmi_blocked))
7126                 vmx->vnmi_blocked_time +=
7127                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7128 }
7129
7130 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7131                                       u32 idt_vectoring_info,
7132                                       int instr_len_field,
7133                                       int error_code_field)
7134 {
7135         u8 vector;
7136         int type;
7137         bool idtv_info_valid;
7138
7139         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7140
7141         vcpu->arch.nmi_injected = false;
7142         kvm_clear_exception_queue(vcpu);
7143         kvm_clear_interrupt_queue(vcpu);
7144
7145         if (!idtv_info_valid)
7146                 return;
7147
7148         kvm_make_request(KVM_REQ_EVENT, vcpu);
7149
7150         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7151         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7152
7153         switch (type) {
7154         case INTR_TYPE_NMI_INTR:
7155                 vcpu->arch.nmi_injected = true;
7156                 /*
7157                  * SDM 3: 27.7.1.2 (September 2008)
7158                  * Clear bit "block by NMI" before VM entry if a NMI
7159                  * delivery faulted.
7160                  */
7161                 vmx_set_nmi_mask(vcpu, false);
7162                 break;
7163         case INTR_TYPE_SOFT_EXCEPTION:
7164                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7165                 /* fall through */
7166         case INTR_TYPE_HARD_EXCEPTION:
7167                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7168                         u32 err = vmcs_read32(error_code_field);
7169                         kvm_requeue_exception_e(vcpu, vector, err);
7170                 } else
7171                         kvm_requeue_exception(vcpu, vector);
7172                 break;
7173         case INTR_TYPE_SOFT_INTR:
7174                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7175                 /* fall through */
7176         case INTR_TYPE_EXT_INTR:
7177                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7178                 break;
7179         default:
7180                 break;
7181         }
7182 }
7183
7184 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7185 {
7186         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7187                                   VM_EXIT_INSTRUCTION_LEN,
7188                                   IDT_VECTORING_ERROR_CODE);
7189 }
7190
7191 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7192 {
7193         __vmx_complete_interrupts(vcpu,
7194                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7195                                   VM_ENTRY_INSTRUCTION_LEN,
7196                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7197
7198         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7199 }
7200
7201 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7202 {
7203         int i, nr_msrs;
7204         struct perf_guest_switch_msr *msrs;
7205
7206         msrs = perf_guest_get_msrs(&nr_msrs);
7207
7208         if (!msrs)
7209                 return;
7210
7211         for (i = 0; i < nr_msrs; i++)
7212                 if (msrs[i].host == msrs[i].guest)
7213                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7214                 else
7215                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7216                                         msrs[i].host);
7217 }
7218
7219 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7220 {
7221         struct vcpu_vmx *vmx = to_vmx(vcpu);
7222         unsigned long debugctlmsr;
7223
7224         /* Record the guest's net vcpu time for enforced NMI injections. */
7225         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7226                 vmx->entry_time = ktime_get();
7227
7228         /* Don't enter VMX if guest state is invalid, let the exit handler
7229            start emulation until we arrive back to a valid state */
7230         if (vmx->emulation_required)
7231                 return;
7232
7233         if (vmx->nested.sync_shadow_vmcs) {
7234                 copy_vmcs12_to_shadow(vmx);
7235                 vmx->nested.sync_shadow_vmcs = false;
7236         }
7237
7238         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7239                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7240         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7241                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7242
7243         /* When single-stepping over STI and MOV SS, we must clear the
7244          * corresponding interruptibility bits in the guest state. Otherwise
7245          * vmentry fails as it then expects bit 14 (BS) in pending debug
7246          * exceptions being set, but that's not correct for the guest debugging
7247          * case. */
7248         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7249                 vmx_set_interrupt_shadow(vcpu, 0);
7250
7251         atomic_switch_perf_msrs(vmx);
7252         debugctlmsr = get_debugctlmsr();
7253
7254         vmx->__launched = vmx->loaded_vmcs->launched;
7255         asm(
7256                 /* Store host registers */
7257                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7258                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7259                 "push %%" _ASM_CX " \n\t"
7260                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7261                 "je 1f \n\t"
7262                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7263                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7264                 "1: \n\t"
7265                 /* Reload cr2 if changed */
7266                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7267                 "mov %%cr2, %%" _ASM_DX " \n\t"
7268                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7269                 "je 2f \n\t"
7270                 "mov %%" _ASM_AX", %%cr2 \n\t"
7271                 "2: \n\t"
7272                 /* Check if vmlaunch of vmresume is needed */
7273                 "cmpl $0, %c[launched](%0) \n\t"
7274                 /* Load guest registers.  Don't clobber flags. */
7275                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7276                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7277                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7278                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7279                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7280                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7281 #ifdef CONFIG_X86_64
7282                 "mov %c[r8](%0),  %%r8  \n\t"
7283                 "mov %c[r9](%0),  %%r9  \n\t"
7284                 "mov %c[r10](%0), %%r10 \n\t"
7285                 "mov %c[r11](%0), %%r11 \n\t"
7286                 "mov %c[r12](%0), %%r12 \n\t"
7287                 "mov %c[r13](%0), %%r13 \n\t"
7288                 "mov %c[r14](%0), %%r14 \n\t"
7289                 "mov %c[r15](%0), %%r15 \n\t"
7290 #endif
7291                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7292
7293                 /* Enter guest mode */
7294                 "jne 1f \n\t"
7295                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7296                 "jmp 2f \n\t"
7297                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7298                 "2: "
7299                 /* Save guest registers, load host registers, keep flags */
7300                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7301                 "pop %0 \n\t"
7302                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7303                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7304                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7305                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7306                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7307                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7308                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7309 #ifdef CONFIG_X86_64
7310                 "mov %%r8,  %c[r8](%0) \n\t"
7311                 "mov %%r9,  %c[r9](%0) \n\t"
7312                 "mov %%r10, %c[r10](%0) \n\t"
7313                 "mov %%r11, %c[r11](%0) \n\t"
7314                 "mov %%r12, %c[r12](%0) \n\t"
7315                 "mov %%r13, %c[r13](%0) \n\t"
7316                 "mov %%r14, %c[r14](%0) \n\t"
7317                 "mov %%r15, %c[r15](%0) \n\t"
7318 #endif
7319                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7320                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7321
7322                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7323                 "setbe %c[fail](%0) \n\t"
7324                 ".pushsection .rodata \n\t"
7325                 ".global vmx_return \n\t"
7326                 "vmx_return: " _ASM_PTR " 2b \n\t"
7327                 ".popsection"
7328               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7329                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7330                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7331                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7332                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7333                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7334                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7335                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7336                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7337                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7338                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7339 #ifdef CONFIG_X86_64
7340                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7341                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7342                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7343                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7344                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7345                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7346                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7347                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7348 #endif
7349                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7350                 [wordsize]"i"(sizeof(ulong))
7351               : "cc", "memory"
7352 #ifdef CONFIG_X86_64
7353                 , "rax", "rbx", "rdi", "rsi"
7354                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7355 #else
7356                 , "eax", "ebx", "edi", "esi"
7357 #endif
7358               );
7359
7360         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7361         if (debugctlmsr)
7362                 update_debugctlmsr(debugctlmsr);
7363
7364 #ifndef CONFIG_X86_64
7365         /*
7366          * The sysexit path does not restore ds/es, so we must set them to
7367          * a reasonable value ourselves.
7368          *
7369          * We can't defer this to vmx_load_host_state() since that function
7370          * may be executed in interrupt context, which saves and restore segments
7371          * around it, nullifying its effect.
7372          */
7373         loadsegment(ds, __USER_DS);
7374         loadsegment(es, __USER_DS);
7375 #endif
7376
7377         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7378                                   | (1 << VCPU_EXREG_RFLAGS)
7379                                   | (1 << VCPU_EXREG_CPL)
7380                                   | (1 << VCPU_EXREG_PDPTR)
7381                                   | (1 << VCPU_EXREG_SEGMENTS)
7382                                   | (1 << VCPU_EXREG_CR3));
7383         vcpu->arch.regs_dirty = 0;
7384
7385         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7386
7387         vmx->loaded_vmcs->launched = 1;
7388
7389         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7390         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7391
7392         /*
7393          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7394          * we did not inject a still-pending event to L1 now because of
7395          * nested_run_pending, we need to re-enable this bit.
7396          */
7397         if (vmx->nested.nested_run_pending)
7398                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7399
7400         vmx->nested.nested_run_pending = 0;
7401
7402         vmx_complete_atomic_exit(vmx);
7403         vmx_recover_nmi_blocking(vmx);
7404         vmx_complete_interrupts(vmx);
7405 }
7406
7407 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7408 {
7409         struct vcpu_vmx *vmx = to_vmx(vcpu);
7410
7411         free_vpid(vmx);
7412         free_loaded_vmcs(vmx->loaded_vmcs);
7413         free_nested(vmx);
7414         kfree(vmx->guest_msrs);
7415         kvm_vcpu_uninit(vcpu);
7416         kmem_cache_free(kvm_vcpu_cache, vmx);
7417 }
7418
7419 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7420 {
7421         int err;
7422         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7423         int cpu;
7424
7425         if (!vmx)
7426                 return ERR_PTR(-ENOMEM);
7427
7428         allocate_vpid(vmx);
7429
7430         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7431         if (err)
7432                 goto free_vcpu;
7433
7434         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7435         err = -ENOMEM;
7436         if (!vmx->guest_msrs) {
7437                 goto uninit_vcpu;
7438         }
7439
7440         vmx->loaded_vmcs = &vmx->vmcs01;
7441         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7442         if (!vmx->loaded_vmcs->vmcs)
7443                 goto free_msrs;
7444         if (!vmm_exclusive)
7445                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7446         loaded_vmcs_init(vmx->loaded_vmcs);
7447         if (!vmm_exclusive)
7448                 kvm_cpu_vmxoff();
7449
7450         cpu = get_cpu();
7451         vmx_vcpu_load(&vmx->vcpu, cpu);
7452         vmx->vcpu.cpu = cpu;
7453         err = vmx_vcpu_setup(vmx);
7454         vmx_vcpu_put(&vmx->vcpu);
7455         put_cpu();
7456         if (err)
7457                 goto free_vmcs;
7458         if (vm_need_virtualize_apic_accesses(kvm)) {
7459                 err = alloc_apic_access_page(kvm);
7460                 if (err)
7461                         goto free_vmcs;
7462         }
7463
7464         if (enable_ept) {
7465                 if (!kvm->arch.ept_identity_map_addr)
7466                         kvm->arch.ept_identity_map_addr =
7467                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7468                 err = -ENOMEM;
7469                 if (alloc_identity_pagetable(kvm) != 0)
7470                         goto free_vmcs;
7471                 if (!init_rmode_identity_map(kvm))
7472                         goto free_vmcs;
7473         }
7474
7475         vmx->nested.current_vmptr = -1ull;
7476         vmx->nested.current_vmcs12 = NULL;
7477
7478         return &vmx->vcpu;
7479
7480 free_vmcs:
7481         free_loaded_vmcs(vmx->loaded_vmcs);
7482 free_msrs:
7483         kfree(vmx->guest_msrs);
7484 uninit_vcpu:
7485         kvm_vcpu_uninit(&vmx->vcpu);
7486 free_vcpu:
7487         free_vpid(vmx);
7488         kmem_cache_free(kvm_vcpu_cache, vmx);
7489         return ERR_PTR(err);
7490 }
7491
7492 static void __init vmx_check_processor_compat(void *rtn)
7493 {
7494         struct vmcs_config vmcs_conf;
7495
7496         *(int *)rtn = 0;
7497         if (setup_vmcs_config(&vmcs_conf) < 0)
7498                 *(int *)rtn = -EIO;
7499         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7500                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7501                                 smp_processor_id());
7502                 *(int *)rtn = -EIO;
7503         }
7504 }
7505
7506 static int get_ept_level(void)
7507 {
7508         return VMX_EPT_DEFAULT_GAW + 1;
7509 }
7510
7511 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7512 {
7513         u64 ret;
7514
7515         /* For VT-d and EPT combination
7516          * 1. MMIO: always map as UC
7517          * 2. EPT with VT-d:
7518          *   a. VT-d without snooping control feature: can't guarantee the
7519          *      result, try to trust guest.
7520          *   b. VT-d with snooping control feature: snooping control feature of
7521          *      VT-d engine can guarantee the cache correctness. Just set it
7522          *      to WB to keep consistent with host. So the same as item 3.
7523          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7524          *    consistent with host MTRR
7525          */
7526         if (is_mmio)
7527                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7528         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7529                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7530                       VMX_EPT_MT_EPTE_SHIFT;
7531         else
7532                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7533                         | VMX_EPT_IPAT_BIT;
7534
7535         return ret;
7536 }
7537
7538 static int vmx_get_lpage_level(void)
7539 {
7540         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7541                 return PT_DIRECTORY_LEVEL;
7542         else
7543                 /* For shadow and EPT supported 1GB page */
7544                 return PT_PDPE_LEVEL;
7545 }
7546
7547 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7548 {
7549         struct kvm_cpuid_entry2 *best;
7550         struct vcpu_vmx *vmx = to_vmx(vcpu);
7551         u32 exec_control;
7552
7553         vmx->rdtscp_enabled = false;
7554         if (vmx_rdtscp_supported()) {
7555                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7556                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7557                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7558                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7559                                 vmx->rdtscp_enabled = true;
7560                         else {
7561                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7562                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7563                                                 exec_control);
7564                         }
7565                 }
7566         }
7567
7568         /* Exposing INVPCID only when PCID is exposed */
7569         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7570         if (vmx_invpcid_supported() &&
7571             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7572             guest_cpuid_has_pcid(vcpu)) {
7573                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7574                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7575                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7576                              exec_control);
7577         } else {
7578                 if (cpu_has_secondary_exec_ctrls()) {
7579                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7580                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7581                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7582                                      exec_control);
7583                 }
7584                 if (best)
7585                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7586         }
7587 }
7588
7589 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7590 {
7591         if (func == 1 && nested)
7592                 entry->ecx |= bit(X86_FEATURE_VMX);
7593 }
7594
7595 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7596                 struct x86_exception *fault)
7597 {
7598         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7599         u32 exit_reason;
7600
7601         if (fault->error_code & PFERR_RSVD_MASK)
7602                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7603         else
7604                 exit_reason = EXIT_REASON_EPT_VIOLATION;
7605         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7606         vmcs12->guest_physical_address = fault->address;
7607 }
7608
7609 /* Callbacks for nested_ept_init_mmu_context: */
7610
7611 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7612 {
7613         /* return the page table to be shadowed - in our case, EPT12 */
7614         return get_vmcs12(vcpu)->ept_pointer;
7615 }
7616
7617 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7618 {
7619         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7620                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7621
7622         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7623         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7624         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7625
7626         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7627 }
7628
7629 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7630 {
7631         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7632 }
7633
7634 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7635                 struct x86_exception *fault)
7636 {
7637         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7638
7639         WARN_ON(!is_guest_mode(vcpu));
7640
7641         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7642         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7643                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7644                                   vmcs_read32(VM_EXIT_INTR_INFO),
7645                                   vmcs_readl(EXIT_QUALIFICATION));
7646         else
7647                 kvm_inject_page_fault(vcpu, fault);
7648 }
7649
7650 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7651 {
7652         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7653         struct vcpu_vmx *vmx = to_vmx(vcpu);
7654
7655         if (vcpu->arch.virtual_tsc_khz == 0)
7656                 return;
7657
7658         /* Make sure short timeouts reliably trigger an immediate vmexit.
7659          * hrtimer_start does not guarantee this. */
7660         if (preemption_timeout <= 1) {
7661                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7662                 return;
7663         }
7664
7665         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7666         preemption_timeout *= 1000000;
7667         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7668         hrtimer_start(&vmx->nested.preemption_timer,
7669                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7670 }
7671
7672 /*
7673  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7674  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7675  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7676  * guest in a way that will both be appropriate to L1's requests, and our
7677  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7678  * function also has additional necessary side-effects, like setting various
7679  * vcpu->arch fields.
7680  */
7681 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7682 {
7683         struct vcpu_vmx *vmx = to_vmx(vcpu);
7684         u32 exec_control;
7685
7686         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7687         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7688         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7689         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7690         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7691         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7692         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7693         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7694         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7695         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7696         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7697         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7698         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7699         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7700         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7701         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7702         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7703         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7704         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7705         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7706         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7707         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7708         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7709         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7710         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7711         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7712         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7713         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7714         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7715         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7716         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7717         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7718         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7719         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7720         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7721         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7722
7723         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7724         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7725                 vmcs12->vm_entry_intr_info_field);
7726         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7727                 vmcs12->vm_entry_exception_error_code);
7728         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7729                 vmcs12->vm_entry_instruction_len);
7730         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7731                 vmcs12->guest_interruptibility_info);
7732         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7733         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7734         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7735         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7736                 vmcs12->guest_pending_dbg_exceptions);
7737         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7738         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7739
7740         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7741
7742         exec_control = vmcs12->pin_based_vm_exec_control;
7743         exec_control |= vmcs_config.pin_based_exec_ctrl;
7744         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7745         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
7746
7747         vmx->nested.preemption_timer_expired = false;
7748         if (nested_cpu_has_preemption_timer(vmcs12))
7749                 vmx_start_preemption_timer(vcpu);
7750
7751         /*
7752          * Whether page-faults are trapped is determined by a combination of
7753          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7754          * If enable_ept, L0 doesn't care about page faults and we should
7755          * set all of these to L1's desires. However, if !enable_ept, L0 does
7756          * care about (at least some) page faults, and because it is not easy
7757          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7758          * to exit on each and every L2 page fault. This is done by setting
7759          * MASK=MATCH=0 and (see below) EB.PF=1.
7760          * Note that below we don't need special code to set EB.PF beyond the
7761          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7762          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7763          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7764          *
7765          * A problem with this approach (when !enable_ept) is that L1 may be
7766          * injected with more page faults than it asked for. This could have
7767          * caused problems, but in practice existing hypervisors don't care.
7768          * To fix this, we will need to emulate the PFEC checking (on the L1
7769          * page tables), using walk_addr(), when injecting PFs to L1.
7770          */
7771         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7772                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7773         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7774                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7775
7776         if (cpu_has_secondary_exec_ctrls()) {
7777                 exec_control = vmx_secondary_exec_control(vmx);
7778                 if (!vmx->rdtscp_enabled)
7779                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7780                 /* Take the following fields only from vmcs12 */
7781                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7782                 if (nested_cpu_has(vmcs12,
7783                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7784                         exec_control |= vmcs12->secondary_vm_exec_control;
7785
7786                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7787                         /*
7788                          * Translate L1 physical address to host physical
7789                          * address for vmcs02. Keep the page pinned, so this
7790                          * physical address remains valid. We keep a reference
7791                          * to it so we can release it later.
7792                          */
7793                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7794                                 nested_release_page(vmx->nested.apic_access_page);
7795                         vmx->nested.apic_access_page =
7796                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7797                         /*
7798                          * If translation failed, no matter: This feature asks
7799                          * to exit when accessing the given address, and if it
7800                          * can never be accessed, this feature won't do
7801                          * anything anyway.
7802                          */
7803                         if (!vmx->nested.apic_access_page)
7804                                 exec_control &=
7805                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7806                         else
7807                                 vmcs_write64(APIC_ACCESS_ADDR,
7808                                   page_to_phys(vmx->nested.apic_access_page));
7809                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7810                         exec_control |=
7811                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7812                         vmcs_write64(APIC_ACCESS_ADDR,
7813                                 page_to_phys(vcpu->kvm->arch.apic_access_page));
7814                 }
7815
7816                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7817         }
7818
7819
7820         /*
7821          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7822          * Some constant fields are set here by vmx_set_constant_host_state().
7823          * Other fields are different per CPU, and will be set later when
7824          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7825          */
7826         vmx_set_constant_host_state(vmx);
7827
7828         /*
7829          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7830          * entry, but only if the current (host) sp changed from the value
7831          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7832          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7833          * here we just force the write to happen on entry.
7834          */
7835         vmx->host_rsp = 0;
7836
7837         exec_control = vmx_exec_control(vmx); /* L0's desires */
7838         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7839         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7840         exec_control &= ~CPU_BASED_TPR_SHADOW;
7841         exec_control |= vmcs12->cpu_based_vm_exec_control;
7842         /*
7843          * Merging of IO and MSR bitmaps not currently supported.
7844          * Rather, exit every time.
7845          */
7846         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7847         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7848         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7849
7850         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7851
7852         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7853          * bitwise-or of what L1 wants to trap for L2, and what we want to
7854          * trap. Note that CR0.TS also needs updating - we do this later.
7855          */
7856         update_exception_bitmap(vcpu);
7857         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7858         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7859
7860         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7861          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7862          * bits are further modified by vmx_set_efer() below.
7863          */
7864         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7865
7866         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7867          * emulated by vmx_set_efer(), below.
7868          */
7869         vm_entry_controls_init(vmx,
7870                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7871                         ~VM_ENTRY_IA32E_MODE) |
7872                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7873
7874         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7875                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7876                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7877         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7878                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7879
7880
7881         set_cr4_guest_host_mask(vmx);
7882
7883         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7884                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7885
7886         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7887                 vmcs_write64(TSC_OFFSET,
7888                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7889         else
7890                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7891
7892         if (enable_vpid) {
7893                 /*
7894                  * Trivially support vpid by letting L2s share their parent
7895                  * L1's vpid. TODO: move to a more elaborate solution, giving
7896                  * each L2 its own vpid and exposing the vpid feature to L1.
7897                  */
7898                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7899                 vmx_flush_tlb(vcpu);
7900         }
7901
7902         if (nested_cpu_has_ept(vmcs12)) {
7903                 kvm_mmu_unload(vcpu);
7904                 nested_ept_init_mmu_context(vcpu);
7905         }
7906
7907         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7908                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7909         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7910                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7911         else
7912                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7913         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7914         vmx_set_efer(vcpu, vcpu->arch.efer);
7915
7916         /*
7917          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7918          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7919          * The CR0_READ_SHADOW is what L2 should have expected to read given
7920          * the specifications by L1; It's not enough to take
7921          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7922          * have more bits than L1 expected.
7923          */
7924         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7925         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7926
7927         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7928         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7929
7930         /* shadow page tables on either EPT or shadow page tables */
7931         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7932         kvm_mmu_reset_context(vcpu);
7933
7934         if (!enable_ept)
7935                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7936
7937         /*
7938          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7939          */
7940         if (enable_ept) {
7941                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7942                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7943                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7944                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7945         }
7946
7947         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7948         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7949 }
7950
7951 /*
7952  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7953  * for running an L2 nested guest.
7954  */
7955 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7956 {
7957         struct vmcs12 *vmcs12;
7958         struct vcpu_vmx *vmx = to_vmx(vcpu);
7959         int cpu;
7960         struct loaded_vmcs *vmcs02;
7961         bool ia32e;
7962
7963         if (!nested_vmx_check_permission(vcpu) ||
7964             !nested_vmx_check_vmcs12(vcpu))
7965                 return 1;
7966
7967         skip_emulated_instruction(vcpu);
7968         vmcs12 = get_vmcs12(vcpu);
7969
7970         if (enable_shadow_vmcs)
7971                 copy_shadow_to_vmcs12(vmx);
7972
7973         /*
7974          * The nested entry process starts with enforcing various prerequisites
7975          * on vmcs12 as required by the Intel SDM, and act appropriately when
7976          * they fail: As the SDM explains, some conditions should cause the
7977          * instruction to fail, while others will cause the instruction to seem
7978          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7979          * To speed up the normal (success) code path, we should avoid checking
7980          * for misconfigurations which will anyway be caught by the processor
7981          * when using the merged vmcs02.
7982          */
7983         if (vmcs12->launch_state == launch) {
7984                 nested_vmx_failValid(vcpu,
7985                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7986                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7987                 return 1;
7988         }
7989
7990         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7991             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
7992                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7993                 return 1;
7994         }
7995
7996         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7997                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7998                 /*TODO: Also verify bits beyond physical address width are 0*/
7999                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8000                 return 1;
8001         }
8002
8003         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8004                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8005                 /*TODO: Also verify bits beyond physical address width are 0*/
8006                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8007                 return 1;
8008         }
8009
8010         if (vmcs12->vm_entry_msr_load_count > 0 ||
8011             vmcs12->vm_exit_msr_load_count > 0 ||
8012             vmcs12->vm_exit_msr_store_count > 0) {
8013                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8014                                     __func__);
8015                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8016                 return 1;
8017         }
8018
8019         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8020               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8021             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8022               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8023             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8024               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8025             !vmx_control_verify(vmcs12->vm_exit_controls,
8026               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8027             !vmx_control_verify(vmcs12->vm_entry_controls,
8028               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8029         {
8030                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8031                 return 1;
8032         }
8033
8034         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8035             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8036                 nested_vmx_failValid(vcpu,
8037                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8038                 return 1;
8039         }
8040
8041         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8042             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8043                 nested_vmx_entry_failure(vcpu, vmcs12,
8044                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8045                 return 1;
8046         }
8047         if (vmcs12->vmcs_link_pointer != -1ull) {
8048                 nested_vmx_entry_failure(vcpu, vmcs12,
8049                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8050                 return 1;
8051         }
8052
8053         /*
8054          * If the load IA32_EFER VM-entry control is 1, the following checks
8055          * are performed on the field for the IA32_EFER MSR:
8056          * - Bits reserved in the IA32_EFER MSR must be 0.
8057          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8058          *   the IA-32e mode guest VM-exit control. It must also be identical
8059          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8060          *   CR0.PG) is 1.
8061          */
8062         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8063                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8064                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8065                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8066                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8067                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8068                         nested_vmx_entry_failure(vcpu, vmcs12,
8069                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8070                         return 1;
8071                 }
8072         }
8073
8074         /*
8075          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8076          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8077          * the values of the LMA and LME bits in the field must each be that of
8078          * the host address-space size VM-exit control.
8079          */
8080         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8081                 ia32e = (vmcs12->vm_exit_controls &
8082                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8083                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8084                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8085                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8086                         nested_vmx_entry_failure(vcpu, vmcs12,
8087                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8088                         return 1;
8089                 }
8090         }
8091
8092         /*
8093          * We're finally done with prerequisite checking, and can start with
8094          * the nested entry.
8095          */
8096
8097         vmcs02 = nested_get_current_vmcs02(vmx);
8098         if (!vmcs02)
8099                 return -ENOMEM;
8100
8101         enter_guest_mode(vcpu);
8102
8103         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8104
8105         cpu = get_cpu();
8106         vmx->loaded_vmcs = vmcs02;
8107         vmx_vcpu_put(vcpu);
8108         vmx_vcpu_load(vcpu, cpu);
8109         vcpu->cpu = cpu;
8110         put_cpu();
8111
8112         vmx_segment_cache_clear(vmx);
8113
8114         vmcs12->launch_state = 1;
8115
8116         prepare_vmcs02(vcpu, vmcs12);
8117
8118         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8119                 return kvm_emulate_halt(vcpu);
8120
8121         vmx->nested.nested_run_pending = 1;
8122
8123         /*
8124          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8125          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8126          * returned as far as L1 is concerned. It will only return (and set
8127          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8128          */
8129         return 1;
8130 }
8131
8132 /*
8133  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8134  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8135  * This function returns the new value we should put in vmcs12.guest_cr0.
8136  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8137  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8138  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8139  *     didn't trap the bit, because if L1 did, so would L0).
8140  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8141  *     been modified by L2, and L1 knows it. So just leave the old value of
8142  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8143  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8144  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8145  *     changed these bits, and therefore they need to be updated, but L0
8146  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8147  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8148  */
8149 static inline unsigned long
8150 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8151 {
8152         return
8153         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8154         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8155         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8156                         vcpu->arch.cr0_guest_owned_bits));
8157 }
8158
8159 static inline unsigned long
8160 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8161 {
8162         return
8163         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8164         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8165         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8166                         vcpu->arch.cr4_guest_owned_bits));
8167 }
8168
8169 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8170                                        struct vmcs12 *vmcs12)
8171 {
8172         u32 idt_vectoring;
8173         unsigned int nr;
8174
8175         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8176                 nr = vcpu->arch.exception.nr;
8177                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8178
8179                 if (kvm_exception_is_soft(nr)) {
8180                         vmcs12->vm_exit_instruction_len =
8181                                 vcpu->arch.event_exit_inst_len;
8182                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8183                 } else
8184                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8185
8186                 if (vcpu->arch.exception.has_error_code) {
8187                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8188                         vmcs12->idt_vectoring_error_code =
8189                                 vcpu->arch.exception.error_code;
8190                 }
8191
8192                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8193         } else if (vcpu->arch.nmi_injected) {
8194                 vmcs12->idt_vectoring_info_field =
8195                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8196         } else if (vcpu->arch.interrupt.pending) {
8197                 nr = vcpu->arch.interrupt.nr;
8198                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8199
8200                 if (vcpu->arch.interrupt.soft) {
8201                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8202                         vmcs12->vm_entry_instruction_len =
8203                                 vcpu->arch.event_exit_inst_len;
8204                 } else
8205                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8206
8207                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8208         }
8209 }
8210
8211 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8212 {
8213         struct vcpu_vmx *vmx = to_vmx(vcpu);
8214
8215         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8216             vmx->nested.preemption_timer_expired) {
8217                 if (vmx->nested.nested_run_pending)
8218                         return -EBUSY;
8219                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8220                 return 0;
8221         }
8222
8223         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8224                 if (vmx->nested.nested_run_pending ||
8225                     vcpu->arch.interrupt.pending)
8226                         return -EBUSY;
8227                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8228                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8229                                   INTR_INFO_VALID_MASK, 0);
8230                 /*
8231                  * The NMI-triggered VM exit counts as injection:
8232                  * clear this one and block further NMIs.
8233                  */
8234                 vcpu->arch.nmi_pending = 0;
8235                 vmx_set_nmi_mask(vcpu, true);
8236                 return 0;
8237         }
8238
8239         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8240             nested_exit_on_intr(vcpu)) {
8241                 if (vmx->nested.nested_run_pending)
8242                         return -EBUSY;
8243                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8244         }
8245
8246         return 0;
8247 }
8248
8249 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8250 {
8251         ktime_t remaining =
8252                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8253         u64 value;
8254
8255         if (ktime_to_ns(remaining) <= 0)
8256                 return 0;
8257
8258         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8259         do_div(value, 1000000);
8260         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8261 }
8262
8263 /*
8264  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8265  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8266  * and this function updates it to reflect the changes to the guest state while
8267  * L2 was running (and perhaps made some exits which were handled directly by L0
8268  * without going back to L1), and to reflect the exit reason.
8269  * Note that we do not have to copy here all VMCS fields, just those that
8270  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8271  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8272  * which already writes to vmcs12 directly.
8273  */
8274 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8275                            u32 exit_reason, u32 exit_intr_info,
8276                            unsigned long exit_qualification)
8277 {
8278         /* update guest state fields: */
8279         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8280         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8281
8282         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8283         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8284         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8285         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8286
8287         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8288         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8289         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8290         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8291         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8292         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8293         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8294         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8295         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8296         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8297         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8298         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8299         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8300         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8301         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8302         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8303         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8304         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8305         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8306         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8307         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8308         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8309         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8310         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8311         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8312         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8313         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8314         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8315         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8316         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8317         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8318         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8319         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8320         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8321         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8322         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8323
8324         vmcs12->guest_interruptibility_info =
8325                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8326         vmcs12->guest_pending_dbg_exceptions =
8327                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8328         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8329                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8330         else
8331                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8332
8333         if (nested_cpu_has_preemption_timer(vmcs12)) {
8334                 if (vmcs12->vm_exit_controls &
8335                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8336                         vmcs12->vmx_preemption_timer_value =
8337                                 vmx_get_preemption_timer_value(vcpu);
8338                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8339         }
8340
8341         /*
8342          * In some cases (usually, nested EPT), L2 is allowed to change its
8343          * own CR3 without exiting. If it has changed it, we must keep it.
8344          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8345          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8346          *
8347          * Additionally, restore L2's PDPTR to vmcs12.
8348          */
8349         if (enable_ept) {
8350                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8351                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8352                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8353                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8354                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8355         }
8356
8357         vmcs12->vm_entry_controls =
8358                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8359                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8360
8361         /* TODO: These cannot have changed unless we have MSR bitmaps and
8362          * the relevant bit asks not to trap the change */
8363         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8364         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8365                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8366         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8367                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8368         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8369         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8370         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8371         if (vmx_mpx_supported())
8372                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8373
8374         /* update exit information fields: */
8375
8376         vmcs12->vm_exit_reason = exit_reason;
8377         vmcs12->exit_qualification = exit_qualification;
8378
8379         vmcs12->vm_exit_intr_info = exit_intr_info;
8380         if ((vmcs12->vm_exit_intr_info &
8381              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8382             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8383                 vmcs12->vm_exit_intr_error_code =
8384                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8385         vmcs12->idt_vectoring_info_field = 0;
8386         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8387         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8388
8389         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8390                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8391                  * instead of reading the real value. */
8392                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8393
8394                 /*
8395                  * Transfer the event that L0 or L1 may wanted to inject into
8396                  * L2 to IDT_VECTORING_INFO_FIELD.
8397                  */
8398                 vmcs12_save_pending_event(vcpu, vmcs12);
8399         }
8400
8401         /*
8402          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8403          * preserved above and would only end up incorrectly in L1.
8404          */
8405         vcpu->arch.nmi_injected = false;
8406         kvm_clear_exception_queue(vcpu);
8407         kvm_clear_interrupt_queue(vcpu);
8408 }
8409
8410 /*
8411  * A part of what we need to when the nested L2 guest exits and we want to
8412  * run its L1 parent, is to reset L1's guest state to the host state specified
8413  * in vmcs12.
8414  * This function is to be called not only on normal nested exit, but also on
8415  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8416  * Failures During or After Loading Guest State").
8417  * This function should be called when the active VMCS is L1's (vmcs01).
8418  */
8419 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8420                                    struct vmcs12 *vmcs12)
8421 {
8422         struct kvm_segment seg;
8423
8424         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8425                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8426         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8427                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8428         else
8429                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8430         vmx_set_efer(vcpu, vcpu->arch.efer);
8431
8432         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8433         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8434         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8435         /*
8436          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8437          * actually changed, because it depends on the current state of
8438          * fpu_active (which may have changed).
8439          * Note that vmx_set_cr0 refers to efer set above.
8440          */
8441         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8442         /*
8443          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8444          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8445          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8446          */
8447         update_exception_bitmap(vcpu);
8448         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8449         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8450
8451         /*
8452          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8453          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8454          */
8455         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8456         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8457
8458         nested_ept_uninit_mmu_context(vcpu);
8459
8460         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8461         kvm_mmu_reset_context(vcpu);
8462
8463         if (!enable_ept)
8464                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8465
8466         if (enable_vpid) {
8467                 /*
8468                  * Trivially support vpid by letting L2s share their parent
8469                  * L1's vpid. TODO: move to a more elaborate solution, giving
8470                  * each L2 its own vpid and exposing the vpid feature to L1.
8471                  */
8472                 vmx_flush_tlb(vcpu);
8473         }
8474
8475
8476         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8477         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8478         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8479         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8480         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8481
8482         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
8483         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8484                 vmcs_write64(GUEST_BNDCFGS, 0);
8485
8486         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8487                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8488                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8489         }
8490         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8491                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8492                         vmcs12->host_ia32_perf_global_ctrl);
8493
8494         /* Set L1 segment info according to Intel SDM
8495             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8496         seg = (struct kvm_segment) {
8497                 .base = 0,
8498                 .limit = 0xFFFFFFFF,
8499                 .selector = vmcs12->host_cs_selector,
8500                 .type = 11,
8501                 .present = 1,
8502                 .s = 1,
8503                 .g = 1
8504         };
8505         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8506                 seg.l = 1;
8507         else
8508                 seg.db = 1;
8509         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8510         seg = (struct kvm_segment) {
8511                 .base = 0,
8512                 .limit = 0xFFFFFFFF,
8513                 .type = 3,
8514                 .present = 1,
8515                 .s = 1,
8516                 .db = 1,
8517                 .g = 1
8518         };
8519         seg.selector = vmcs12->host_ds_selector;
8520         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8521         seg.selector = vmcs12->host_es_selector;
8522         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8523         seg.selector = vmcs12->host_ss_selector;
8524         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8525         seg.selector = vmcs12->host_fs_selector;
8526         seg.base = vmcs12->host_fs_base;
8527         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8528         seg.selector = vmcs12->host_gs_selector;
8529         seg.base = vmcs12->host_gs_base;
8530         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8531         seg = (struct kvm_segment) {
8532                 .base = vmcs12->host_tr_base,
8533                 .limit = 0x67,
8534                 .selector = vmcs12->host_tr_selector,
8535                 .type = 11,
8536                 .present = 1
8537         };
8538         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8539
8540         kvm_set_dr(vcpu, 7, 0x400);
8541         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8542 }
8543
8544 /*
8545  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8546  * and modify vmcs12 to make it see what it would expect to see there if
8547  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8548  */
8549 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8550                               u32 exit_intr_info,
8551                               unsigned long exit_qualification)
8552 {
8553         struct vcpu_vmx *vmx = to_vmx(vcpu);
8554         int cpu;
8555         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8556
8557         /* trying to cancel vmlaunch/vmresume is a bug */
8558         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8559
8560         leave_guest_mode(vcpu);
8561         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8562                        exit_qualification);
8563
8564         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8565                                        vmcs12->exit_qualification,
8566                                        vmcs12->idt_vectoring_info_field,
8567                                        vmcs12->vm_exit_intr_info,
8568                                        vmcs12->vm_exit_intr_error_code,
8569                                        KVM_ISA_VMX);
8570
8571         cpu = get_cpu();
8572         vmx->loaded_vmcs = &vmx->vmcs01;
8573         vmx_vcpu_put(vcpu);
8574         vmx_vcpu_load(vcpu, cpu);
8575         vcpu->cpu = cpu;
8576         put_cpu();
8577
8578         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8579         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8580         vmx_segment_cache_clear(vmx);
8581
8582         /* if no vmcs02 cache requested, remove the one we used */
8583         if (VMCS02_POOL_SIZE == 0)
8584                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8585
8586         load_vmcs12_host_state(vcpu, vmcs12);
8587
8588         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8589         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8590
8591         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8592         vmx->host_rsp = 0;
8593
8594         /* Unpin physical memory we referred to in vmcs02 */
8595         if (vmx->nested.apic_access_page) {
8596                 nested_release_page(vmx->nested.apic_access_page);
8597                 vmx->nested.apic_access_page = 0;
8598         }
8599
8600         /*
8601          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8602          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8603          * success or failure flag accordingly.
8604          */
8605         if (unlikely(vmx->fail)) {
8606                 vmx->fail = 0;
8607                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8608         } else
8609                 nested_vmx_succeed(vcpu);
8610         if (enable_shadow_vmcs)
8611                 vmx->nested.sync_shadow_vmcs = true;
8612
8613         /* in case we halted in L2 */
8614         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8615 }
8616
8617 /*
8618  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8619  */
8620 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8621 {
8622         if (is_guest_mode(vcpu))
8623                 nested_vmx_vmexit(vcpu, -1, 0, 0);
8624         free_nested(to_vmx(vcpu));
8625 }
8626
8627 /*
8628  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8629  * 23.7 "VM-entry failures during or after loading guest state" (this also
8630  * lists the acceptable exit-reason and exit-qualification parameters).
8631  * It should only be called before L2 actually succeeded to run, and when
8632  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8633  */
8634 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8635                         struct vmcs12 *vmcs12,
8636                         u32 reason, unsigned long qualification)
8637 {
8638         load_vmcs12_host_state(vcpu, vmcs12);
8639         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8640         vmcs12->exit_qualification = qualification;
8641         nested_vmx_succeed(vcpu);
8642         if (enable_shadow_vmcs)
8643                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8644 }
8645
8646 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8647                                struct x86_instruction_info *info,
8648                                enum x86_intercept_stage stage)
8649 {
8650         return X86EMUL_CONTINUE;
8651 }
8652
8653 static struct kvm_x86_ops vmx_x86_ops = {
8654         .cpu_has_kvm_support = cpu_has_kvm_support,
8655         .disabled_by_bios = vmx_disabled_by_bios,
8656         .hardware_setup = hardware_setup,
8657         .hardware_unsetup = hardware_unsetup,
8658         .check_processor_compatibility = vmx_check_processor_compat,
8659         .hardware_enable = hardware_enable,
8660         .hardware_disable = hardware_disable,
8661         .cpu_has_accelerated_tpr = report_flexpriority,
8662
8663         .vcpu_create = vmx_create_vcpu,
8664         .vcpu_free = vmx_free_vcpu,
8665         .vcpu_reset = vmx_vcpu_reset,
8666
8667         .prepare_guest_switch = vmx_save_host_state,
8668         .vcpu_load = vmx_vcpu_load,
8669         .vcpu_put = vmx_vcpu_put,
8670
8671         .update_db_bp_intercept = update_exception_bitmap,
8672         .get_msr = vmx_get_msr,
8673         .set_msr = vmx_set_msr,
8674         .get_segment_base = vmx_get_segment_base,
8675         .get_segment = vmx_get_segment,
8676         .set_segment = vmx_set_segment,
8677         .get_cpl = vmx_get_cpl,
8678         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8679         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8680         .decache_cr3 = vmx_decache_cr3,
8681         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8682         .set_cr0 = vmx_set_cr0,
8683         .set_cr3 = vmx_set_cr3,
8684         .set_cr4 = vmx_set_cr4,
8685         .set_efer = vmx_set_efer,
8686         .get_idt = vmx_get_idt,
8687         .set_idt = vmx_set_idt,
8688         .get_gdt = vmx_get_gdt,
8689         .set_gdt = vmx_set_gdt,
8690         .get_dr6 = vmx_get_dr6,
8691         .set_dr6 = vmx_set_dr6,
8692         .set_dr7 = vmx_set_dr7,
8693         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
8694         .cache_reg = vmx_cache_reg,
8695         .get_rflags = vmx_get_rflags,
8696         .set_rflags = vmx_set_rflags,
8697         .fpu_activate = vmx_fpu_activate,
8698         .fpu_deactivate = vmx_fpu_deactivate,
8699
8700         .tlb_flush = vmx_flush_tlb,
8701
8702         .run = vmx_vcpu_run,
8703         .handle_exit = vmx_handle_exit,
8704         .skip_emulated_instruction = skip_emulated_instruction,
8705         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8706         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8707         .patch_hypercall = vmx_patch_hypercall,
8708         .set_irq = vmx_inject_irq,
8709         .set_nmi = vmx_inject_nmi,
8710         .queue_exception = vmx_queue_exception,
8711         .cancel_injection = vmx_cancel_injection,
8712         .interrupt_allowed = vmx_interrupt_allowed,
8713         .nmi_allowed = vmx_nmi_allowed,
8714         .get_nmi_mask = vmx_get_nmi_mask,
8715         .set_nmi_mask = vmx_set_nmi_mask,
8716         .enable_nmi_window = enable_nmi_window,
8717         .enable_irq_window = enable_irq_window,
8718         .update_cr8_intercept = update_cr8_intercept,
8719         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8720         .vm_has_apicv = vmx_vm_has_apicv,
8721         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8722         .hwapic_irr_update = vmx_hwapic_irr_update,
8723         .hwapic_isr_update = vmx_hwapic_isr_update,
8724         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8725         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8726
8727         .set_tss_addr = vmx_set_tss_addr,
8728         .get_tdp_level = get_ept_level,
8729         .get_mt_mask = vmx_get_mt_mask,
8730
8731         .get_exit_info = vmx_get_exit_info,
8732
8733         .get_lpage_level = vmx_get_lpage_level,
8734
8735         .cpuid_update = vmx_cpuid_update,
8736
8737         .rdtscp_supported = vmx_rdtscp_supported,
8738         .invpcid_supported = vmx_invpcid_supported,
8739
8740         .set_supported_cpuid = vmx_set_supported_cpuid,
8741
8742         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8743
8744         .set_tsc_khz = vmx_set_tsc_khz,
8745         .read_tsc_offset = vmx_read_tsc_offset,
8746         .write_tsc_offset = vmx_write_tsc_offset,
8747         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8748         .compute_tsc_offset = vmx_compute_tsc_offset,
8749         .read_l1_tsc = vmx_read_l1_tsc,
8750
8751         .set_tdp_cr3 = vmx_set_cr3,
8752
8753         .check_intercept = vmx_check_intercept,
8754         .handle_external_intr = vmx_handle_external_intr,
8755         .mpx_supported = vmx_mpx_supported,
8756
8757         .check_nested_events = vmx_check_nested_events,
8758 };
8759
8760 static int __init vmx_init(void)
8761 {
8762         int r, i, msr;
8763
8764         rdmsrl_safe(MSR_EFER, &host_efer);
8765
8766         for (i = 0; i < NR_VMX_MSR; ++i)
8767                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8768
8769         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8770         if (!vmx_io_bitmap_a)
8771                 return -ENOMEM;
8772
8773         r = -ENOMEM;
8774
8775         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8776         if (!vmx_io_bitmap_b)
8777                 goto out;
8778
8779         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8780         if (!vmx_msr_bitmap_legacy)
8781                 goto out1;
8782
8783         vmx_msr_bitmap_legacy_x2apic =
8784                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8785         if (!vmx_msr_bitmap_legacy_x2apic)
8786                 goto out2;
8787
8788         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8789         if (!vmx_msr_bitmap_longmode)
8790                 goto out3;
8791
8792         vmx_msr_bitmap_longmode_x2apic =
8793                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8794         if (!vmx_msr_bitmap_longmode_x2apic)
8795                 goto out4;
8796         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8797         if (!vmx_vmread_bitmap)
8798                 goto out5;
8799
8800         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8801         if (!vmx_vmwrite_bitmap)
8802                 goto out6;
8803
8804         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8805         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8806         /* shadowed read/write fields */
8807         for (i = 0; i < max_shadow_read_write_fields; i++) {
8808                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8809                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8810         }
8811         /* shadowed read only fields */
8812         for (i = 0; i < max_shadow_read_only_fields; i++)
8813                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8814
8815         /*
8816          * Allow direct access to the PC debug port (it is often used for I/O
8817          * delays, but the vmexits simply slow things down).
8818          */
8819         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8820         clear_bit(0x80, vmx_io_bitmap_a);
8821
8822         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8823
8824         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8825         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8826
8827         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8828
8829         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8830                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8831         if (r)
8832                 goto out7;
8833
8834 #ifdef CONFIG_KEXEC
8835         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8836                            crash_vmclear_local_loaded_vmcss);
8837 #endif
8838
8839         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8840         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8841         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8842         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8843         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8844         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8845         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8846
8847         memcpy(vmx_msr_bitmap_legacy_x2apic,
8848                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8849         memcpy(vmx_msr_bitmap_longmode_x2apic,
8850                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8851
8852         if (enable_apicv) {
8853                 for (msr = 0x800; msr <= 0x8ff; msr++)
8854                         vmx_disable_intercept_msr_read_x2apic(msr);
8855
8856                 /* According SDM, in x2apic mode, the whole id reg is used.
8857                  * But in KVM, it only use the highest eight bits. Need to
8858                  * intercept it */
8859                 vmx_enable_intercept_msr_read_x2apic(0x802);
8860                 /* TMCCT */
8861                 vmx_enable_intercept_msr_read_x2apic(0x839);
8862                 /* TPR */
8863                 vmx_disable_intercept_msr_write_x2apic(0x808);
8864                 /* EOI */
8865                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8866                 /* SELF-IPI */
8867                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8868         }
8869
8870         if (enable_ept) {
8871                 kvm_mmu_set_mask_ptes(0ull,
8872                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8873                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8874                         0ull, VMX_EPT_EXECUTABLE_MASK);
8875                 ept_set_mmio_spte_mask();
8876                 kvm_enable_tdp();
8877         } else
8878                 kvm_disable_tdp();
8879
8880         return 0;
8881
8882 out7:
8883         free_page((unsigned long)vmx_vmwrite_bitmap);
8884 out6:
8885         free_page((unsigned long)vmx_vmread_bitmap);
8886 out5:
8887         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8888 out4:
8889         free_page((unsigned long)vmx_msr_bitmap_longmode);
8890 out3:
8891         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8892 out2:
8893         free_page((unsigned long)vmx_msr_bitmap_legacy);
8894 out1:
8895         free_page((unsigned long)vmx_io_bitmap_b);
8896 out:
8897         free_page((unsigned long)vmx_io_bitmap_a);
8898         return r;
8899 }
8900
8901 static void __exit vmx_exit(void)
8902 {
8903         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8904         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8905         free_page((unsigned long)vmx_msr_bitmap_legacy);
8906         free_page((unsigned long)vmx_msr_bitmap_longmode);
8907         free_page((unsigned long)vmx_io_bitmap_b);
8908         free_page((unsigned long)vmx_io_bitmap_a);
8909         free_page((unsigned long)vmx_vmwrite_bitmap);
8910         free_page((unsigned long)vmx_vmread_bitmap);
8911
8912 #ifdef CONFIG_KEXEC
8913         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8914         synchronize_rcu();
8915 #endif
8916
8917         kvm_exit();
8918 }
8919
8920 module_init(vmx_init)
8921 module_exit(vmx_exit)