arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affilates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34
  35 #include <asm/virtext.h>
  36 #include "trace.h"
  37
  38 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  39
  40 MODULE_AUTHOR("Qumranet");
  41 MODULE_LICENSE("GPL");
  42
  43 #define IOPM_ALLOC_ORDER 2
  44 #define MSRPM_ALLOC_ORDER 1
  45
  46 #define SEG_TYPE_LDT 2
  47 #define SEG_TYPE_BUSY_TSS16 3
  48
  49 #define SVM_FEATURE_NPT            (1 <<  0)
  50 #define SVM_FEATURE_LBRV           (1 <<  1)
  51 #define SVM_FEATURE_SVML           (1 <<  2)
  52 #define SVM_FEATURE_NRIP           (1 <<  3)
  53 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  54
  55 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  56 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  57 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  58
  59 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  60
  61 static bool erratum_383_found __read_mostly;
  62
  63 static const u32 host_save_user_msrs[] = {
  64 #ifdef CONFIG_X86_64
  65         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  66         MSR_FS_BASE,
  67 #endif
  68         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  69 };
  70
  71 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  72
  73 struct kvm_vcpu;
  74
  75 struct nested_state {
  76         struct vmcb *hsave;
  77         u64 hsave_msr;
  78         u64 vm_cr_msr;
  79         u64 vmcb;
  80
  81         /* These are the merged vectors */
  82         u32 *msrpm;
  83
  84         /* gpa pointers to the real vectors */
  85         u64 vmcb_msrpm;
  86         u64 vmcb_iopm;
  87
  88         /* A VMEXIT is required but not yet emulated */
  89         bool exit_required;
  90
  91         /* cache for intercepts of the guest */
  92         u16 intercept_cr_read;
  93         u16 intercept_cr_write;
  94         u16 intercept_dr_read;
  95         u16 intercept_dr_write;
  96         u32 intercept_exceptions;
  97         u64 intercept;
  98
  99 };
 100
 101 #define MSRPM_OFFSETS   16
 102 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 103
 104 struct vcpu_svm {
 105         struct kvm_vcpu vcpu;
 106         struct vmcb *vmcb;
 107         unsigned long vmcb_pa;
 108         struct svm_cpu_data *svm_data;
 109         uint64_t asid_generation;
 110         uint64_t sysenter_esp;
 111         uint64_t sysenter_eip;
 112
 113         u64 next_rip;
 114
 115         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 116         u64 host_gs_base;
 117
 118         u32 *msrpm;
 119
 120         struct nested_state nested;
 121
 122         bool nmi_singlestep;
 123
 124         unsigned int3_injected;
 125         unsigned long int3_rip;
 126 };
 127
 128 #define MSR_INVALID                     0xffffffffU
 129
 130 static struct svm_direct_access_msrs {
 131         u32 index;   /* Index of the MSR */
 132         bool always; /* True if intercept is always on */
 133 } direct_access_msrs[] = {
 134         { .index = MSR_STAR,                            .always = true  },
 135         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 136 #ifdef CONFIG_X86_64
 137         { .index = MSR_GS_BASE,                         .always = true  },
 138         { .index = MSR_FS_BASE,                         .always = true  },
 139         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 140         { .index = MSR_LSTAR,                           .always = true  },
 141         { .index = MSR_CSTAR,                           .always = true  },
 142         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 143 #endif
 144         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 145         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 146         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 147         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 148         { .index = MSR_INVALID,                         .always = false },
 149 };
 150
 151 /* enable NPT for AMD64 and X86 with PAE */
 152 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 153 static bool npt_enabled = true;
 154 #else
 155 static bool npt_enabled;
 156 #endif
 157 static int npt = 1;
 158
 159 module_param(npt, int, S_IRUGO);
 160
 161 static int nested = 1;
 162 module_param(nested, int, S_IRUGO);
 163
 164 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 165 static void svm_complete_interrupts(struct vcpu_svm *svm);
 166
 167 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 168 static int nested_svm_intercept(struct vcpu_svm *svm);
 169 static int nested_svm_vmexit(struct vcpu_svm *svm);
 170 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 171                                       bool has_error_code, u32 error_code);
 172
 173 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 174 {
 175         return container_of(vcpu, struct vcpu_svm, vcpu);
 176 }
 177
 178 static inline bool is_nested(struct vcpu_svm *svm)
 179 {
 180         return svm->nested.vmcb;
 181 }
 182
 183 static inline void enable_gif(struct vcpu_svm *svm)
 184 {
 185         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 186 }
 187
 188 static inline void disable_gif(struct vcpu_svm *svm)
 189 {
 190         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 191 }
 192
 193 static inline bool gif_set(struct vcpu_svm *svm)
 194 {
 195         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 196 }
 197
 198 static unsigned long iopm_base;
 199
 200 struct kvm_ldttss_desc {
 201         u16 limit0;
 202         u16 base0;
 203         unsigned base1:8, type:5, dpl:2, p:1;
 204         unsigned limit1:4, zero0:3, g:1, base2:8;
 205         u32 base3;
 206         u32 zero1;
 207 } __attribute__((packed));
 208
 209 struct svm_cpu_data {
 210         int cpu;
 211
 212         u64 asid_generation;
 213         u32 max_asid;
 214         u32 next_asid;
 215         struct kvm_ldttss_desc *tss_desc;
 216
 217         struct page *save_area;
 218 };
 219
 220 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 221 static uint32_t svm_features;
 222
 223 struct svm_init_data {
 224         int cpu;
 225         int r;
 226 };
 227
 228 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 229
 230 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 231 #define MSRS_RANGE_SIZE 2048
 232 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 233
 234 static u32 svm_msrpm_offset(u32 msr)
 235 {
 236         u32 offset;
 237         int i;
 238
 239         for (i = 0; i < NUM_MSR_MAPS; i++) {
 240                 if (msr < msrpm_ranges[i] ||
 241                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 242                         continue;
 243
 244                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 245                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 246
 247                 /* Now we have the u8 offset - but need the u32 offset */
 248                 return offset / 4;
 249         }
 250
 251         /* MSR not in any range */
 252         return MSR_INVALID;
 253 }
 254
 255 #define MAX_INST_SIZE 15
 256
 257 static inline u32 svm_has(u32 feat)
 258 {
 259         return svm_features & feat;
 260 }
 261
 262 static inline void clgi(void)
 263 {
 264         asm volatile (__ex(SVM_CLGI));
 265 }
 266
 267 static inline void stgi(void)
 268 {
 269         asm volatile (__ex(SVM_STGI));
 270 }
 271
 272 static inline void invlpga(unsigned long addr, u32 asid)
 273 {
 274         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 275 }
 276
 277 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 278 {
 279         to_svm(vcpu)->asid_generation--;
 280 }
 281
 282 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 283 {
 284         force_new_asid(vcpu);
 285 }
 286
 287 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 288 {
 289         vcpu->arch.efer = efer;
 290         if (!npt_enabled && !(efer & EFER_LMA))
 291                 efer &= ~EFER_LME;
 292
 293         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 294 }
 295
 296 static int is_external_interrupt(u32 info)
 297 {
 298         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 299         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 300 }
 301
 302 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 303 {
 304         struct vcpu_svm *svm = to_svm(vcpu);
 305         u32 ret = 0;
 306
 307         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 308                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 309         return ret & mask;
 310 }
 311
 312 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 313 {
 314         struct vcpu_svm *svm = to_svm(vcpu);
 315
 316         if (mask == 0)
 317                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 318         else
 319                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 320
 321 }
 322
 323 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 324 {
 325         struct vcpu_svm *svm = to_svm(vcpu);
 326
 327         if (svm->vmcb->control.next_rip != 0)
 328                 svm->next_rip = svm->vmcb->control.next_rip;
 329
 330         if (!svm->next_rip) {
 331                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 332                                 EMULATE_DONE)
 333                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 334                 return;
 335         }
 336         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 337                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 338                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 339
 340         kvm_rip_write(vcpu, svm->next_rip);
 341         svm_set_interrupt_shadow(vcpu, 0);
 342 }
 343
 344 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 345                                 bool has_error_code, u32 error_code,
 346                                 bool reinject)
 347 {
 348         struct vcpu_svm *svm = to_svm(vcpu);
 349
 350         /*
 351          * If we are within a nested VM we'd better #VMEXIT and let the guest
 352          * handle the exception
 353          */
 354         if (!reinject &&
 355             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 356                 return;
 357
 358         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 359                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 360
 361                 /*
 362                  * For guest debugging where we have to reinject #BP if some
 363                  * INT3 is guest-owned:
 364                  * Emulate nRIP by moving RIP forward. Will fail if injection
 365                  * raises a fault that is not intercepted. Still better than
 366                  * failing in all cases.
 367                  */
 368                 skip_emulated_instruction(&svm->vcpu);
 369                 rip = kvm_rip_read(&svm->vcpu);
 370                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 371                 svm->int3_injected = rip - old_rip;
 372         }
 373
 374         svm->vmcb->control.event_inj = nr
 375                 | SVM_EVTINJ_VALID
 376                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 377                 | SVM_EVTINJ_TYPE_EXEPT;
 378         svm->vmcb->control.event_inj_err = error_code;
 379 }
 380
 381 static void svm_init_erratum_383(void)
 382 {
 383         u32 low, high;
 384         int err;
 385         u64 val;
 386
 387         if (!cpu_has_amd_erratum(amd_erratum_383))
 388                 return;
 389
 390         /* Use _safe variants to not break nested virtualization */
 391         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 392         if (err)
 393                 return;
 394
 395         val |= (1ULL << 47);
 396
 397         low  = lower_32_bits(val);
 398         high = upper_32_bits(val);
 399
 400         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 401
 402         erratum_383_found = true;
 403 }
 404
 405 static int has_svm(void)
 406 {
 407         const char *msg;
 408
 409         if (!cpu_has_svm(&msg)) {
 410                 printk(KERN_INFO "has_svm: %s\n", msg);
 411                 return 0;
 412         }
 413
 414         return 1;
 415 }
 416
 417 static void svm_hardware_disable(void *garbage)
 418 {
 419         cpu_svm_disable();
 420 }
 421
 422 static int svm_hardware_enable(void *garbage)
 423 {
 424
 425         struct svm_cpu_data *sd;
 426         uint64_t efer;
 427         struct desc_ptr gdt_descr;
 428         struct desc_struct *gdt;
 429         int me = raw_smp_processor_id();
 430
 431         rdmsrl(MSR_EFER, efer);
 432         if (efer & EFER_SVME)
 433                 return -EBUSY;
 434
 435         if (!has_svm()) {
 436                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 437                        me);
 438                 return -EINVAL;
 439         }
 440         sd = per_cpu(svm_data, me);
 441
 442         if (!sd) {
 443                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 444                        me);
 445                 return -EINVAL;
 446         }
 447
 448         sd->asid_generation = 1;
 449         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 450         sd->next_asid = sd->max_asid + 1;
 451
 452         native_store_gdt(&gdt_descr);
 453         gdt = (struct desc_struct *)gdt_descr.address;
 454         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 455
 456         wrmsrl(MSR_EFER, efer | EFER_SVME);
 457
 458         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 459
 460         svm_init_erratum_383();
 461
 462         return 0;
 463 }
 464
 465 static void svm_cpu_uninit(int cpu)
 466 {
 467         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 468
 469         if (!sd)
 470                 return;
 471
 472         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 473         __free_page(sd->save_area);
 474         kfree(sd);
 475 }
 476
 477 static int svm_cpu_init(int cpu)
 478 {
 479         struct svm_cpu_data *sd;
 480         int r;
 481
 482         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 483         if (!sd)
 484                 return -ENOMEM;
 485         sd->cpu = cpu;
 486         sd->save_area = alloc_page(GFP_KERNEL);
 487         r = -ENOMEM;
 488         if (!sd->save_area)
 489                 goto err_1;
 490
 491         per_cpu(svm_data, cpu) = sd;
 492
 493         return 0;
 494
 495 err_1:
 496         kfree(sd);
 497         return r;
 498
 499 }
 500
 501 static bool valid_msr_intercept(u32 index)
 502 {
 503         int i;
 504
 505         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 506                 if (direct_access_msrs[i].index == index)
 507                         return true;
 508
 509         return false;
 510 }
 511
 512 static void set_msr_interception(u32 *msrpm, unsigned msr,
 513                                  int read, int write)
 514 {
 515         u8 bit_read, bit_write;
 516         unsigned long tmp;
 517         u32 offset;
 518
 519         /*
 520          * If this warning triggers extend the direct_access_msrs list at the
 521          * beginning of the file
 522          */
 523         WARN_ON(!valid_msr_intercept(msr));
 524
 525         offset    = svm_msrpm_offset(msr);
 526         bit_read  = 2 * (msr & 0x0f);
 527         bit_write = 2 * (msr & 0x0f) + 1;
 528         tmp       = msrpm[offset];
 529
 530         BUG_ON(offset == MSR_INVALID);
 531
 532         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 533         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 534
 535         msrpm[offset] = tmp;
 536 }
 537
 538 static void svm_vcpu_init_msrpm(u32 *msrpm)
 539 {
 540         int i;
 541
 542         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 543
 544         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 545                 if (!direct_access_msrs[i].always)
 546                         continue;
 547
 548                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 549         }
 550 }
 551
 552 static void add_msr_offset(u32 offset)
 553 {
 554         int i;
 555
 556         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 557
 558                 /* Offset already in list? */
 559                 if (msrpm_offsets[i] == offset)
 560                         return;
 561
 562                 /* Slot used by another offset? */
 563                 if (msrpm_offsets[i] != MSR_INVALID)
 564                         continue;
 565
 566                 /* Add offset to list */
 567                 msrpm_offsets[i] = offset;
 568
 569                 return;
 570         }
 571
 572         /*
 573          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 574          * increase MSRPM_OFFSETS in this case.
 575          */
 576         BUG();
 577 }
 578
 579 static void init_msrpm_offsets(void)
 580 {
 581         int i;
 582
 583         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 584
 585         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 586                 u32 offset;
 587
 588                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 589                 BUG_ON(offset == MSR_INVALID);
 590
 591                 add_msr_offset(offset);
 592         }
 593 }
 594
 595 static void svm_enable_lbrv(struct vcpu_svm *svm)
 596 {
 597         u32 *msrpm = svm->msrpm;
 598
 599         svm->vmcb->control.lbr_ctl = 1;
 600         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 601         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 602         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 603         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 604 }
 605
 606 static void svm_disable_lbrv(struct vcpu_svm *svm)
 607 {
 608         u32 *msrpm = svm->msrpm;
 609
 610         svm->vmcb->control.lbr_ctl = 0;
 611         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 612         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 613         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 614         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 615 }
 616
 617 static __init int svm_hardware_setup(void)
 618 {
 619         int cpu;
 620         struct page *iopm_pages;
 621         void *iopm_va;
 622         int r;
 623
 624         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 625
 626         if (!iopm_pages)
 627                 return -ENOMEM;
 628
 629         iopm_va = page_address(iopm_pages);
 630         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 631         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 632
 633         init_msrpm_offsets();
 634
 635         if (boot_cpu_has(X86_FEATURE_NX))
 636                 kvm_enable_efer_bits(EFER_NX);
 637
 638         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 639                 kvm_enable_efer_bits(EFER_FFXSR);
 640
 641         if (nested) {
 642                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 643                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 644         }
 645
 646         for_each_possible_cpu(cpu) {
 647                 r = svm_cpu_init(cpu);
 648                 if (r)
 649                         goto err;
 650         }
 651
 652         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 653
 654         if (!svm_has(SVM_FEATURE_NPT))
 655                 npt_enabled = false;
 656
 657         if (npt_enabled && !npt) {
 658                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 659                 npt_enabled = false;
 660         }
 661
 662         if (npt_enabled) {
 663                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 664                 kvm_enable_tdp();
 665         } else
 666                 kvm_disable_tdp();
 667
 668         return 0;
 669
 670 err:
 671         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 672         iopm_base = 0;
 673         return r;
 674 }
 675
 676 static __exit void svm_hardware_unsetup(void)
 677 {
 678         int cpu;
 679
 680         for_each_possible_cpu(cpu)
 681                 svm_cpu_uninit(cpu);
 682
 683         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 684         iopm_base = 0;
 685 }
 686
 687 static void init_seg(struct vmcb_seg *seg)
 688 {
 689         seg->selector = 0;
 690         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 691                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 692         seg->limit = 0xffff;
 693         seg->base = 0;
 694 }
 695
 696 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 697 {
 698         seg->selector = 0;
 699         seg->attrib = SVM_SELECTOR_P_MASK | type;
 700         seg->limit = 0xffff;
 701         seg->base = 0;
 702 }
 703
 704 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 705 {
 706         struct vcpu_svm *svm = to_svm(vcpu);
 707         u64 g_tsc_offset = 0;
 708
 709         if (is_nested(svm)) {
 710                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 711                                svm->nested.hsave->control.tsc_offset;
 712                 svm->nested.hsave->control.tsc_offset = offset;
 713         }
 714
 715         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 716 }
 717
 718 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
 719 {
 720         struct vcpu_svm *svm = to_svm(vcpu);
 721
 722         svm->vmcb->control.tsc_offset += adjustment;
 723         if (is_nested(svm))
 724                 svm->nested.hsave->control.tsc_offset += adjustment;
 725 }
 726
 727 static void init_vmcb(struct vcpu_svm *svm)
 728 {
 729         struct vmcb_control_area *control = &svm->vmcb->control;
 730         struct vmcb_save_area *save = &svm->vmcb->save;
 731
 732         svm->vcpu.fpu_active = 1;
 733
 734         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 735                                         INTERCEPT_CR3_MASK |
 736                                         INTERCEPT_CR4_MASK;
 737
 738         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 739                                         INTERCEPT_CR3_MASK |
 740                                         INTERCEPT_CR4_MASK |
 741                                         INTERCEPT_CR8_MASK;
 742
 743         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 744                                         INTERCEPT_DR1_MASK |
 745                                         INTERCEPT_DR2_MASK |
 746                                         INTERCEPT_DR3_MASK |
 747                                         INTERCEPT_DR4_MASK |
 748                                         INTERCEPT_DR5_MASK |
 749                                         INTERCEPT_DR6_MASK |
 750                                         INTERCEPT_DR7_MASK;
 751
 752         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 753                                         INTERCEPT_DR1_MASK |
 754                                         INTERCEPT_DR2_MASK |
 755                                         INTERCEPT_DR3_MASK |
 756                                         INTERCEPT_DR4_MASK |
 757                                         INTERCEPT_DR5_MASK |
 758                                         INTERCEPT_DR6_MASK |
 759                                         INTERCEPT_DR7_MASK;
 760
 761         control->intercept_exceptions = (1 << PF_VECTOR) |
 762                                         (1 << UD_VECTOR) |
 763                                         (1 << MC_VECTOR);
 764
 765
 766         control->intercept =    (1ULL << INTERCEPT_INTR) |
 767                                 (1ULL << INTERCEPT_NMI) |
 768                                 (1ULL << INTERCEPT_SMI) |
 769                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 770                                 (1ULL << INTERCEPT_CPUID) |
 771                                 (1ULL << INTERCEPT_INVD) |
 772                                 (1ULL << INTERCEPT_HLT) |
 773                                 (1ULL << INTERCEPT_INVLPG) |
 774                                 (1ULL << INTERCEPT_INVLPGA) |
 775                                 (1ULL << INTERCEPT_IOIO_PROT) |
 776                                 (1ULL << INTERCEPT_MSR_PROT) |
 777                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 778                                 (1ULL << INTERCEPT_SHUTDOWN) |
 779                                 (1ULL << INTERCEPT_VMRUN) |
 780                                 (1ULL << INTERCEPT_VMMCALL) |
 781                                 (1ULL << INTERCEPT_VMLOAD) |
 782                                 (1ULL << INTERCEPT_VMSAVE) |
 783                                 (1ULL << INTERCEPT_STGI) |
 784                                 (1ULL << INTERCEPT_CLGI) |
 785                                 (1ULL << INTERCEPT_SKINIT) |
 786                                 (1ULL << INTERCEPT_WBINVD) |
 787                                 (1ULL << INTERCEPT_MONITOR) |
 788                                 (1ULL << INTERCEPT_MWAIT);
 789
 790         control->iopm_base_pa = iopm_base;
 791         control->msrpm_base_pa = __pa(svm->msrpm);
 792         control->int_ctl = V_INTR_MASKING_MASK;
 793
 794         init_seg(&save->es);
 795         init_seg(&save->ss);
 796         init_seg(&save->ds);
 797         init_seg(&save->fs);
 798         init_seg(&save->gs);
 799
 800         save->cs.selector = 0xf000;
 801         /* Executable/Readable Code Segment */
 802         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 803                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 804         save->cs.limit = 0xffff;
 805         /*
 806          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 807          * be consistent with it.
 808          *
 809          * Replace when we have real mode working for vmx.
 810          */
 811         save->cs.base = 0xf0000;
 812
 813         save->gdtr.limit = 0xffff;
 814         save->idtr.limit = 0xffff;
 815
 816         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 817         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 818
 819         svm_set_efer(&svm->vcpu, 0);
 820         save->dr6 = 0xffff0ff0;
 821         save->dr7 = 0x400;
 822         save->rflags = 2;
 823         save->rip = 0x0000fff0;
 824         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 825
 826         /*
 827          * This is the guest-visible cr0 value.
 828          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 829          */
 830         svm->vcpu.arch.cr0 = 0;
 831         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
 832
 833         save->cr4 = X86_CR4_PAE;
 834         /* rdx = ?? */
 835
 836         if (npt_enabled) {
 837                 /* Setup VMCB for Nested Paging */
 838                 control->nested_ctl = 1;
 839                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 840                                         (1ULL << INTERCEPT_INVLPG));
 841                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 842                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 843                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 844                 save->g_pat = 0x0007040600070406ULL;
 845                 save->cr3 = 0;
 846                 save->cr4 = 0;
 847         }
 848         force_new_asid(&svm->vcpu);
 849
 850         svm->nested.vmcb = 0;
 851         svm->vcpu.arch.hflags = 0;
 852
 853         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 854                 control->pause_filter_count = 3000;
 855                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 856         }
 857
 858         enable_gif(svm);
 859 }
 860
 861 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 862 {
 863         struct vcpu_svm *svm = to_svm(vcpu);
 864
 865         init_vmcb(svm);
 866
 867         if (!kvm_vcpu_is_bsp(vcpu)) {
 868                 kvm_rip_write(vcpu, 0);
 869                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 870                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 871         }
 872         vcpu->arch.regs_avail = ~0;
 873         vcpu->arch.regs_dirty = ~0;
 874
 875         return 0;
 876 }
 877
 878 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 879 {
 880         struct vcpu_svm *svm;
 881         struct page *page;
 882         struct page *msrpm_pages;
 883         struct page *hsave_page;
 884         struct page *nested_msrpm_pages;
 885         int err;
 886
 887         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 888         if (!svm) {
 889                 err = -ENOMEM;
 890                 goto out;
 891         }
 892
 893         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 894         if (err)
 895                 goto free_svm;
 896
 897         err = -ENOMEM;
 898         page = alloc_page(GFP_KERNEL);
 899         if (!page)
 900                 goto uninit;
 901
 902         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 903         if (!msrpm_pages)
 904                 goto free_page1;
 905
 906         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 907         if (!nested_msrpm_pages)
 908                 goto free_page2;
 909
 910         hsave_page = alloc_page(GFP_KERNEL);
 911         if (!hsave_page)
 912                 goto free_page3;
 913
 914         svm->nested.hsave = page_address(hsave_page);
 915
 916         svm->msrpm = page_address(msrpm_pages);
 917         svm_vcpu_init_msrpm(svm->msrpm);
 918
 919         svm->nested.msrpm = page_address(nested_msrpm_pages);
 920         svm_vcpu_init_msrpm(svm->nested.msrpm);
 921
 922         svm->vmcb = page_address(page);
 923         clear_page(svm->vmcb);
 924         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 925         svm->asid_generation = 0;
 926         init_vmcb(svm);
 927         kvm_write_tsc(&svm->vcpu, 0);
 928
 929         err = fx_init(&svm->vcpu);
 930         if (err)
 931                 goto free_page4;
 932
 933         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 934         if (kvm_vcpu_is_bsp(&svm->vcpu))
 935                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 936
 937         return &svm->vcpu;
 938
 939 free_page4:
 940         __free_page(hsave_page);
 941 free_page3:
 942         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 943 free_page2:
 944         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 945 free_page1:
 946         __free_page(page);
 947 uninit:
 948         kvm_vcpu_uninit(&svm->vcpu);
 949 free_svm:
 950         kmem_cache_free(kvm_vcpu_cache, svm);
 951 out:
 952         return ERR_PTR(err);
 953 }
 954
 955 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 956 {
 957         struct vcpu_svm *svm = to_svm(vcpu);
 958
 959         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 960         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 961         __free_page(virt_to_page(svm->nested.hsave));
 962         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 963         kvm_vcpu_uninit(vcpu);
 964         kmem_cache_free(kvm_vcpu_cache, svm);
 965 }
 966
 967 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 968 {
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970         int i;
 971
 972         if (unlikely(cpu != vcpu->cpu)) {
 973                 svm->asid_generation = 0;
 974         }
 975
 976         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 977                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 978 }
 979
 980 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 981 {
 982         struct vcpu_svm *svm = to_svm(vcpu);
 983         int i;
 984
 985         ++vcpu->stat.host_state_reload;
 986         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 987                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 988 }
 989
 990 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 991 {
 992         return to_svm(vcpu)->vmcb->save.rflags;
 993 }
 994
 995 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 996 {
 997         to_svm(vcpu)->vmcb->save.rflags = rflags;
 998 }
 999
1000 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1001 {
1002         switch (reg) {
1003         case VCPU_EXREG_PDPTR:
1004                 BUG_ON(!npt_enabled);
1005                 load_pdptrs(vcpu, vcpu->arch.cr3);
1006                 break;
1007         default:
1008                 BUG();
1009         }
1010 }
1011
1012 static void svm_set_vintr(struct vcpu_svm *svm)
1013 {
1014         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1015 }
1016
1017 static void svm_clear_vintr(struct vcpu_svm *svm)
1018 {
1019         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1020 }
1021
1022 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1023 {
1024         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1025
1026         switch (seg) {
1027         case VCPU_SREG_CS: return &save->cs;
1028         case VCPU_SREG_DS: return &save->ds;
1029         case VCPU_SREG_ES: return &save->es;
1030         case VCPU_SREG_FS: return &save->fs;
1031         case VCPU_SREG_GS: return &save->gs;
1032         case VCPU_SREG_SS: return &save->ss;
1033         case VCPU_SREG_TR: return &save->tr;
1034         case VCPU_SREG_LDTR: return &save->ldtr;
1035         }
1036         BUG();
1037         return NULL;
1038 }
1039
1040 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1041 {
1042         struct vmcb_seg *s = svm_seg(vcpu, seg);
1043
1044         return s->base;
1045 }
1046
1047 static void svm_get_segment(struct kvm_vcpu *vcpu,
1048                             struct kvm_segment *var, int seg)
1049 {
1050         struct vmcb_seg *s = svm_seg(vcpu, seg);
1051
1052         var->base = s->base;
1053         var->limit = s->limit;
1054         var->selector = s->selector;
1055         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1056         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1057         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1058         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1059         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1060         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1061         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1062         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1063
1064         /*
1065          * AMD's VMCB does not have an explicit unusable field, so emulate it
1066          * for cross vendor migration purposes by "not present"
1067          */
1068         var->unusable = !var->present || (var->type == 0);
1069
1070         switch (seg) {
1071         case VCPU_SREG_CS:
1072                 /*
1073                  * SVM always stores 0 for the 'G' bit in the CS selector in
1074                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1075                  * Intel's VMENTRY has a check on the 'G' bit.
1076                  */
1077                 var->g = s->limit > 0xfffff;
1078                 break;
1079         case VCPU_SREG_TR:
1080                 /*
1081                  * Work around a bug where the busy flag in the tr selector
1082                  * isn't exposed
1083                  */
1084                 var->type |= 0x2;
1085                 break;
1086         case VCPU_SREG_DS:
1087         case VCPU_SREG_ES:
1088         case VCPU_SREG_FS:
1089         case VCPU_SREG_GS:
1090                 /*
1091                  * The accessed bit must always be set in the segment
1092                  * descriptor cache, although it can be cleared in the
1093                  * descriptor, the cached bit always remains at 1. Since
1094                  * Intel has a check on this, set it here to support
1095                  * cross-vendor migration.
1096                  */
1097                 if (!var->unusable)
1098                         var->type |= 0x1;
1099                 break;
1100         case VCPU_SREG_SS:
1101                 /*
1102                  * On AMD CPUs sometimes the DB bit in the segment
1103                  * descriptor is left as 1, although the whole segment has
1104                  * been made unusable. Clear it here to pass an Intel VMX
1105                  * entry check when cross vendor migrating.
1106                  */
1107                 if (var->unusable)
1108                         var->db = 0;
1109                 break;
1110         }
1111 }
1112
1113 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1114 {
1115         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1116
1117         return save->cpl;
1118 }
1119
1120 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1121 {
1122         struct vcpu_svm *svm = to_svm(vcpu);
1123
1124         dt->size = svm->vmcb->save.idtr.limit;
1125         dt->address = svm->vmcb->save.idtr.base;
1126 }
1127
1128 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1129 {
1130         struct vcpu_svm *svm = to_svm(vcpu);
1131
1132         svm->vmcb->save.idtr.limit = dt->size;
1133         svm->vmcb->save.idtr.base = dt->address ;
1134 }
1135
1136 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1137 {
1138         struct vcpu_svm *svm = to_svm(vcpu);
1139
1140         dt->size = svm->vmcb->save.gdtr.limit;
1141         dt->address = svm->vmcb->save.gdtr.base;
1142 }
1143
1144 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1145 {
1146         struct vcpu_svm *svm = to_svm(vcpu);
1147
1148         svm->vmcb->save.gdtr.limit = dt->size;
1149         svm->vmcb->save.gdtr.base = dt->address ;
1150 }
1151
1152 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1153 {
1154 }
1155
1156 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1157 {
1158 }
1159
1160 static void update_cr0_intercept(struct vcpu_svm *svm)
1161 {
1162         struct vmcb *vmcb = svm->vmcb;
1163         ulong gcr0 = svm->vcpu.arch.cr0;
1164         u64 *hcr0 = &svm->vmcb->save.cr0;
1165
1166         if (!svm->vcpu.fpu_active)
1167                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1168         else
1169                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1170                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1171
1172
1173         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1174                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1175                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1176                 if (is_nested(svm)) {
1177                         struct vmcb *hsave = svm->nested.hsave;
1178
1179                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1180                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1181                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1182                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1183                 }
1184         } else {
1185                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1186                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1187                 if (is_nested(svm)) {
1188                         struct vmcb *hsave = svm->nested.hsave;
1189
1190                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1191                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1192                 }
1193         }
1194 }
1195
1196 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1197 {
1198         struct vcpu_svm *svm = to_svm(vcpu);
1199
1200         if (is_nested(svm)) {
1201                 /*
1202                  * We are here because we run in nested mode, the host kvm
1203                  * intercepts cr0 writes but the l1 hypervisor does not.
1204                  * But the L1 hypervisor may intercept selective cr0 writes.
1205                  * This needs to be checked here.
1206                  */
1207                 unsigned long old, new;
1208
1209                 /* Remove bits that would trigger a real cr0 write intercept */
1210                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1211                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1212
1213                 if (old == new) {
1214                         /* cr0 write with ts and mp unchanged */
1215                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1216                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1217                                 return;
1218                 }
1219         }
1220
1221 #ifdef CONFIG_X86_64
1222         if (vcpu->arch.efer & EFER_LME) {
1223                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1224                         vcpu->arch.efer |= EFER_LMA;
1225                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1226                 }
1227
1228                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1229                         vcpu->arch.efer &= ~EFER_LMA;
1230                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1231                 }
1232         }
1233 #endif
1234         vcpu->arch.cr0 = cr0;
1235
1236         if (!npt_enabled)
1237                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1238
1239         if (!vcpu->fpu_active)
1240                 cr0 |= X86_CR0_TS;
1241         /*
1242          * re-enable caching here because the QEMU bios
1243          * does not do it - this results in some delay at
1244          * reboot
1245          */
1246         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1247         svm->vmcb->save.cr0 = cr0;
1248         update_cr0_intercept(svm);
1249 }
1250
1251 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1252 {
1253         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1254         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1255
1256         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1257                 force_new_asid(vcpu);
1258
1259         vcpu->arch.cr4 = cr4;
1260         if (!npt_enabled)
1261                 cr4 |= X86_CR4_PAE;
1262         cr4 |= host_cr4_mce;
1263         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1264 }
1265
1266 static void svm_set_segment(struct kvm_vcpu *vcpu,
1267                             struct kvm_segment *var, int seg)
1268 {
1269         struct vcpu_svm *svm = to_svm(vcpu);
1270         struct vmcb_seg *s = svm_seg(vcpu, seg);
1271
1272         s->base = var->base;
1273         s->limit = var->limit;
1274         s->selector = var->selector;
1275         if (var->unusable)
1276                 s->attrib = 0;
1277         else {
1278                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1279                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1280                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1281                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1282                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1283                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1284                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1285                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1286         }
1287         if (seg == VCPU_SREG_CS)
1288                 svm->vmcb->save.cpl
1289                         = (svm->vmcb->save.cs.attrib
1290                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1291
1292 }
1293
1294 static void update_db_intercept(struct kvm_vcpu *vcpu)
1295 {
1296         struct vcpu_svm *svm = to_svm(vcpu);
1297
1298         svm->vmcb->control.intercept_exceptions &=
1299                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1300
1301         if (svm->nmi_singlestep)
1302                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1303
1304         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1305                 if (vcpu->guest_debug &
1306                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1307                         svm->vmcb->control.intercept_exceptions |=
1308                                 1 << DB_VECTOR;
1309                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1310                         svm->vmcb->control.intercept_exceptions |=
1311                                 1 << BP_VECTOR;
1312         } else
1313                 vcpu->guest_debug = 0;
1314 }
1315
1316 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1317 {
1318         struct vcpu_svm *svm = to_svm(vcpu);
1319
1320         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1321                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1322         else
1323                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1324
1325         update_db_intercept(vcpu);
1326 }
1327
1328 static void load_host_msrs(struct kvm_vcpu *vcpu)
1329 {
1330 #ifdef CONFIG_X86_64
1331         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1332 #endif
1333 }
1334
1335 static void save_host_msrs(struct kvm_vcpu *vcpu)
1336 {
1337 #ifdef CONFIG_X86_64
1338         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1339 #endif
1340 }
1341
1342 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1343 {
1344         if (sd->next_asid > sd->max_asid) {
1345                 ++sd->asid_generation;
1346                 sd->next_asid = 1;
1347                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1348         }
1349
1350         svm->asid_generation = sd->asid_generation;
1351         svm->vmcb->control.asid = sd->next_asid++;
1352 }
1353
1354 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1355 {
1356         struct vcpu_svm *svm = to_svm(vcpu);
1357
1358         svm->vmcb->save.dr7 = value;
1359 }
1360
1361 static int pf_interception(struct vcpu_svm *svm)
1362 {
1363         u64 fault_address;
1364         u32 error_code;
1365
1366         fault_address  = svm->vmcb->control.exit_info_2;
1367         error_code = svm->vmcb->control.exit_info_1;
1368
1369         trace_kvm_page_fault(fault_address, error_code);
1370         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1371                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1372         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1373 }
1374
1375 static int db_interception(struct vcpu_svm *svm)
1376 {
1377         struct kvm_run *kvm_run = svm->vcpu.run;
1378
1379         if (!(svm->vcpu.guest_debug &
1380               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1381                 !svm->nmi_singlestep) {
1382                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1383                 return 1;
1384         }
1385
1386         if (svm->nmi_singlestep) {
1387                 svm->nmi_singlestep = false;
1388                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1389                         svm->vmcb->save.rflags &=
1390                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1391                 update_db_intercept(&svm->vcpu);
1392         }
1393
1394         if (svm->vcpu.guest_debug &
1395             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1396                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1397                 kvm_run->debug.arch.pc =
1398                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1399                 kvm_run->debug.arch.exception = DB_VECTOR;
1400                 return 0;
1401         }
1402
1403         return 1;
1404 }
1405
1406 static int bp_interception(struct vcpu_svm *svm)
1407 {
1408         struct kvm_run *kvm_run = svm->vcpu.run;
1409
1410         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1411         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1412         kvm_run->debug.arch.exception = BP_VECTOR;
1413         return 0;
1414 }
1415
1416 static int ud_interception(struct vcpu_svm *svm)
1417 {
1418         int er;
1419
1420         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1421         if (er != EMULATE_DONE)
1422                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1423         return 1;
1424 }
1425
1426 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1427 {
1428         struct vcpu_svm *svm = to_svm(vcpu);
1429         u32 excp;
1430
1431         if (is_nested(svm)) {
1432                 u32 h_excp, n_excp;
1433
1434                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1435                 n_excp  = svm->nested.intercept_exceptions;
1436                 h_excp &= ~(1 << NM_VECTOR);
1437                 excp    = h_excp | n_excp;
1438         } else {
1439                 excp  = svm->vmcb->control.intercept_exceptions;
1440                 excp &= ~(1 << NM_VECTOR);
1441         }
1442
1443         svm->vmcb->control.intercept_exceptions = excp;
1444
1445         svm->vcpu.fpu_active = 1;
1446         update_cr0_intercept(svm);
1447 }
1448
1449 static int nm_interception(struct vcpu_svm *svm)
1450 {
1451         svm_fpu_activate(&svm->vcpu);
1452         return 1;
1453 }
1454
1455 static bool is_erratum_383(void)
1456 {
1457         int err, i;
1458         u64 value;
1459
1460         if (!erratum_383_found)
1461                 return false;
1462
1463         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1464         if (err)
1465                 return false;
1466
1467         /* Bit 62 may or may not be set for this mce */
1468         value &= ~(1ULL << 62);
1469
1470         if (value != 0xb600000000010015ULL)
1471                 return false;
1472
1473         /* Clear MCi_STATUS registers */
1474         for (i = 0; i < 6; ++i)
1475                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1476
1477         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1478         if (!err) {
1479                 u32 low, high;
1480
1481                 value &= ~(1ULL << 2);
1482                 low    = lower_32_bits(value);
1483                 high   = upper_32_bits(value);
1484
1485                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1486         }
1487
1488         /* Flush tlb to evict multi-match entries */
1489         __flush_tlb_all();
1490
1491         return true;
1492 }
1493
1494 static void svm_handle_mce(struct vcpu_svm *svm)
1495 {
1496         if (is_erratum_383()) {
1497                 /*
1498                  * Erratum 383 triggered. Guest state is corrupt so kill the
1499                  * guest.
1500                  */
1501                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1502
1503                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1504
1505                 return;
1506         }
1507
1508         /*
1509          * On an #MC intercept the MCE handler is not called automatically in
1510          * the host. So do it by hand here.
1511          */
1512         asm volatile (
1513                 "int $0x12\n");
1514         /* not sure if we ever come back to this point */
1515
1516         return;
1517 }
1518
1519 static int mc_interception(struct vcpu_svm *svm)
1520 {
1521         return 1;
1522 }
1523
1524 static int shutdown_interception(struct vcpu_svm *svm)
1525 {
1526         struct kvm_run *kvm_run = svm->vcpu.run;
1527
1528         /*
1529          * VMCB is undefined after a SHUTDOWN intercept
1530          * so reinitialize it.
1531          */
1532         clear_page(svm->vmcb);
1533         init_vmcb(svm);
1534
1535         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1536         return 0;
1537 }
1538
1539 static int io_interception(struct vcpu_svm *svm)
1540 {
1541         struct kvm_vcpu *vcpu = &svm->vcpu;
1542         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1543         int size, in, string;
1544         unsigned port;
1545
1546         ++svm->vcpu.stat.io_exits;
1547         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1548         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1549         if (string || in)
1550                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1551
1552         port = io_info >> 16;
1553         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1554         svm->next_rip = svm->vmcb->control.exit_info_2;
1555         skip_emulated_instruction(&svm->vcpu);
1556
1557         return kvm_fast_pio_out(vcpu, size, port);
1558 }
1559
1560 static int nmi_interception(struct vcpu_svm *svm)
1561 {
1562         return 1;
1563 }
1564
1565 static int intr_interception(struct vcpu_svm *svm)
1566 {
1567         ++svm->vcpu.stat.irq_exits;
1568         return 1;
1569 }
1570
1571 static int nop_on_interception(struct vcpu_svm *svm)
1572 {
1573         return 1;
1574 }
1575
1576 static int halt_interception(struct vcpu_svm *svm)
1577 {
1578         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1579         skip_emulated_instruction(&svm->vcpu);
1580         return kvm_emulate_halt(&svm->vcpu);
1581 }
1582
1583 static int vmmcall_interception(struct vcpu_svm *svm)
1584 {
1585         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1586         skip_emulated_instruction(&svm->vcpu);
1587         kvm_emulate_hypercall(&svm->vcpu);
1588         return 1;
1589 }
1590
1591 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1592 {
1593         if (!(svm->vcpu.arch.efer & EFER_SVME)
1594             || !is_paging(&svm->vcpu)) {
1595                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1596                 return 1;
1597         }
1598
1599         if (svm->vmcb->save.cpl) {
1600                 kvm_inject_gp(&svm->vcpu, 0);
1601                 return 1;
1602         }
1603
1604        return 0;
1605 }
1606
1607 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1608                                       bool has_error_code, u32 error_code)
1609 {
1610         int vmexit;
1611
1612         if (!is_nested(svm))
1613                 return 0;
1614
1615         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1616         svm->vmcb->control.exit_code_hi = 0;
1617         svm->vmcb->control.exit_info_1 = error_code;
1618         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1619
1620         vmexit = nested_svm_intercept(svm);
1621         if (vmexit == NESTED_EXIT_DONE)
1622                 svm->nested.exit_required = true;
1623
1624         return vmexit;
1625 }
1626
1627 /* This function returns true if it is save to enable the irq window */
1628 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1629 {
1630         if (!is_nested(svm))
1631                 return true;
1632
1633         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1634                 return true;
1635
1636         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1637                 return false;
1638
1639         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1640         svm->vmcb->control.exit_info_1 = 0;
1641         svm->vmcb->control.exit_info_2 = 0;
1642
1643         if (svm->nested.intercept & 1ULL) {
1644                 /*
1645                  * The #vmexit can't be emulated here directly because this
1646                  * code path runs with irqs and preemtion disabled. A
1647                  * #vmexit emulation might sleep. Only signal request for
1648                  * the #vmexit here.
1649                  */
1650                 svm->nested.exit_required = true;
1651                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1652                 return false;
1653         }
1654
1655         return true;
1656 }
1657
1658 /* This function returns true if it is save to enable the nmi window */
1659 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1660 {
1661         if (!is_nested(svm))
1662                 return true;
1663
1664         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1665                 return true;
1666
1667         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1668         svm->nested.exit_required = true;
1669
1670         return false;
1671 }
1672
1673 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1674 {
1675         struct page *page;
1676
1677         might_sleep();
1678
1679         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1680         if (is_error_page(page))
1681                 goto error;
1682
1683         *_page = page;
1684
1685         return kmap(page);
1686
1687 error:
1688         kvm_release_page_clean(page);
1689         kvm_inject_gp(&svm->vcpu, 0);
1690
1691         return NULL;
1692 }
1693
1694 static void nested_svm_unmap(struct page *page)
1695 {
1696         kunmap(page);
1697         kvm_release_page_dirty(page);
1698 }
1699
1700 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1701 {
1702         unsigned port;
1703         u8 val, bit;
1704         u64 gpa;
1705
1706         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1707                 return NESTED_EXIT_HOST;
1708
1709         port = svm->vmcb->control.exit_info_1 >> 16;
1710         gpa  = svm->nested.vmcb_iopm + (port / 8);
1711         bit  = port % 8;
1712         val  = 0;
1713
1714         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1715                 val &= (1 << bit);
1716
1717         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1718 }
1719
1720 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1721 {
1722         u32 offset, msr, value;
1723         int write, mask;
1724
1725         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1726                 return NESTED_EXIT_HOST;
1727
1728         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1729         offset = svm_msrpm_offset(msr);
1730         write  = svm->vmcb->control.exit_info_1 & 1;
1731         mask   = 1 << ((2 * (msr & 0xf)) + write);
1732
1733         if (offset == MSR_INVALID)
1734                 return NESTED_EXIT_DONE;
1735
1736         /* Offset is in 32 bit units but need in 8 bit units */
1737         offset *= 4;
1738
1739         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1740                 return NESTED_EXIT_DONE;
1741
1742         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1743 }
1744
1745 static int nested_svm_exit_special(struct vcpu_svm *svm)
1746 {
1747         u32 exit_code = svm->vmcb->control.exit_code;
1748
1749         switch (exit_code) {
1750         case SVM_EXIT_INTR:
1751         case SVM_EXIT_NMI:
1752         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1753                 return NESTED_EXIT_HOST;
1754         case SVM_EXIT_NPF:
1755                 /* For now we are always handling NPFs when using them */
1756                 if (npt_enabled)
1757                         return NESTED_EXIT_HOST;
1758                 break;
1759         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1760                 /* When we're shadowing, trap PFs */
1761                 if (!npt_enabled)
1762                         return NESTED_EXIT_HOST;
1763                 break;
1764         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1765                 nm_interception(svm);
1766                 break;
1767         default:
1768                 break;
1769         }
1770
1771         return NESTED_EXIT_CONTINUE;
1772 }
1773
1774 /*
1775  * If this function returns true, this #vmexit was already handled
1776  */
1777 static int nested_svm_intercept(struct vcpu_svm *svm)
1778 {
1779         u32 exit_code = svm->vmcb->control.exit_code;
1780         int vmexit = NESTED_EXIT_HOST;
1781
1782         switch (exit_code) {
1783         case SVM_EXIT_MSR:
1784                 vmexit = nested_svm_exit_handled_msr(svm);
1785                 break;
1786         case SVM_EXIT_IOIO:
1787                 vmexit = nested_svm_intercept_ioio(svm);
1788                 break;
1789         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1790                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1791                 if (svm->nested.intercept_cr_read & cr_bits)
1792                         vmexit = NESTED_EXIT_DONE;
1793                 break;
1794         }
1795         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1796                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1797                 if (svm->nested.intercept_cr_write & cr_bits)
1798                         vmexit = NESTED_EXIT_DONE;
1799                 break;
1800         }
1801         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1802                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1803                 if (svm->nested.intercept_dr_read & dr_bits)
1804                         vmexit = NESTED_EXIT_DONE;
1805                 break;
1806         }
1807         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1808                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1809                 if (svm->nested.intercept_dr_write & dr_bits)
1810                         vmexit = NESTED_EXIT_DONE;
1811                 break;
1812         }
1813         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1814                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1815                 if (svm->nested.intercept_exceptions & excp_bits)
1816                         vmexit = NESTED_EXIT_DONE;
1817                 break;
1818         }
1819         case SVM_EXIT_ERR: {
1820                 vmexit = NESTED_EXIT_DONE;
1821                 break;
1822         }
1823         default: {
1824                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1825                 if (svm->nested.intercept & exit_bits)
1826                         vmexit = NESTED_EXIT_DONE;
1827         }
1828         }
1829
1830         return vmexit;
1831 }
1832
1833 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1834 {
1835         int vmexit;
1836
1837         vmexit = nested_svm_intercept(svm);
1838
1839         if (vmexit == NESTED_EXIT_DONE)
1840                 nested_svm_vmexit(svm);
1841
1842         return vmexit;
1843 }
1844
1845 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1846 {
1847         struct vmcb_control_area *dst  = &dst_vmcb->control;
1848         struct vmcb_control_area *from = &from_vmcb->control;
1849
1850         dst->intercept_cr_read    = from->intercept_cr_read;
1851         dst->intercept_cr_write   = from->intercept_cr_write;
1852         dst->intercept_dr_read    = from->intercept_dr_read;
1853         dst->intercept_dr_write   = from->intercept_dr_write;
1854         dst->intercept_exceptions = from->intercept_exceptions;
1855         dst->intercept            = from->intercept;
1856         dst->iopm_base_pa         = from->iopm_base_pa;
1857         dst->msrpm_base_pa        = from->msrpm_base_pa;
1858         dst->tsc_offset           = from->tsc_offset;
1859         dst->asid                 = from->asid;
1860         dst->tlb_ctl              = from->tlb_ctl;
1861         dst->int_ctl              = from->int_ctl;
1862         dst->int_vector           = from->int_vector;
1863         dst->int_state            = from->int_state;
1864         dst->exit_code            = from->exit_code;
1865         dst->exit_code_hi         = from->exit_code_hi;
1866         dst->exit_info_1          = from->exit_info_1;
1867         dst->exit_info_2          = from->exit_info_2;
1868         dst->exit_int_info        = from->exit_int_info;
1869         dst->exit_int_info_err    = from->exit_int_info_err;
1870         dst->nested_ctl           = from->nested_ctl;
1871         dst->event_inj            = from->event_inj;
1872         dst->event_inj_err        = from->event_inj_err;
1873         dst->nested_cr3           = from->nested_cr3;
1874         dst->lbr_ctl              = from->lbr_ctl;
1875 }
1876
1877 static int nested_svm_vmexit(struct vcpu_svm *svm)
1878 {
1879         struct vmcb *nested_vmcb;
1880         struct vmcb *hsave = svm->nested.hsave;
1881         struct vmcb *vmcb = svm->vmcb;
1882         struct page *page;
1883
1884         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1885                                        vmcb->control.exit_info_1,
1886                                        vmcb->control.exit_info_2,
1887                                        vmcb->control.exit_int_info,
1888                                        vmcb->control.exit_int_info_err);
1889
1890         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1891         if (!nested_vmcb)
1892                 return 1;
1893
1894         /* Exit nested SVM mode */
1895         svm->nested.vmcb = 0;
1896
1897         /* Give the current vmcb to the guest */
1898         disable_gif(svm);
1899
1900         nested_vmcb->save.es     = vmcb->save.es;
1901         nested_vmcb->save.cs     = vmcb->save.cs;
1902         nested_vmcb->save.ss     = vmcb->save.ss;
1903         nested_vmcb->save.ds     = vmcb->save.ds;
1904         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1905         nested_vmcb->save.idtr   = vmcb->save.idtr;
1906         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
1907         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1908         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1909         nested_vmcb->save.cr2    = vmcb->save.cr2;
1910         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1911         nested_vmcb->save.rflags = vmcb->save.rflags;
1912         nested_vmcb->save.rip    = vmcb->save.rip;
1913         nested_vmcb->save.rsp    = vmcb->save.rsp;
1914         nested_vmcb->save.rax    = vmcb->save.rax;
1915         nested_vmcb->save.dr7    = vmcb->save.dr7;
1916         nested_vmcb->save.dr6    = vmcb->save.dr6;
1917         nested_vmcb->save.cpl    = vmcb->save.cpl;
1918
1919         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1920         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1921         nested_vmcb->control.int_state         = vmcb->control.int_state;
1922         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1923         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1924         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1925         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1926         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1927         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1928         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
1929
1930         /*
1931          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1932          * to make sure that we do not lose injected events. So check event_inj
1933          * here and copy it to exit_int_info if it is valid.
1934          * Exit_int_info and event_inj can't be both valid because the case
1935          * below only happens on a VMRUN instruction intercept which has
1936          * no valid exit_int_info set.
1937          */
1938         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1939                 struct vmcb_control_area *nc = &nested_vmcb->control;
1940
1941                 nc->exit_int_info     = vmcb->control.event_inj;
1942                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1943         }
1944
1945         nested_vmcb->control.tlb_ctl           = 0;
1946         nested_vmcb->control.event_inj         = 0;
1947         nested_vmcb->control.event_inj_err     = 0;
1948
1949         /* We always set V_INTR_MASKING and remember the old value in hflags */
1950         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1951                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1952
1953         /* Restore the original control entries */
1954         copy_vmcb_control_area(vmcb, hsave);
1955
1956         kvm_clear_exception_queue(&svm->vcpu);
1957         kvm_clear_interrupt_queue(&svm->vcpu);
1958
1959         /* Restore selected save entries */
1960         svm->vmcb->save.es = hsave->save.es;
1961         svm->vmcb->save.cs = hsave->save.cs;
1962         svm->vmcb->save.ss = hsave->save.ss;
1963         svm->vmcb->save.ds = hsave->save.ds;
1964         svm->vmcb->save.gdtr = hsave->save.gdtr;
1965         svm->vmcb->save.idtr = hsave->save.idtr;
1966         svm->vmcb->save.rflags = hsave->save.rflags;
1967         svm_set_efer(&svm->vcpu, hsave->save.efer);
1968         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1969         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1970         if (npt_enabled) {
1971                 svm->vmcb->save.cr3 = hsave->save.cr3;
1972                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1973         } else {
1974                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1975         }
1976         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1977         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1978         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1979         svm->vmcb->save.dr7 = 0;
1980         svm->vmcb->save.cpl = 0;
1981         svm->vmcb->control.exit_int_info = 0;
1982
1983         nested_svm_unmap(page);
1984
1985         kvm_mmu_reset_context(&svm->vcpu);
1986         kvm_mmu_load(&svm->vcpu);
1987
1988         return 0;
1989 }
1990
1991 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1992 {
1993         /*
1994          * This function merges the msr permission bitmaps of kvm and the
1995          * nested vmcb. It is omptimized in that it only merges the parts where
1996          * the kvm msr permission bitmap may contain zero bits
1997          */
1998         int i;
1999
2000         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2001                 return true;
2002
2003         for (i = 0; i < MSRPM_OFFSETS; i++) {
2004                 u32 value, p;
2005                 u64 offset;
2006
2007                 if (msrpm_offsets[i] == 0xffffffff)
2008                         break;
2009
2010                 p      = msrpm_offsets[i];
2011                 offset = svm->nested.vmcb_msrpm + (p * 4);
2012
2013                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2014                         return false;
2015
2016                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2017         }
2018
2019         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2020
2021         return true;
2022 }
2023
2024 static bool nested_vmcb_checks(struct vmcb *vmcb)
2025 {
2026         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2027                 return false;
2028
2029         if (vmcb->control.asid == 0)
2030                 return false;
2031
2032         return true;
2033 }
2034
2035 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2036 {
2037         struct vmcb *nested_vmcb;
2038         struct vmcb *hsave = svm->nested.hsave;
2039         struct vmcb *vmcb = svm->vmcb;
2040         struct page *page;
2041         u64 vmcb_gpa;
2042
2043         vmcb_gpa = svm->vmcb->save.rax;
2044
2045         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2046         if (!nested_vmcb)
2047                 return false;
2048
2049         if (!nested_vmcb_checks(nested_vmcb)) {
2050                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2051                 nested_vmcb->control.exit_code_hi = 0;
2052                 nested_vmcb->control.exit_info_1  = 0;
2053                 nested_vmcb->control.exit_info_2  = 0;
2054
2055                 nested_svm_unmap(page);
2056
2057                 return false;
2058         }
2059
2060         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
2061                                nested_vmcb->save.rip,
2062                                nested_vmcb->control.int_ctl,
2063                                nested_vmcb->control.event_inj,
2064                                nested_vmcb->control.nested_ctl);
2065
2066         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2067                                     nested_vmcb->control.intercept_cr_write,
2068                                     nested_vmcb->control.intercept_exceptions,
2069                                     nested_vmcb->control.intercept);
2070
2071         /* Clear internal status */
2072         kvm_clear_exception_queue(&svm->vcpu);
2073         kvm_clear_interrupt_queue(&svm->vcpu);
2074
2075         /*
2076          * Save the old vmcb, so we don't need to pick what we save, but can
2077          * restore everything when a VMEXIT occurs
2078          */
2079         hsave->save.es     = vmcb->save.es;
2080         hsave->save.cs     = vmcb->save.cs;
2081         hsave->save.ss     = vmcb->save.ss;
2082         hsave->save.ds     = vmcb->save.ds;
2083         hsave->save.gdtr   = vmcb->save.gdtr;
2084         hsave->save.idtr   = vmcb->save.idtr;
2085         hsave->save.efer   = svm->vcpu.arch.efer;
2086         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2087         hsave->save.cr4    = svm->vcpu.arch.cr4;
2088         hsave->save.rflags = vmcb->save.rflags;
2089         hsave->save.rip    = svm->next_rip;
2090         hsave->save.rsp    = vmcb->save.rsp;
2091         hsave->save.rax    = vmcb->save.rax;
2092         if (npt_enabled)
2093                 hsave->save.cr3    = vmcb->save.cr3;
2094         else
2095                 hsave->save.cr3    = svm->vcpu.arch.cr3;
2096
2097         copy_vmcb_control_area(hsave, vmcb);
2098
2099         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2100                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2101         else
2102                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2103
2104         /* Load the nested guest state */
2105         svm->vmcb->save.es = nested_vmcb->save.es;
2106         svm->vmcb->save.cs = nested_vmcb->save.cs;
2107         svm->vmcb->save.ss = nested_vmcb->save.ss;
2108         svm->vmcb->save.ds = nested_vmcb->save.ds;
2109         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2110         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2111         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2112         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2113         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2114         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2115         if (npt_enabled) {
2116                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2117                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2118         } else
2119                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2120
2121         /* Guest paging mode is active - reset mmu */
2122         kvm_mmu_reset_context(&svm->vcpu);
2123
2124         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2125         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2126         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2127         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2128
2129         /* In case we don't even reach vcpu_run, the fields are not updated */
2130         svm->vmcb->save.rax = nested_vmcb->save.rax;
2131         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2132         svm->vmcb->save.rip = nested_vmcb->save.rip;
2133         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2134         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2135         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2136
2137         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2138         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2139
2140         /* cache intercepts */
2141         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2142         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2143         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2144         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2145         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2146         svm->nested.intercept            = nested_vmcb->control.intercept;
2147
2148         force_new_asid(&svm->vcpu);
2149         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2150         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2151                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2152         else
2153                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2154
2155         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2156                 /* We only want the cr8 intercept bits of the guest */
2157                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2158                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2159         }
2160
2161         /* We don't want to see VMMCALLs from a nested guest */
2162         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2163
2164         /*
2165          * We don't want a nested guest to be more powerful than the guest, so
2166          * all intercepts are ORed
2167          */
2168         svm->vmcb->control.intercept_cr_read |=
2169                 nested_vmcb->control.intercept_cr_read;
2170         svm->vmcb->control.intercept_cr_write |=
2171                 nested_vmcb->control.intercept_cr_write;
2172         svm->vmcb->control.intercept_dr_read |=
2173                 nested_vmcb->control.intercept_dr_read;
2174         svm->vmcb->control.intercept_dr_write |=
2175                 nested_vmcb->control.intercept_dr_write;
2176         svm->vmcb->control.intercept_exceptions |=
2177                 nested_vmcb->control.intercept_exceptions;
2178
2179         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2180
2181         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2182         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2183         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2184         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2185         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2186         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2187
2188         nested_svm_unmap(page);
2189
2190         /* nested_vmcb is our indicator if nested SVM is activated */
2191         svm->nested.vmcb = vmcb_gpa;
2192
2193         enable_gif(svm);
2194
2195         return true;
2196 }
2197
2198 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2199 {
2200         to_vmcb->save.fs = from_vmcb->save.fs;
2201         to_vmcb->save.gs = from_vmcb->save.gs;
2202         to_vmcb->save.tr = from_vmcb->save.tr;
2203         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2204         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2205         to_vmcb->save.star = from_vmcb->save.star;
2206         to_vmcb->save.lstar = from_vmcb->save.lstar;
2207         to_vmcb->save.cstar = from_vmcb->save.cstar;
2208         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2209         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2210         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2211         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2212 }
2213
2214 static int vmload_interception(struct vcpu_svm *svm)
2215 {
2216         struct vmcb *nested_vmcb;
2217         struct page *page;
2218
2219         if (nested_svm_check_permissions(svm))
2220                 return 1;
2221
2222         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2223         skip_emulated_instruction(&svm->vcpu);
2224
2225         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2226         if (!nested_vmcb)
2227                 return 1;
2228
2229         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2230         nested_svm_unmap(page);
2231
2232         return 1;
2233 }
2234
2235 static int vmsave_interception(struct vcpu_svm *svm)
2236 {
2237         struct vmcb *nested_vmcb;
2238         struct page *page;
2239
2240         if (nested_svm_check_permissions(svm))
2241                 return 1;
2242
2243         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2244         skip_emulated_instruction(&svm->vcpu);
2245
2246         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2247         if (!nested_vmcb)
2248                 return 1;
2249
2250         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2251         nested_svm_unmap(page);
2252
2253         return 1;
2254 }
2255
2256 static int vmrun_interception(struct vcpu_svm *svm)
2257 {
2258         if (nested_svm_check_permissions(svm))
2259                 return 1;
2260
2261         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2262         skip_emulated_instruction(&svm->vcpu);
2263
2264         if (!nested_svm_vmrun(svm))
2265                 return 1;
2266
2267         if (!nested_svm_vmrun_msrpm(svm))
2268                 goto failed;
2269
2270         return 1;
2271
2272 failed:
2273
2274         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2275         svm->vmcb->control.exit_code_hi = 0;
2276         svm->vmcb->control.exit_info_1  = 0;
2277         svm->vmcb->control.exit_info_2  = 0;
2278
2279         nested_svm_vmexit(svm);
2280
2281         return 1;
2282 }
2283
2284 static int stgi_interception(struct vcpu_svm *svm)
2285 {
2286         if (nested_svm_check_permissions(svm))
2287                 return 1;
2288
2289         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2290         skip_emulated_instruction(&svm->vcpu);
2291
2292         enable_gif(svm);
2293
2294         return 1;
2295 }
2296
2297 static int clgi_interception(struct vcpu_svm *svm)
2298 {
2299         if (nested_svm_check_permissions(svm))
2300                 return 1;
2301
2302         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2303         skip_emulated_instruction(&svm->vcpu);
2304
2305         disable_gif(svm);
2306
2307         /* After a CLGI no interrupts should come */
2308         svm_clear_vintr(svm);
2309         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2310
2311         return 1;
2312 }
2313
2314 static int invlpga_interception(struct vcpu_svm *svm)
2315 {
2316         struct kvm_vcpu *vcpu = &svm->vcpu;
2317
2318         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2319                           vcpu->arch.regs[VCPU_REGS_RAX]);
2320
2321         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2322         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2323
2324         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2325         skip_emulated_instruction(&svm->vcpu);
2326         return 1;
2327 }
2328
2329 static int skinit_interception(struct vcpu_svm *svm)
2330 {
2331         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2332
2333         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2334         return 1;
2335 }
2336
2337 static int invalid_op_interception(struct vcpu_svm *svm)
2338 {
2339         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2340         return 1;
2341 }
2342
2343 static int task_switch_interception(struct vcpu_svm *svm)
2344 {
2345         u16 tss_selector;
2346         int reason;
2347         int int_type = svm->vmcb->control.exit_int_info &
2348                 SVM_EXITINTINFO_TYPE_MASK;
2349         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2350         uint32_t type =
2351                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2352         uint32_t idt_v =
2353                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2354         bool has_error_code = false;
2355         u32 error_code = 0;
2356
2357         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2358
2359         if (svm->vmcb->control.exit_info_2 &
2360             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2361                 reason = TASK_SWITCH_IRET;
2362         else if (svm->vmcb->control.exit_info_2 &
2363                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2364                 reason = TASK_SWITCH_JMP;
2365         else if (idt_v)
2366                 reason = TASK_SWITCH_GATE;
2367         else
2368                 reason = TASK_SWITCH_CALL;
2369
2370         if (reason == TASK_SWITCH_GATE) {
2371                 switch (type) {
2372                 case SVM_EXITINTINFO_TYPE_NMI:
2373                         svm->vcpu.arch.nmi_injected = false;
2374                         break;
2375                 case SVM_EXITINTINFO_TYPE_EXEPT:
2376                         if (svm->vmcb->control.exit_info_2 &
2377                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2378                                 has_error_code = true;
2379                                 error_code =
2380                                         (u32)svm->vmcb->control.exit_info_2;
2381                         }
2382                         kvm_clear_exception_queue(&svm->vcpu);
2383                         break;
2384                 case SVM_EXITINTINFO_TYPE_INTR:
2385                         kvm_clear_interrupt_queue(&svm->vcpu);
2386                         break;
2387                 default:
2388                         break;
2389                 }
2390         }
2391
2392         if (reason != TASK_SWITCH_GATE ||
2393             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2394             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2395              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2396                 skip_emulated_instruction(&svm->vcpu);
2397
2398         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2399                                 has_error_code, error_code) == EMULATE_FAIL) {
2400                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2401                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2402                 svm->vcpu.run->internal.ndata = 0;
2403                 return 0;
2404         }
2405         return 1;
2406 }
2407
2408 static int cpuid_interception(struct vcpu_svm *svm)
2409 {
2410         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2411         kvm_emulate_cpuid(&svm->vcpu);
2412         return 1;
2413 }
2414
2415 static int iret_interception(struct vcpu_svm *svm)
2416 {
2417         ++svm->vcpu.stat.nmi_window_exits;
2418         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2419         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2420         return 1;
2421 }
2422
2423 static int invlpg_interception(struct vcpu_svm *svm)
2424 {
2425         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2426 }
2427
2428 static int emulate_on_interception(struct vcpu_svm *svm)
2429 {
2430         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2431 }
2432
2433 static int cr8_write_interception(struct vcpu_svm *svm)
2434 {
2435         struct kvm_run *kvm_run = svm->vcpu.run;
2436
2437         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2438         /* instruction emulation calls kvm_set_cr8() */
2439         emulate_instruction(&svm->vcpu, 0, 0, 0);
2440         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2441                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2442                 return 1;
2443         }
2444         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2445                 return 1;
2446         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2447         return 0;
2448 }
2449
2450 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2451 {
2452         struct vcpu_svm *svm = to_svm(vcpu);
2453
2454         switch (ecx) {
2455         case MSR_IA32_TSC: {
2456                 u64 tsc_offset;
2457
2458                 if (is_nested(svm))
2459                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2460                 else
2461                         tsc_offset = svm->vmcb->control.tsc_offset;
2462
2463                 *data = tsc_offset + native_read_tsc();
2464                 break;
2465         }
2466         case MSR_STAR:
2467                 *data = svm->vmcb->save.star;
2468                 break;
2469 #ifdef CONFIG_X86_64
2470         case MSR_LSTAR:
2471                 *data = svm->vmcb->save.lstar;
2472                 break;
2473         case MSR_CSTAR:
2474                 *data = svm->vmcb->save.cstar;
2475                 break;
2476         case MSR_KERNEL_GS_BASE:
2477                 *data = svm->vmcb->save.kernel_gs_base;
2478                 break;
2479         case MSR_SYSCALL_MASK:
2480                 *data = svm->vmcb->save.sfmask;
2481                 break;
2482 #endif
2483         case MSR_IA32_SYSENTER_CS:
2484                 *data = svm->vmcb->save.sysenter_cs;
2485                 break;
2486         case MSR_IA32_SYSENTER_EIP:
2487                 *data = svm->sysenter_eip;
2488                 break;
2489         case MSR_IA32_SYSENTER_ESP:
2490                 *data = svm->sysenter_esp;
2491                 break;
2492         /*
2493          * Nobody will change the following 5 values in the VMCB so we can
2494          * safely return them on rdmsr. They will always be 0 until LBRV is
2495          * implemented.
2496          */
2497         case MSR_IA32_DEBUGCTLMSR:
2498                 *data = svm->vmcb->save.dbgctl;
2499                 break;
2500         case MSR_IA32_LASTBRANCHFROMIP:
2501                 *data = svm->vmcb->save.br_from;
2502                 break;
2503         case MSR_IA32_LASTBRANCHTOIP:
2504                 *data = svm->vmcb->save.br_to;
2505                 break;
2506         case MSR_IA32_LASTINTFROMIP:
2507                 *data = svm->vmcb->save.last_excp_from;
2508                 break;
2509         case MSR_IA32_LASTINTTOIP:
2510                 *data = svm->vmcb->save.last_excp_to;
2511                 break;
2512         case MSR_VM_HSAVE_PA:
2513                 *data = svm->nested.hsave_msr;
2514                 break;
2515         case MSR_VM_CR:
2516                 *data = svm->nested.vm_cr_msr;
2517                 break;
2518         case MSR_IA32_UCODE_REV:
2519                 *data = 0x01000065;
2520                 break;
2521         default:
2522                 return kvm_get_msr_common(vcpu, ecx, data);
2523         }
2524         return 0;
2525 }
2526
2527 static int rdmsr_interception(struct vcpu_svm *svm)
2528 {
2529         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2530         u64 data;
2531
2532         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2533                 trace_kvm_msr_read_ex(ecx);
2534                 kvm_inject_gp(&svm->vcpu, 0);
2535         } else {
2536                 trace_kvm_msr_read(ecx, data);
2537
2538                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2539                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2540                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2541                 skip_emulated_instruction(&svm->vcpu);
2542         }
2543         return 1;
2544 }
2545
2546 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2547 {
2548         struct vcpu_svm *svm = to_svm(vcpu);
2549         int svm_dis, chg_mask;
2550
2551         if (data & ~SVM_VM_CR_VALID_MASK)
2552                 return 1;
2553
2554         chg_mask = SVM_VM_CR_VALID_MASK;
2555
2556         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2557                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2558
2559         svm->nested.vm_cr_msr &= ~chg_mask;
2560         svm->nested.vm_cr_msr |= (data & chg_mask);
2561
2562         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2563
2564         /* check for svm_disable while efer.svme is set */
2565         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2566                 return 1;
2567
2568         return 0;
2569 }
2570
2571 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2572 {
2573         struct vcpu_svm *svm = to_svm(vcpu);
2574
2575         switch (ecx) {
2576         case MSR_IA32_TSC:
2577                 kvm_write_tsc(vcpu, data);
2578                 break;
2579         case MSR_STAR:
2580                 svm->vmcb->save.star = data;
2581                 break;
2582 #ifdef CONFIG_X86_64
2583         case MSR_LSTAR:
2584                 svm->vmcb->save.lstar = data;
2585                 break;
2586         case MSR_CSTAR:
2587                 svm->vmcb->save.cstar = data;
2588                 break;
2589         case MSR_KERNEL_GS_BASE:
2590                 svm->vmcb->save.kernel_gs_base = data;
2591                 break;
2592         case MSR_SYSCALL_MASK:
2593                 svm->vmcb->save.sfmask = data;
2594                 break;
2595 #endif
2596         case MSR_IA32_SYSENTER_CS:
2597                 svm->vmcb->save.sysenter_cs = data;
2598                 break;
2599         case MSR_IA32_SYSENTER_EIP:
2600                 svm->sysenter_eip = data;
2601                 svm->vmcb->save.sysenter_eip = data;
2602                 break;
2603         case MSR_IA32_SYSENTER_ESP:
2604                 svm->sysenter_esp = data;
2605                 svm->vmcb->save.sysenter_esp = data;
2606                 break;
2607         case MSR_IA32_DEBUGCTLMSR:
2608                 if (!svm_has(SVM_FEATURE_LBRV)) {
2609                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2610                                         __func__, data);
2611                         break;
2612                 }
2613                 if (data & DEBUGCTL_RESERVED_BITS)
2614                         return 1;
2615
2616                 svm->vmcb->save.dbgctl = data;
2617                 if (data & (1ULL<<0))
2618                         svm_enable_lbrv(svm);
2619                 else
2620                         svm_disable_lbrv(svm);
2621                 break;
2622         case MSR_VM_HSAVE_PA:
2623                 svm->nested.hsave_msr = data;
2624                 break;
2625         case MSR_VM_CR:
2626                 return svm_set_vm_cr(vcpu, data);
2627         case MSR_VM_IGNNE:
2628                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2629                 break;
2630         default:
2631                 return kvm_set_msr_common(vcpu, ecx, data);
2632         }
2633         return 0;
2634 }
2635
2636 static int wrmsr_interception(struct vcpu_svm *svm)
2637 {
2638         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2639         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2640                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2641
2642
2643         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2644         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2645                 trace_kvm_msr_write_ex(ecx, data);
2646                 kvm_inject_gp(&svm->vcpu, 0);
2647         } else {
2648                 trace_kvm_msr_write(ecx, data);
2649                 skip_emulated_instruction(&svm->vcpu);
2650         }
2651         return 1;
2652 }
2653
2654 static int msr_interception(struct vcpu_svm *svm)
2655 {
2656         if (svm->vmcb->control.exit_info_1)
2657                 return wrmsr_interception(svm);
2658         else
2659                 return rdmsr_interception(svm);
2660 }
2661
2662 static int interrupt_window_interception(struct vcpu_svm *svm)
2663 {
2664         struct kvm_run *kvm_run = svm->vcpu.run;
2665
2666         svm_clear_vintr(svm);
2667         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2668         /*
2669          * If the user space waits to inject interrupts, exit as soon as
2670          * possible
2671          */
2672         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2673             kvm_run->request_interrupt_window &&
2674             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2675                 ++svm->vcpu.stat.irq_window_exits;
2676                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2677                 return 0;
2678         }
2679
2680         return 1;
2681 }
2682
2683 static int pause_interception(struct vcpu_svm *svm)
2684 {
2685         kvm_vcpu_on_spin(&(svm->vcpu));
2686         return 1;
2687 }
2688
2689 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2690         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2691         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2692         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2693         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2694         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2695         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2696         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2697         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2698         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2699         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2700         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2701         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2702         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2703         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2704         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2705         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2706         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2707         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2708         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2709         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2710         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2711         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2712         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2713         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2714         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2715         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2716         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2717         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2718         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2719         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2720         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2721         [SVM_EXIT_INTR]                         = intr_interception,
2722         [SVM_EXIT_NMI]                          = nmi_interception,
2723         [SVM_EXIT_SMI]                          = nop_on_interception,
2724         [SVM_EXIT_INIT]                         = nop_on_interception,
2725         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2726         [SVM_EXIT_CPUID]                        = cpuid_interception,
2727         [SVM_EXIT_IRET]                         = iret_interception,
2728         [SVM_EXIT_INVD]                         = emulate_on_interception,
2729         [SVM_EXIT_PAUSE]                        = pause_interception,
2730         [SVM_EXIT_HLT]                          = halt_interception,
2731         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2732         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2733         [SVM_EXIT_IOIO]                         = io_interception,
2734         [SVM_EXIT_MSR]                          = msr_interception,
2735         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2736         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2737         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2738         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2739         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2740         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2741         [SVM_EXIT_STGI]                         = stgi_interception,
2742         [SVM_EXIT_CLGI]                         = clgi_interception,
2743         [SVM_EXIT_SKINIT]                       = skinit_interception,
2744         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2745         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2746         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2747         [SVM_EXIT_NPF]                          = pf_interception,
2748 };
2749
2750 void dump_vmcb(struct kvm_vcpu *vcpu)
2751 {
2752         struct vcpu_svm *svm = to_svm(vcpu);
2753         struct vmcb_control_area *control = &svm->vmcb->control;
2754         struct vmcb_save_area *save = &svm->vmcb->save;
2755
2756         pr_err("VMCB Control Area:\n");
2757         pr_err("cr_read:            %04x\n", control->intercept_cr_read);
2758         pr_err("cr_write:           %04x\n", control->intercept_cr_write);
2759         pr_err("dr_read:            %04x\n", control->intercept_dr_read);
2760         pr_err("dr_write:           %04x\n", control->intercept_dr_write);
2761         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
2762         pr_err("intercepts:         %016llx\n", control->intercept);
2763         pr_err("pause filter count: %d\n", control->pause_filter_count);
2764         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
2765         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
2766         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
2767         pr_err("asid:               %d\n", control->asid);
2768         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
2769         pr_err("int_ctl:            %08x\n", control->int_ctl);
2770         pr_err("int_vector:         %08x\n", control->int_vector);
2771         pr_err("int_state:          %08x\n", control->int_state);
2772         pr_err("exit_code:          %08x\n", control->exit_code);
2773         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
2774         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
2775         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
2776         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
2777         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
2778         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
2779         pr_err("event_inj:          %08x\n", control->event_inj);
2780         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
2781         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
2782         pr_err("next_rip:           %016llx\n", control->next_rip);
2783         pr_err("VMCB State Save Area:\n");
2784         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
2785                 save->es.selector, save->es.attrib,
2786                 save->es.limit, save->es.base);
2787         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
2788                 save->cs.selector, save->cs.attrib,
2789                 save->cs.limit, save->cs.base);
2790         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
2791                 save->ss.selector, save->ss.attrib,
2792                 save->ss.limit, save->ss.base);
2793         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
2794                 save->ds.selector, save->ds.attrib,
2795                 save->ds.limit, save->ds.base);
2796         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
2797                 save->fs.selector, save->fs.attrib,
2798                 save->fs.limit, save->fs.base);
2799         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
2800                 save->gs.selector, save->gs.attrib,
2801                 save->gs.limit, save->gs.base);
2802         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2803                 save->gdtr.selector, save->gdtr.attrib,
2804                 save->gdtr.limit, save->gdtr.base);
2805         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2806                 save->ldtr.selector, save->ldtr.attrib,
2807                 save->ldtr.limit, save->ldtr.base);
2808         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2809                 save->idtr.selector, save->idtr.attrib,
2810                 save->idtr.limit, save->idtr.base);
2811         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
2812                 save->tr.selector, save->tr.attrib,
2813                 save->tr.limit, save->tr.base);
2814         pr_err("cpl:            %d                efer:         %016llx\n",
2815                 save->cpl, save->efer);
2816         pr_err("cr0:            %016llx cr2:          %016llx\n",
2817                 save->cr0, save->cr2);
2818         pr_err("cr3:            %016llx cr4:          %016llx\n",
2819                 save->cr3, save->cr4);
2820         pr_err("dr6:            %016llx dr7:          %016llx\n",
2821                 save->dr6, save->dr7);
2822         pr_err("rip:            %016llx rflags:       %016llx\n",
2823                 save->rip, save->rflags);
2824         pr_err("rsp:            %016llx rax:          %016llx\n",
2825                 save->rsp, save->rax);
2826         pr_err("star:           %016llx lstar:        %016llx\n",
2827                 save->star, save->lstar);
2828         pr_err("cstar:          %016llx sfmask:       %016llx\n",
2829                 save->cstar, save->sfmask);
2830         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
2831                 save->kernel_gs_base, save->sysenter_cs);
2832         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
2833                 save->sysenter_esp, save->sysenter_eip);
2834         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
2835                 save->g_pat, save->dbgctl);
2836         pr_err("br_from:        %016llx br_to:        %016llx\n",
2837                 save->br_from, save->br_to);
2838         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
2839                 save->last_excp_from, save->last_excp_to);
2840
2841 }
2842
2843 static int handle_exit(struct kvm_vcpu *vcpu)
2844 {
2845         struct vcpu_svm *svm = to_svm(vcpu);
2846         struct kvm_run *kvm_run = vcpu->run;
2847         u32 exit_code = svm->vmcb->control.exit_code;
2848
2849         trace_kvm_exit(exit_code, vcpu);
2850
2851         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2852                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2853         if (npt_enabled)
2854                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2855
2856         if (unlikely(svm->nested.exit_required)) {
2857                 nested_svm_vmexit(svm);
2858                 svm->nested.exit_required = false;
2859
2860                 return 1;
2861         }
2862
2863         if (is_nested(svm)) {
2864                 int vmexit;
2865
2866                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2867                                         svm->vmcb->control.exit_info_1,
2868                                         svm->vmcb->control.exit_info_2,
2869                                         svm->vmcb->control.exit_int_info,
2870                                         svm->vmcb->control.exit_int_info_err);
2871
2872                 vmexit = nested_svm_exit_special(svm);
2873
2874                 if (vmexit == NESTED_EXIT_CONTINUE)
2875                         vmexit = nested_svm_exit_handled(svm);
2876
2877                 if (vmexit == NESTED_EXIT_DONE)
2878                         return 1;
2879         }
2880
2881         svm_complete_interrupts(svm);
2882
2883         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2884                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2885                 kvm_run->fail_entry.hardware_entry_failure_reason
2886                         = svm->vmcb->control.exit_code;
2887                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2888                 dump_vmcb(vcpu);
2889                 return 0;
2890         }
2891
2892         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2893             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2894             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2895                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2896                        "exit_code 0x%x\n",
2897                        __func__, svm->vmcb->control.exit_int_info,
2898                        exit_code);
2899
2900         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2901             || !svm_exit_handlers[exit_code]) {
2902                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2903                 kvm_run->hw.hardware_exit_reason = exit_code;
2904                 return 0;
2905         }
2906
2907         return svm_exit_handlers[exit_code](svm);
2908 }
2909
2910 static void reload_tss(struct kvm_vcpu *vcpu)
2911 {
2912         int cpu = raw_smp_processor_id();
2913
2914         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2915         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2916         load_TR_desc();
2917 }
2918
2919 static void pre_svm_run(struct vcpu_svm *svm)
2920 {
2921         int cpu = raw_smp_processor_id();
2922
2923         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2924
2925         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2926         /* FIXME: handle wraparound of asid_generation */
2927         if (svm->asid_generation != sd->asid_generation)
2928                 new_asid(svm, sd);
2929 }
2930
2931 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2932 {
2933         struct vcpu_svm *svm = to_svm(vcpu);
2934
2935         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2936         vcpu->arch.hflags |= HF_NMI_MASK;
2937         svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2938         ++vcpu->stat.nmi_injections;
2939 }
2940
2941 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2942 {
2943         struct vmcb_control_area *control;
2944
2945         control = &svm->vmcb->control;
2946         control->int_vector = irq;
2947         control->int_ctl &= ~V_INTR_PRIO_MASK;
2948         control->int_ctl |= V_IRQ_MASK |
2949                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2950 }
2951
2952 static void svm_set_irq(struct kvm_vcpu *vcpu)
2953 {
2954         struct vcpu_svm *svm = to_svm(vcpu);
2955
2956         BUG_ON(!(gif_set(svm)));
2957
2958         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
2959         ++vcpu->stat.irq_injections;
2960
2961         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2962                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2963 }
2964
2965 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2966 {
2967         struct vcpu_svm *svm = to_svm(vcpu);
2968
2969         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2970                 return;
2971
2972         if (irr == -1)
2973                 return;
2974
2975         if (tpr >= irr)
2976                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2977 }
2978
2979 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2980 {
2981         struct vcpu_svm *svm = to_svm(vcpu);
2982         struct vmcb *vmcb = svm->vmcb;
2983         int ret;
2984         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2985               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2986         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2987
2988         return ret;
2989 }
2990
2991 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2992 {
2993         struct vcpu_svm *svm = to_svm(vcpu);
2994
2995         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2996 }
2997
2998 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2999 {
3000         struct vcpu_svm *svm = to_svm(vcpu);
3001
3002         if (masked) {
3003                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3004                 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3005         } else {
3006                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3007                 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3008         }
3009 }
3010
3011 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3012 {
3013         struct vcpu_svm *svm = to_svm(vcpu);
3014         struct vmcb *vmcb = svm->vmcb;
3015         int ret;
3016
3017         if (!gif_set(svm) ||
3018              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3019                 return 0;
3020
3021         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3022
3023         if (is_nested(svm))
3024                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3025
3026         return ret;
3027 }
3028
3029 static void enable_irq_window(struct kvm_vcpu *vcpu)
3030 {
3031         struct vcpu_svm *svm = to_svm(vcpu);
3032
3033         /*
3034          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3035          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3036          * get that intercept, this function will be called again though and
3037          * we'll get the vintr intercept.
3038          */
3039         if (gif_set(svm) && nested_svm_intr(svm)) {
3040                 svm_set_vintr(svm);
3041                 svm_inject_irq(svm, 0x0);
3042         }
3043 }
3044
3045 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3046 {
3047         struct vcpu_svm *svm = to_svm(vcpu);
3048
3049         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3050             == HF_NMI_MASK)
3051                 return; /* IRET will cause a vm exit */
3052
3053         /*
3054          * Something prevents NMI from been injected. Single step over possible
3055          * problem (IRET or exception injection or interrupt shadow)
3056          */
3057         svm->nmi_singlestep = true;
3058         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3059         update_db_intercept(vcpu);
3060 }
3061
3062 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3063 {
3064         return 0;
3065 }
3066
3067 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3068 {
3069         force_new_asid(vcpu);
3070 }
3071
3072 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3073 {
3074 }
3075
3076 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3077 {
3078         struct vcpu_svm *svm = to_svm(vcpu);
3079
3080         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3081                 return;
3082
3083         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3084                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3085                 kvm_set_cr8(vcpu, cr8);
3086         }
3087 }
3088
3089 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3090 {
3091         struct vcpu_svm *svm = to_svm(vcpu);
3092         u64 cr8;
3093
3094         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3095                 return;
3096
3097         cr8 = kvm_get_cr8(vcpu);
3098         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3099         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3100 }
3101
3102 static void svm_complete_interrupts(struct vcpu_svm *svm)
3103 {
3104         u8 vector;
3105         int type;
3106         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3107         unsigned int3_injected = svm->int3_injected;
3108
3109         svm->int3_injected = 0;
3110
3111         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3112                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3113
3114         svm->vcpu.arch.nmi_injected = false;
3115         kvm_clear_exception_queue(&svm->vcpu);
3116         kvm_clear_interrupt_queue(&svm->vcpu);
3117
3118         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3119                 return;
3120
3121         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3122         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3123
3124         switch (type) {
3125         case SVM_EXITINTINFO_TYPE_NMI:
3126                 svm->vcpu.arch.nmi_injected = true;
3127                 break;
3128         case SVM_EXITINTINFO_TYPE_EXEPT:
3129                 /*
3130                  * In case of software exceptions, do not reinject the vector,
3131                  * but re-execute the instruction instead. Rewind RIP first
3132                  * if we emulated INT3 before.
3133                  */
3134                 if (kvm_exception_is_soft(vector)) {
3135                         if (vector == BP_VECTOR && int3_injected &&
3136                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3137                                 kvm_rip_write(&svm->vcpu,
3138                                               kvm_rip_read(&svm->vcpu) -
3139                                               int3_injected);
3140                         break;
3141                 }
3142                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3143                         u32 err = svm->vmcb->control.exit_int_info_err;
3144                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3145
3146                 } else
3147                         kvm_requeue_exception(&svm->vcpu, vector);
3148                 break;
3149         case SVM_EXITINTINFO_TYPE_INTR:
3150                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3151                 break;
3152         default:
3153                 break;
3154         }
3155 }
3156
3157 #ifdef CONFIG_X86_64
3158 #define R "r"
3159 #else
3160 #define R "e"
3161 #endif
3162
3163 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3164 {
3165         struct vcpu_svm *svm = to_svm(vcpu);
3166         u16 fs_selector;
3167         u16 gs_selector;
3168         u16 ldt_selector;
3169
3170         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3171         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3172         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3173
3174         /*
3175          * A vmexit emulation is required before the vcpu can be executed
3176          * again.
3177          */
3178         if (unlikely(svm->nested.exit_required))
3179                 return;
3180
3181         pre_svm_run(svm);
3182
3183         sync_lapic_to_cr8(vcpu);
3184
3185         save_host_msrs(vcpu);
3186         savesegment(fs, fs_selector);
3187         savesegment(gs, gs_selector);
3188         ldt_selector = kvm_read_ldt();
3189         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3190         /* required for live migration with NPT */
3191         if (npt_enabled)
3192                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3193
3194         clgi();
3195
3196         local_irq_enable();
3197
3198         asm volatile (
3199                 "push %%"R"bp; \n\t"
3200                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3201                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3202                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3203                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3204                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3205                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3206 #ifdef CONFIG_X86_64
3207                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3208                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3209                 "mov %c[r10](%[svm]), %%r10 \n\t"
3210                 "mov %c[r11](%[svm]), %%r11 \n\t"
3211                 "mov %c[r12](%[svm]), %%r12 \n\t"
3212                 "mov %c[r13](%[svm]), %%r13 \n\t"
3213                 "mov %c[r14](%[svm]), %%r14 \n\t"
3214                 "mov %c[r15](%[svm]), %%r15 \n\t"
3215 #endif
3216
3217                 /* Enter guest mode */
3218                 "push %%"R"ax \n\t"
3219                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3220                 __ex(SVM_VMLOAD) "\n\t"
3221                 __ex(SVM_VMRUN) "\n\t"
3222                 __ex(SVM_VMSAVE) "\n\t"
3223                 "pop %%"R"ax \n\t"
3224
3225                 /* Save guest registers, load host registers */
3226                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3227                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3228                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3229                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3230                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3231                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3232 #ifdef CONFIG_X86_64
3233                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3234                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3235                 "mov %%r10, %c[r10](%[svm]) \n\t"
3236                 "mov %%r11, %c[r11](%[svm]) \n\t"
3237                 "mov %%r12, %c[r12](%[svm]) \n\t"
3238                 "mov %%r13, %c[r13](%[svm]) \n\t"
3239                 "mov %%r14, %c[r14](%[svm]) \n\t"
3240                 "mov %%r15, %c[r15](%[svm]) \n\t"
3241 #endif
3242                 "pop %%"R"bp"
3243                 :
3244                 : [svm]"a"(svm),
3245                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3246                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3247                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3248                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3249                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3250                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3251                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3252 #ifdef CONFIG_X86_64
3253                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3254                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3255                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3256                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3257                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3258                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3259                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3260                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3261 #endif
3262                 : "cc", "memory"
3263                 , R"bx", R"cx", R"dx", R"si", R"di"
3264 #ifdef CONFIG_X86_64
3265                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3266 #endif
3267                 );
3268
3269         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3270         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3271         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3272         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3273
3274         load_host_msrs(vcpu);
3275         loadsegment(fs, fs_selector);
3276 #ifdef CONFIG_X86_64
3277         load_gs_index(gs_selector);
3278         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3279 #else
3280         loadsegment(gs, gs_selector);
3281 #endif
3282         kvm_load_ldt(ldt_selector);
3283
3284         reload_tss(vcpu);
3285
3286         local_irq_disable();
3287
3288         stgi();
3289
3290         sync_cr8_to_lapic(vcpu);
3291
3292         svm->next_rip = 0;
3293
3294         if (npt_enabled) {
3295                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3296                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3297         }
3298
3299         /*
3300          * We need to handle MC intercepts here before the vcpu has a chance to
3301          * change the physical cpu
3302          */
3303         if (unlikely(svm->vmcb->control.exit_code ==
3304                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3305                 svm_handle_mce(svm);
3306 }
3307
3308 #undef R
3309
3310 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3311 {
3312         struct vcpu_svm *svm = to_svm(vcpu);
3313
3314         if (npt_enabled) {
3315                 svm->vmcb->control.nested_cr3 = root;
3316                 force_new_asid(vcpu);
3317                 return;
3318         }
3319
3320         svm->vmcb->save.cr3 = root;
3321         force_new_asid(vcpu);
3322 }
3323
3324 static int is_disabled(void)
3325 {
3326         u64 vm_cr;
3327
3328         rdmsrl(MSR_VM_CR, vm_cr);
3329         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3330                 return 1;
3331
3332         return 0;
3333 }
3334
3335 static void
3336 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3337 {
3338         /*
3339          * Patch in the VMMCALL instruction:
3340          */
3341         hypercall[0] = 0x0f;
3342         hypercall[1] = 0x01;
3343         hypercall[2] = 0xd9;
3344 }
3345
3346 static void svm_check_processor_compat(void *rtn)
3347 {
3348         *(int *)rtn = 0;
3349 }
3350
3351 static bool svm_cpu_has_accelerated_tpr(void)
3352 {
3353         return false;
3354 }
3355
3356 static int get_npt_level(void)
3357 {
3358 #ifdef CONFIG_X86_64
3359         return PT64_ROOT_LEVEL;
3360 #else
3361         return PT32E_ROOT_LEVEL;
3362 #endif
3363 }
3364
3365 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3366 {
3367         return 0;
3368 }
3369
3370 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3371 {
3372 }
3373
3374 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3375 {
3376         switch (func) {
3377         case 0x8000000A:
3378                 entry->eax = 1; /* SVM revision 1 */
3379                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3380                                    ASID emulation to nested SVM */
3381                 entry->ecx = 0; /* Reserved */
3382                 entry->edx = 0; /* Per default do not support any
3383                                    additional features */
3384
3385                 /* Support next_rip if host supports it */
3386                 if (svm_has(SVM_FEATURE_NRIP))
3387                         entry->edx |= SVM_FEATURE_NRIP;
3388
3389                 break;
3390         }
3391 }
3392
3393 static const struct trace_print_flags svm_exit_reasons_str[] = {
3394         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3395         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3396         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3397         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3398         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3399         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3400         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3401         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3402         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3403         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3404         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3405         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3406         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3407         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3408         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3409         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3410         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3411         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3412         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3413         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3414         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3415         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3416         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3417         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3418         { SVM_EXIT_INTR,                        "interrupt" },
3419         { SVM_EXIT_NMI,                         "nmi" },
3420         { SVM_EXIT_SMI,                         "smi" },
3421         { SVM_EXIT_INIT,                        "init" },
3422         { SVM_EXIT_VINTR,                       "vintr" },
3423         { SVM_EXIT_CPUID,                       "cpuid" },
3424         { SVM_EXIT_INVD,                        "invd" },
3425         { SVM_EXIT_HLT,                         "hlt" },
3426         { SVM_EXIT_INVLPG,                      "invlpg" },
3427         { SVM_EXIT_INVLPGA,                     "invlpga" },
3428         { SVM_EXIT_IOIO,                        "io" },
3429         { SVM_EXIT_MSR,                         "msr" },
3430         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3431         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3432         { SVM_EXIT_VMRUN,                       "vmrun" },
3433         { SVM_EXIT_VMMCALL,                     "hypercall" },
3434         { SVM_EXIT_VMLOAD,                      "vmload" },
3435         { SVM_EXIT_VMSAVE,                      "vmsave" },
3436         { SVM_EXIT_STGI,                        "stgi" },
3437         { SVM_EXIT_CLGI,                        "clgi" },
3438         { SVM_EXIT_SKINIT,                      "skinit" },
3439         { SVM_EXIT_WBINVD,                      "wbinvd" },
3440         { SVM_EXIT_MONITOR,                     "monitor" },
3441         { SVM_EXIT_MWAIT,                       "mwait" },
3442         { SVM_EXIT_NPF,                         "npf" },
3443         { -1, NULL }
3444 };
3445
3446 static int svm_get_lpage_level(void)
3447 {
3448         return PT_PDPE_LEVEL;
3449 }
3450
3451 static bool svm_rdtscp_supported(void)
3452 {
3453         return false;
3454 }
3455
3456 static bool svm_has_wbinvd_exit(void)
3457 {
3458         return true;
3459 }
3460
3461 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3462 {
3463         struct vcpu_svm *svm = to_svm(vcpu);
3464
3465         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3466         if (is_nested(svm))
3467                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3468         update_cr0_intercept(svm);
3469 }
3470
3471 static struct kvm_x86_ops svm_x86_ops = {
3472         .cpu_has_kvm_support = has_svm,
3473         .disabled_by_bios = is_disabled,
3474         .hardware_setup = svm_hardware_setup,
3475         .hardware_unsetup = svm_hardware_unsetup,
3476         .check_processor_compatibility = svm_check_processor_compat,
3477         .hardware_enable = svm_hardware_enable,
3478         .hardware_disable = svm_hardware_disable,
3479         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3480
3481         .vcpu_create = svm_create_vcpu,
3482         .vcpu_free = svm_free_vcpu,
3483         .vcpu_reset = svm_vcpu_reset,
3484
3485         .prepare_guest_switch = svm_prepare_guest_switch,
3486         .vcpu_load = svm_vcpu_load,
3487         .vcpu_put = svm_vcpu_put,
3488
3489         .set_guest_debug = svm_guest_debug,
3490         .get_msr = svm_get_msr,
3491         .set_msr = svm_set_msr,
3492         .get_segment_base = svm_get_segment_base,
3493         .get_segment = svm_get_segment,
3494         .set_segment = svm_set_segment,
3495         .get_cpl = svm_get_cpl,
3496         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3497         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3498         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3499         .set_cr0 = svm_set_cr0,
3500         .set_cr3 = svm_set_cr3,
3501         .set_cr4 = svm_set_cr4,
3502         .set_efer = svm_set_efer,
3503         .get_idt = svm_get_idt,
3504         .set_idt = svm_set_idt,
3505         .get_gdt = svm_get_gdt,
3506         .set_gdt = svm_set_gdt,
3507         .set_dr7 = svm_set_dr7,
3508         .cache_reg = svm_cache_reg,
3509         .get_rflags = svm_get_rflags,
3510         .set_rflags = svm_set_rflags,
3511         .fpu_activate = svm_fpu_activate,
3512         .fpu_deactivate = svm_fpu_deactivate,
3513
3514         .tlb_flush = svm_flush_tlb,
3515
3516         .run = svm_vcpu_run,
3517         .handle_exit = handle_exit,
3518         .skip_emulated_instruction = skip_emulated_instruction,
3519         .set_interrupt_shadow = svm_set_interrupt_shadow,
3520         .get_interrupt_shadow = svm_get_interrupt_shadow,
3521         .patch_hypercall = svm_patch_hypercall,
3522         .set_irq = svm_set_irq,
3523         .set_nmi = svm_inject_nmi,
3524         .queue_exception = svm_queue_exception,
3525         .interrupt_allowed = svm_interrupt_allowed,
3526         .nmi_allowed = svm_nmi_allowed,
3527         .get_nmi_mask = svm_get_nmi_mask,
3528         .set_nmi_mask = svm_set_nmi_mask,
3529         .enable_nmi_window = enable_nmi_window,
3530         .enable_irq_window = enable_irq_window,
3531         .update_cr8_intercept = update_cr8_intercept,
3532
3533         .set_tss_addr = svm_set_tss_addr,
3534         .get_tdp_level = get_npt_level,
3535         .get_mt_mask = svm_get_mt_mask,
3536
3537         .exit_reasons_str = svm_exit_reasons_str,
3538         .get_lpage_level = svm_get_lpage_level,
3539
3540         .cpuid_update = svm_cpuid_update,
3541
3542         .rdtscp_supported = svm_rdtscp_supported,
3543
3544         .set_supported_cpuid = svm_set_supported_cpuid,
3545
3546         .has_wbinvd_exit = svm_has_wbinvd_exit,
3547
3548         .write_tsc_offset = svm_write_tsc_offset,
3549         .adjust_tsc_offset = svm_adjust_tsc_offset,
3550 };
3551
3552 static int __init svm_init(void)
3553 {
3554         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3555                         __alignof__(struct vcpu_svm), THIS_MODULE);
3556 }
3557
3558 static void __exit svm_exit(void)
3559 {
3560         kvm_exit();
3561 }
3562
3563 module_init(svm_init)
3564 module_exit(svm_exit)