arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #include <asm/virtext.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 #define IOPM_ALLOC_ORDER 2
  39 #define MSRPM_ALLOC_ORDER 1
  40
  41 #define SEG_TYPE_LDT 2
  42 #define SEG_TYPE_BUSY_TSS16 3
  43
  44 #define SVM_FEATURE_NPT  (1 << 0)
  45 #define SVM_FEATURE_LBRV (1 << 1)
  46 #define SVM_FEATURE_SVML (1 << 2)
  47
  48 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  49
  50 /* Turn on to get debugging output*/
  51 /* #define NESTED_DEBUG */
  52
  53 #ifdef NESTED_DEBUG
  54 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  55 #else
  56 #define nsvm_printk(fmt, args...) do {} while(0)
  57 #endif
  58
  59 /* enable NPT for AMD64 and X86 with PAE */
  60 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  61 static bool npt_enabled = true;
  62 #else
  63 static bool npt_enabled = false;
  64 #endif
  65 static int npt = 1;
  66
  67 module_param(npt, int, S_IRUGO);
  68
  69 static int nested = 0;
  70 module_param(nested, int, S_IRUGO);
  71
  72 static void kvm_reput_irq(struct vcpu_svm *svm);
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  76 static int nested_svm_vmexit(struct vcpu_svm *svm);
  77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  78                              void *arg2, void *opaque);
  79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  80                                       bool has_error_code, u32 error_code);
  81
  82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_svm, vcpu);
  85 }
  86
  87 static inline bool is_nested(struct vcpu_svm *svm)
  88 {
  89         return svm->nested_vmcb;
  90 }
  91
  92 static unsigned long iopm_base;
  93
  94 struct kvm_ldttss_desc {
  95         u16 limit0;
  96         u16 base0;
  97         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  98         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  99         u32 base3;
 100         u32 zero1;
 101 } __attribute__((packed));
 102
 103 struct svm_cpu_data {
 104         int cpu;
 105
 106         u64 asid_generation;
 107         u32 max_asid;
 108         u32 next_asid;
 109         struct kvm_ldttss_desc *tss_desc;
 110
 111         struct page *save_area;
 112 };
 113
 114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 115 static uint32_t svm_features;
 116
 117 struct svm_init_data {
 118         int cpu;
 119         int r;
 120 };
 121
 122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 123
 124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 125 #define MSRS_RANGE_SIZE 2048
 126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 127
 128 #define MAX_INST_SIZE 15
 129
 130 static inline u32 svm_has(u32 feat)
 131 {
 132         return svm_features & feat;
 133 }
 134
 135 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 136 {
 137         int word_index = __ffs(vcpu->arch.irq_summary);
 138         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 139         int irq = word_index * BITS_PER_LONG + bit_index;
 140
 141         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 142         if (!vcpu->arch.irq_pending[word_index])
 143                 clear_bit(word_index, &vcpu->arch.irq_summary);
 144         return irq;
 145 }
 146
 147 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 148 {
 149         set_bit(irq, vcpu->arch.irq_pending);
 150         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 151 }
 152
 153 static inline void clgi(void)
 154 {
 155         asm volatile (__ex(SVM_CLGI));
 156 }
 157
 158 static inline void stgi(void)
 159 {
 160         asm volatile (__ex(SVM_STGI));
 161 }
 162
 163 static inline void invlpga(unsigned long addr, u32 asid)
 164 {
 165         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 166 }
 167
 168 static inline unsigned long kvm_read_cr2(void)
 169 {
 170         unsigned long cr2;
 171
 172         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 173         return cr2;
 174 }
 175
 176 static inline void kvm_write_cr2(unsigned long val)
 177 {
 178         asm volatile ("mov %0, %%cr2" :: "r" (val));
 179 }
 180
 181 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 182 {
 183         to_svm(vcpu)->asid_generation--;
 184 }
 185
 186 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 187 {
 188         force_new_asid(vcpu);
 189 }
 190
 191 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 192 {
 193         if (!npt_enabled && !(efer & EFER_LMA))
 194                 efer &= ~EFER_LME;
 195
 196         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 197         vcpu->arch.shadow_efer = efer;
 198 }
 199
 200 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 201                                 bool has_error_code, u32 error_code)
 202 {
 203         struct vcpu_svm *svm = to_svm(vcpu);
 204
 205         /* If we are within a nested VM we'd better #VMEXIT and let the
 206            guest handle the exception */
 207         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 208                 return;
 209
 210         svm->vmcb->control.event_inj = nr
 211                 | SVM_EVTINJ_VALID
 212                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 213                 | SVM_EVTINJ_TYPE_EXEPT;
 214         svm->vmcb->control.event_inj_err = error_code;
 215 }
 216
 217 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 218 {
 219         struct vcpu_svm *svm = to_svm(vcpu);
 220
 221         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 222 }
 223
 224 static int is_external_interrupt(u32 info)
 225 {
 226         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 227         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 228 }
 229
 230 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 231 {
 232         struct vcpu_svm *svm = to_svm(vcpu);
 233
 234         if (!svm->next_rip) {
 235                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 236                 return;
 237         }
 238         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 239                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 240                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 241
 242         kvm_rip_write(vcpu, svm->next_rip);
 243         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 244
 245         vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
 246 }
 247
 248 static int has_svm(void)
 249 {
 250         const char *msg;
 251
 252         if (!cpu_has_svm(&msg)) {
 253                 printk(KERN_INFO "has_svm: %s\n", msg);
 254                 return 0;
 255         }
 256
 257         return 1;
 258 }
 259
 260 static void svm_hardware_disable(void *garbage)
 261 {
 262         cpu_svm_disable();
 263 }
 264
 265 static void svm_hardware_enable(void *garbage)
 266 {
 267
 268         struct svm_cpu_data *svm_data;
 269         uint64_t efer;
 270         struct desc_ptr gdt_descr;
 271         struct desc_struct *gdt;
 272         int me = raw_smp_processor_id();
 273
 274         if (!has_svm()) {
 275                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 276                 return;
 277         }
 278         svm_data = per_cpu(svm_data, me);
 279
 280         if (!svm_data) {
 281                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 282                        me);
 283                 return;
 284         }
 285
 286         svm_data->asid_generation = 1;
 287         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 288         svm_data->next_asid = svm_data->max_asid + 1;
 289
 290         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 291         gdt = (struct desc_struct *)gdt_descr.address;
 292         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 293
 294         rdmsrl(MSR_EFER, efer);
 295         wrmsrl(MSR_EFER, efer | EFER_SVME);
 296
 297         wrmsrl(MSR_VM_HSAVE_PA,
 298                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 299 }
 300
 301 static void svm_cpu_uninit(int cpu)
 302 {
 303         struct svm_cpu_data *svm_data
 304                 = per_cpu(svm_data, raw_smp_processor_id());
 305
 306         if (!svm_data)
 307                 return;
 308
 309         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 310         __free_page(svm_data->save_area);
 311         kfree(svm_data);
 312 }
 313
 314 static int svm_cpu_init(int cpu)
 315 {
 316         struct svm_cpu_data *svm_data;
 317         int r;
 318
 319         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 320         if (!svm_data)
 321                 return -ENOMEM;
 322         svm_data->cpu = cpu;
 323         svm_data->save_area = alloc_page(GFP_KERNEL);
 324         r = -ENOMEM;
 325         if (!svm_data->save_area)
 326                 goto err_1;
 327
 328         per_cpu(svm_data, cpu) = svm_data;
 329
 330         return 0;
 331
 332 err_1:
 333         kfree(svm_data);
 334         return r;
 335
 336 }
 337
 338 static void set_msr_interception(u32 *msrpm, unsigned msr,
 339                                  int read, int write)
 340 {
 341         int i;
 342
 343         for (i = 0; i < NUM_MSR_MAPS; i++) {
 344                 if (msr >= msrpm_ranges[i] &&
 345                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 346                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 347                                           msrpm_ranges[i]) * 2;
 348
 349                         u32 *base = msrpm + (msr_offset / 32);
 350                         u32 msr_shift = msr_offset % 32;
 351                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 352                         *base = (*base & ~(0x3 << msr_shift)) |
 353                                 (mask << msr_shift);
 354                         return;
 355                 }
 356         }
 357         BUG();
 358 }
 359
 360 static void svm_vcpu_init_msrpm(u32 *msrpm)
 361 {
 362         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 363
 364 #ifdef CONFIG_X86_64
 365         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 366         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 367         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 368         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 369         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 370         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 371 #endif
 372         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 373         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 374         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 375         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 376 }
 377
 378 static void svm_enable_lbrv(struct vcpu_svm *svm)
 379 {
 380         u32 *msrpm = svm->msrpm;
 381
 382         svm->vmcb->control.lbr_ctl = 1;
 383         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 384         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 385         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 386         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 387 }
 388
 389 static void svm_disable_lbrv(struct vcpu_svm *svm)
 390 {
 391         u32 *msrpm = svm->msrpm;
 392
 393         svm->vmcb->control.lbr_ctl = 0;
 394         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 395         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 396         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 397         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 398 }
 399
 400 static __init int svm_hardware_setup(void)
 401 {
 402         int cpu;
 403         struct page *iopm_pages;
 404         void *iopm_va;
 405         int r;
 406
 407         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 408
 409         if (!iopm_pages)
 410                 return -ENOMEM;
 411
 412         iopm_va = page_address(iopm_pages);
 413         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 414         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 415         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 416
 417         if (boot_cpu_has(X86_FEATURE_NX))
 418                 kvm_enable_efer_bits(EFER_NX);
 419
 420         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 421                 kvm_enable_efer_bits(EFER_FFXSR);
 422
 423         if (nested) {
 424                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 425                 kvm_enable_efer_bits(EFER_SVME);
 426         }
 427
 428         for_each_online_cpu(cpu) {
 429                 r = svm_cpu_init(cpu);
 430                 if (r)
 431                         goto err;
 432         }
 433
 434         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 435
 436         if (!svm_has(SVM_FEATURE_NPT))
 437                 npt_enabled = false;
 438
 439         if (npt_enabled && !npt) {
 440                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 441                 npt_enabled = false;
 442         }
 443
 444         if (npt_enabled) {
 445                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 446                 kvm_enable_tdp();
 447         } else
 448                 kvm_disable_tdp();
 449
 450         return 0;
 451
 452 err:
 453         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 454         iopm_base = 0;
 455         return r;
 456 }
 457
 458 static __exit void svm_hardware_unsetup(void)
 459 {
 460         int cpu;
 461
 462         for_each_online_cpu(cpu)
 463                 svm_cpu_uninit(cpu);
 464
 465         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 466         iopm_base = 0;
 467 }
 468
 469 static void init_seg(struct vmcb_seg *seg)
 470 {
 471         seg->selector = 0;
 472         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 473                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 474         seg->limit = 0xffff;
 475         seg->base = 0;
 476 }
 477
 478 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 479 {
 480         seg->selector = 0;
 481         seg->attrib = SVM_SELECTOR_P_MASK | type;
 482         seg->limit = 0xffff;
 483         seg->base = 0;
 484 }
 485
 486 static void init_vmcb(struct vcpu_svm *svm)
 487 {
 488         struct vmcb_control_area *control = &svm->vmcb->control;
 489         struct vmcb_save_area *save = &svm->vmcb->save;
 490
 491         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 492                                         INTERCEPT_CR3_MASK |
 493                                         INTERCEPT_CR4_MASK;
 494
 495         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 496                                         INTERCEPT_CR3_MASK |
 497                                         INTERCEPT_CR4_MASK |
 498                                         INTERCEPT_CR8_MASK;
 499
 500         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 501                                         INTERCEPT_DR1_MASK |
 502                                         INTERCEPT_DR2_MASK |
 503                                         INTERCEPT_DR3_MASK;
 504
 505         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 506                                         INTERCEPT_DR1_MASK |
 507                                         INTERCEPT_DR2_MASK |
 508                                         INTERCEPT_DR3_MASK |
 509                                         INTERCEPT_DR5_MASK |
 510                                         INTERCEPT_DR7_MASK;
 511
 512         control->intercept_exceptions = (1 << PF_VECTOR) |
 513                                         (1 << UD_VECTOR) |
 514                                         (1 << MC_VECTOR);
 515
 516
 517         control->intercept =    (1ULL << INTERCEPT_INTR) |
 518                                 (1ULL << INTERCEPT_NMI) |
 519                                 (1ULL << INTERCEPT_SMI) |
 520                                 (1ULL << INTERCEPT_CPUID) |
 521                                 (1ULL << INTERCEPT_INVD) |
 522                                 (1ULL << INTERCEPT_HLT) |
 523                                 (1ULL << INTERCEPT_INVLPG) |
 524                                 (1ULL << INTERCEPT_INVLPGA) |
 525                                 (1ULL << INTERCEPT_IOIO_PROT) |
 526                                 (1ULL << INTERCEPT_MSR_PROT) |
 527                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 528                                 (1ULL << INTERCEPT_SHUTDOWN) |
 529                                 (1ULL << INTERCEPT_VMRUN) |
 530                                 (1ULL << INTERCEPT_VMMCALL) |
 531                                 (1ULL << INTERCEPT_VMLOAD) |
 532                                 (1ULL << INTERCEPT_VMSAVE) |
 533                                 (1ULL << INTERCEPT_STGI) |
 534                                 (1ULL << INTERCEPT_CLGI) |
 535                                 (1ULL << INTERCEPT_SKINIT) |
 536                                 (1ULL << INTERCEPT_WBINVD) |
 537                                 (1ULL << INTERCEPT_MONITOR) |
 538                                 (1ULL << INTERCEPT_MWAIT);
 539
 540         control->iopm_base_pa = iopm_base;
 541         control->msrpm_base_pa = __pa(svm->msrpm);
 542         control->tsc_offset = 0;
 543         control->int_ctl = V_INTR_MASKING_MASK;
 544
 545         init_seg(&save->es);
 546         init_seg(&save->ss);
 547         init_seg(&save->ds);
 548         init_seg(&save->fs);
 549         init_seg(&save->gs);
 550
 551         save->cs.selector = 0xf000;
 552         /* Executable/Readable Code Segment */
 553         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 554                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 555         save->cs.limit = 0xffff;
 556         /*
 557          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 558          * be consistent with it.
 559          *
 560          * Replace when we have real mode working for vmx.
 561          */
 562         save->cs.base = 0xf0000;
 563
 564         save->gdtr.limit = 0xffff;
 565         save->idtr.limit = 0xffff;
 566
 567         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 568         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 569
 570         save->efer = EFER_SVME;
 571         save->dr6 = 0xffff0ff0;
 572         save->dr7 = 0x400;
 573         save->rflags = 2;
 574         save->rip = 0x0000fff0;
 575         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 576
 577         /*
 578          * cr0 val on cpu init should be 0x60000010, we enable cpu
 579          * cache by default. the orderly way is to enable cache in bios.
 580          */
 581         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 582         save->cr4 = X86_CR4_PAE;
 583         /* rdx = ?? */
 584
 585         if (npt_enabled) {
 586                 /* Setup VMCB for Nested Paging */
 587                 control->nested_ctl = 1;
 588                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 589                                         (1ULL << INTERCEPT_INVLPG));
 590                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 591                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 592                                                 INTERCEPT_CR3_MASK);
 593                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 594                                                  INTERCEPT_CR3_MASK);
 595                 save->g_pat = 0x0007040600070406ULL;
 596                 /* enable caching because the QEMU Bios doesn't enable it */
 597                 save->cr0 = X86_CR0_ET;
 598                 save->cr3 = 0;
 599                 save->cr4 = 0;
 600         }
 601         force_new_asid(&svm->vcpu);
 602
 603         svm->nested_vmcb = 0;
 604         svm->vcpu.arch.hflags = HF_GIF_MASK;
 605 }
 606
 607 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 608 {
 609         struct vcpu_svm *svm = to_svm(vcpu);
 610
 611         init_vmcb(svm);
 612
 613         if (vcpu->vcpu_id != 0) {
 614                 kvm_rip_write(vcpu, 0);
 615                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 616                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 617         }
 618         vcpu->arch.regs_avail = ~0;
 619         vcpu->arch.regs_dirty = ~0;
 620
 621         return 0;
 622 }
 623
 624 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 625 {
 626         struct vcpu_svm *svm;
 627         struct page *page;
 628         struct page *msrpm_pages;
 629         struct page *hsave_page;
 630         struct page *nested_msrpm_pages;
 631         int err;
 632
 633         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 634         if (!svm) {
 635                 err = -ENOMEM;
 636                 goto out;
 637         }
 638
 639         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 640         if (err)
 641                 goto free_svm;
 642
 643         page = alloc_page(GFP_KERNEL);
 644         if (!page) {
 645                 err = -ENOMEM;
 646                 goto uninit;
 647         }
 648
 649         err = -ENOMEM;
 650         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 651         if (!msrpm_pages)
 652                 goto uninit;
 653
 654         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 655         if (!nested_msrpm_pages)
 656                 goto uninit;
 657
 658         svm->msrpm = page_address(msrpm_pages);
 659         svm_vcpu_init_msrpm(svm->msrpm);
 660
 661         hsave_page = alloc_page(GFP_KERNEL);
 662         if (!hsave_page)
 663                 goto uninit;
 664         svm->hsave = page_address(hsave_page);
 665
 666         svm->nested_msrpm = page_address(nested_msrpm_pages);
 667
 668         svm->vmcb = page_address(page);
 669         clear_page(svm->vmcb);
 670         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 671         svm->asid_generation = 0;
 672         init_vmcb(svm);
 673
 674         fx_init(&svm->vcpu);
 675         svm->vcpu.fpu_active = 1;
 676         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 677         if (svm->vcpu.vcpu_id == 0)
 678                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 679
 680         return &svm->vcpu;
 681
 682 uninit:
 683         kvm_vcpu_uninit(&svm->vcpu);
 684 free_svm:
 685         kmem_cache_free(kvm_vcpu_cache, svm);
 686 out:
 687         return ERR_PTR(err);
 688 }
 689
 690 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 691 {
 692         struct vcpu_svm *svm = to_svm(vcpu);
 693
 694         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 695         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 696         __free_page(virt_to_page(svm->hsave));
 697         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 698         kvm_vcpu_uninit(vcpu);
 699         kmem_cache_free(kvm_vcpu_cache, svm);
 700 }
 701
 702 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 703 {
 704         struct vcpu_svm *svm = to_svm(vcpu);
 705         int i;
 706
 707         if (unlikely(cpu != vcpu->cpu)) {
 708                 u64 tsc_this, delta;
 709
 710                 /*
 711                  * Make sure that the guest sees a monotonically
 712                  * increasing TSC.
 713                  */
 714                 rdtscll(tsc_this);
 715                 delta = vcpu->arch.host_tsc - tsc_this;
 716                 svm->vmcb->control.tsc_offset += delta;
 717                 vcpu->cpu = cpu;
 718                 kvm_migrate_timers(vcpu);
 719         }
 720
 721         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 722                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 723 }
 724
 725 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 726 {
 727         struct vcpu_svm *svm = to_svm(vcpu);
 728         int i;
 729
 730         ++vcpu->stat.host_state_reload;
 731         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 732                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 733
 734         rdtscll(vcpu->arch.host_tsc);
 735 }
 736
 737 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 738 {
 739         return to_svm(vcpu)->vmcb->save.rflags;
 740 }
 741
 742 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 743 {
 744         to_svm(vcpu)->vmcb->save.rflags = rflags;
 745 }
 746
 747 static void svm_set_vintr(struct vcpu_svm *svm)
 748 {
 749         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 750 }
 751
 752 static void svm_clear_vintr(struct vcpu_svm *svm)
 753 {
 754         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 755 }
 756
 757 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 758 {
 759         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 760
 761         switch (seg) {
 762         case VCPU_SREG_CS: return &save->cs;
 763         case VCPU_SREG_DS: return &save->ds;
 764         case VCPU_SREG_ES: return &save->es;
 765         case VCPU_SREG_FS: return &save->fs;
 766         case VCPU_SREG_GS: return &save->gs;
 767         case VCPU_SREG_SS: return &save->ss;
 768         case VCPU_SREG_TR: return &save->tr;
 769         case VCPU_SREG_LDTR: return &save->ldtr;
 770         }
 771         BUG();
 772         return NULL;
 773 }
 774
 775 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 776 {
 777         struct vmcb_seg *s = svm_seg(vcpu, seg);
 778
 779         return s->base;
 780 }
 781
 782 static void svm_get_segment(struct kvm_vcpu *vcpu,
 783                             struct kvm_segment *var, int seg)
 784 {
 785         struct vmcb_seg *s = svm_seg(vcpu, seg);
 786
 787         var->base = s->base;
 788         var->limit = s->limit;
 789         var->selector = s->selector;
 790         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 791         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 792         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 793         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 794         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 795         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 796         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 797         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 798
 799         /*
 800          * SVM always stores 0 for the 'G' bit in the CS selector in
 801          * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 802          * Intel's VMENTRY has a check on the 'G' bit.
 803          */
 804         if (seg == VCPU_SREG_CS)
 805                 var->g = s->limit > 0xfffff;
 806
 807         /*
 808          * Work around a bug where the busy flag in the tr selector
 809          * isn't exposed
 810          */
 811         if (seg == VCPU_SREG_TR)
 812                 var->type |= 0x2;
 813
 814         var->unusable = !var->present;
 815 }
 816
 817 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 818 {
 819         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 820
 821         return save->cpl;
 822 }
 823
 824 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 825 {
 826         struct vcpu_svm *svm = to_svm(vcpu);
 827
 828         dt->limit = svm->vmcb->save.idtr.limit;
 829         dt->base = svm->vmcb->save.idtr.base;
 830 }
 831
 832 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 833 {
 834         struct vcpu_svm *svm = to_svm(vcpu);
 835
 836         svm->vmcb->save.idtr.limit = dt->limit;
 837         svm->vmcb->save.idtr.base = dt->base ;
 838 }
 839
 840 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 841 {
 842         struct vcpu_svm *svm = to_svm(vcpu);
 843
 844         dt->limit = svm->vmcb->save.gdtr.limit;
 845         dt->base = svm->vmcb->save.gdtr.base;
 846 }
 847
 848 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 849 {
 850         struct vcpu_svm *svm = to_svm(vcpu);
 851
 852         svm->vmcb->save.gdtr.limit = dt->limit;
 853         svm->vmcb->save.gdtr.base = dt->base ;
 854 }
 855
 856 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 857 {
 858 }
 859
 860 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 861 {
 862         struct vcpu_svm *svm = to_svm(vcpu);
 863
 864 #ifdef CONFIG_X86_64
 865         if (vcpu->arch.shadow_efer & EFER_LME) {
 866                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 867                         vcpu->arch.shadow_efer |= EFER_LMA;
 868                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 869                 }
 870
 871                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 872                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 873                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 874                 }
 875         }
 876 #endif
 877         if (npt_enabled)
 878                 goto set;
 879
 880         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 881                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 882                 vcpu->fpu_active = 1;
 883         }
 884
 885         vcpu->arch.cr0 = cr0;
 886         cr0 |= X86_CR0_PG | X86_CR0_WP;
 887         if (!vcpu->fpu_active) {
 888                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 889                 cr0 |= X86_CR0_TS;
 890         }
 891 set:
 892         /*
 893          * re-enable caching here because the QEMU bios
 894          * does not do it - this results in some delay at
 895          * reboot
 896          */
 897         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 898         svm->vmcb->save.cr0 = cr0;
 899 }
 900
 901 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 902 {
 903         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 904         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 905
 906         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 907                 force_new_asid(vcpu);
 908
 909         vcpu->arch.cr4 = cr4;
 910         if (!npt_enabled)
 911                 cr4 |= X86_CR4_PAE;
 912         cr4 |= host_cr4_mce;
 913         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 914 }
 915
 916 static void svm_set_segment(struct kvm_vcpu *vcpu,
 917                             struct kvm_segment *var, int seg)
 918 {
 919         struct vcpu_svm *svm = to_svm(vcpu);
 920         struct vmcb_seg *s = svm_seg(vcpu, seg);
 921
 922         s->base = var->base;
 923         s->limit = var->limit;
 924         s->selector = var->selector;
 925         if (var->unusable)
 926                 s->attrib = 0;
 927         else {
 928                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 929                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 930                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 931                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 932                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 933                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 934                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 935                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 936         }
 937         if (seg == VCPU_SREG_CS)
 938                 svm->vmcb->save.cpl
 939                         = (svm->vmcb->save.cs.attrib
 940                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 941
 942 }
 943
 944 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
 945 {
 946         int old_debug = vcpu->guest_debug;
 947         struct vcpu_svm *svm = to_svm(vcpu);
 948
 949         vcpu->guest_debug = dbg->control;
 950
 951         svm->vmcb->control.intercept_exceptions &=
 952                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
 953         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 954                 if (vcpu->guest_debug &
 955                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 956                         svm->vmcb->control.intercept_exceptions |=
 957                                 1 << DB_VECTOR;
 958                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 959                         svm->vmcb->control.intercept_exceptions |=
 960                                 1 << BP_VECTOR;
 961         } else
 962                 vcpu->guest_debug = 0;
 963
 964         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 965                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
 966         else
 967                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
 968
 969         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
 970                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
 971         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
 972                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 973
 974         return 0;
 975 }
 976
 977 static int svm_get_irq(struct kvm_vcpu *vcpu)
 978 {
 979         struct vcpu_svm *svm = to_svm(vcpu);
 980         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 981
 982         if (is_external_interrupt(exit_int_info))
 983                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 984         return -1;
 985 }
 986
 987 static void load_host_msrs(struct kvm_vcpu *vcpu)
 988 {
 989 #ifdef CONFIG_X86_64
 990         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 991 #endif
 992 }
 993
 994 static void save_host_msrs(struct kvm_vcpu *vcpu)
 995 {
 996 #ifdef CONFIG_X86_64
 997         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 998 #endif
 999 }
1000
1001 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1002 {
1003         if (svm_data->next_asid > svm_data->max_asid) {
1004                 ++svm_data->asid_generation;
1005                 svm_data->next_asid = 1;
1006                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1007         }
1008
1009         svm->vcpu.cpu = svm_data->cpu;
1010         svm->asid_generation = svm_data->asid_generation;
1011         svm->vmcb->control.asid = svm_data->next_asid++;
1012 }
1013
1014 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1015 {
1016         struct vcpu_svm *svm = to_svm(vcpu);
1017         unsigned long val;
1018
1019         switch (dr) {
1020         case 0 ... 3:
1021                 val = vcpu->arch.db[dr];
1022                 break;
1023         case 6:
1024                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1025                         val = vcpu->arch.dr6;
1026                 else
1027                         val = svm->vmcb->save.dr6;
1028                 break;
1029         case 7:
1030                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1031                         val = vcpu->arch.dr7;
1032                 else
1033                         val = svm->vmcb->save.dr7;
1034                 break;
1035         default:
1036                 val = 0;
1037         }
1038
1039         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1040         return val;
1041 }
1042
1043 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1044                        int *exception)
1045 {
1046         struct vcpu_svm *svm = to_svm(vcpu);
1047
1048         KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1049
1050         *exception = 0;
1051
1052         switch (dr) {
1053         case 0 ... 3:
1054                 vcpu->arch.db[dr] = value;
1055                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1056                         vcpu->arch.eff_db[dr] = value;
1057                 return;
1058         case 4 ... 5:
1059                 if (vcpu->arch.cr4 & X86_CR4_DE)
1060                         *exception = UD_VECTOR;
1061                 return;
1062         case 6:
1063                 if (value & 0xffffffff00000000ULL) {
1064                         *exception = GP_VECTOR;
1065                         return;
1066                 }
1067                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1068                 return;
1069         case 7:
1070                 if (value & 0xffffffff00000000ULL) {
1071                         *exception = GP_VECTOR;
1072                         return;
1073                 }
1074                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1075                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1076                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1077                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1078                 }
1079                 return;
1080         default:
1081                 /* FIXME: Possible case? */
1082                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1083                        __func__, dr);
1084                 *exception = UD_VECTOR;
1085                 return;
1086         }
1087 }
1088
1089 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1090 {
1091         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1092         struct kvm *kvm = svm->vcpu.kvm;
1093         u64 fault_address;
1094         u32 error_code;
1095         bool event_injection = false;
1096
1097         if (!irqchip_in_kernel(kvm) &&
1098             is_external_interrupt(exit_int_info)) {
1099                 event_injection = true;
1100                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1101         }
1102
1103         fault_address  = svm->vmcb->control.exit_info_2;
1104         error_code = svm->vmcb->control.exit_info_1;
1105
1106         if (!npt_enabled)
1107                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1108                             (u32)fault_address, (u32)(fault_address >> 32),
1109                             handler);
1110         else
1111                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1112                             (u32)fault_address, (u32)(fault_address >> 32),
1113                             handler);
1114         /*
1115          * FIXME: Tis shouldn't be necessary here, but there is a flush
1116          * missing in the MMU code. Until we find this bug, flush the
1117          * complete TLB here on an NPF
1118          */
1119         if (npt_enabled)
1120                 svm_flush_tlb(&svm->vcpu);
1121
1122         if (!npt_enabled && event_injection)
1123                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1124         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1125 }
1126
1127 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1128 {
1129         if (!(svm->vcpu.guest_debug &
1130               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1131                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1132                 return 1;
1133         }
1134         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1135         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1136         kvm_run->debug.arch.exception = DB_VECTOR;
1137         return 0;
1138 }
1139
1140 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1141 {
1142         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1143         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1144         kvm_run->debug.arch.exception = BP_VECTOR;
1145         return 0;
1146 }
1147
1148 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1149 {
1150         int er;
1151
1152         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1153         if (er != EMULATE_DONE)
1154                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1155         return 1;
1156 }
1157
1158 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1159 {
1160         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1161         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1162                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1163         svm->vcpu.fpu_active = 1;
1164
1165         return 1;
1166 }
1167
1168 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1169 {
1170         /*
1171          * On an #MC intercept the MCE handler is not called automatically in
1172          * the host. So do it by hand here.
1173          */
1174         asm volatile (
1175                 "int $0x12\n");
1176         /* not sure if we ever come back to this point */
1177
1178         return 1;
1179 }
1180
1181 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1182 {
1183         /*
1184          * VMCB is undefined after a SHUTDOWN intercept
1185          * so reinitialize it.
1186          */
1187         clear_page(svm->vmcb);
1188         init_vmcb(svm);
1189
1190         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1191         return 0;
1192 }
1193
1194 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1195 {
1196         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1197         int size, down, in, string, rep;
1198         unsigned port;
1199
1200         ++svm->vcpu.stat.io_exits;
1201
1202         svm->next_rip = svm->vmcb->control.exit_info_2;
1203
1204         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1205
1206         if (string) {
1207                 if (emulate_instruction(&svm->vcpu,
1208                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1209                         return 0;
1210                 return 1;
1211         }
1212
1213         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1214         port = io_info >> 16;
1215         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1216         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1217         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1218
1219         skip_emulated_instruction(&svm->vcpu);
1220         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1221 }
1222
1223 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1224 {
1225         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1226         return 1;
1227 }
1228
1229 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1230 {
1231         ++svm->vcpu.stat.irq_exits;
1232         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1233         return 1;
1234 }
1235
1236 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1237 {
1238         return 1;
1239 }
1240
1241 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1242 {
1243         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1244         skip_emulated_instruction(&svm->vcpu);
1245         return kvm_emulate_halt(&svm->vcpu);
1246 }
1247
1248 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1249 {
1250         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1251         skip_emulated_instruction(&svm->vcpu);
1252         kvm_emulate_hypercall(&svm->vcpu);
1253         return 1;
1254 }
1255
1256 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1257 {
1258         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1259             || !is_paging(&svm->vcpu)) {
1260                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1261                 return 1;
1262         }
1263
1264         if (svm->vmcb->save.cpl) {
1265                 kvm_inject_gp(&svm->vcpu, 0);
1266                 return 1;
1267         }
1268
1269        return 0;
1270 }
1271
1272 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1273                                       bool has_error_code, u32 error_code)
1274 {
1275         if (is_nested(svm)) {
1276                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1277                 svm->vmcb->control.exit_code_hi = 0;
1278                 svm->vmcb->control.exit_info_1 = error_code;
1279                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1280                 if (nested_svm_exit_handled(svm, false)) {
1281                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1282
1283                         nested_svm_vmexit(svm);
1284                         return 1;
1285                 }
1286         }
1287
1288         return 0;
1289 }
1290
1291 static inline int nested_svm_intr(struct vcpu_svm *svm)
1292 {
1293         if (is_nested(svm)) {
1294                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1295                         return 0;
1296
1297                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1298                         return 0;
1299
1300                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1301
1302                 if (nested_svm_exit_handled(svm, false)) {
1303                         nsvm_printk("VMexit -> INTR\n");
1304                         nested_svm_vmexit(svm);
1305                         return 1;
1306                 }
1307         }
1308
1309         return 0;
1310 }
1311
1312 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1313 {
1314         struct page *page;
1315
1316         down_read(&current->mm->mmap_sem);
1317         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1318         up_read(&current->mm->mmap_sem);
1319
1320         if (is_error_page(page)) {
1321                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1322                        __func__, gpa);
1323                 kvm_release_page_clean(page);
1324                 kvm_inject_gp(&svm->vcpu, 0);
1325                 return NULL;
1326         }
1327         return page;
1328 }
1329
1330 static int nested_svm_do(struct vcpu_svm *svm,
1331                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1332                          int (*handler)(struct vcpu_svm *svm,
1333                                         void *arg1,
1334                                         void *arg2,
1335                                         void *opaque))
1336 {
1337         struct page *arg1_page;
1338         struct page *arg2_page = NULL;
1339         void *arg1;
1340         void *arg2 = NULL;
1341         int retval;
1342
1343         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1344         if(arg1_page == NULL)
1345                 return 1;
1346
1347         if (arg2_gpa) {
1348                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1349                 if(arg2_page == NULL) {
1350                         kvm_release_page_clean(arg1_page);
1351                         return 1;
1352                 }
1353         }
1354
1355         arg1 = kmap_atomic(arg1_page, KM_USER0);
1356         if (arg2_gpa)
1357                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1358
1359         retval = handler(svm, arg1, arg2, opaque);
1360
1361         kunmap_atomic(arg1, KM_USER0);
1362         if (arg2_gpa)
1363                 kunmap_atomic(arg2, KM_USER1);
1364
1365         kvm_release_page_dirty(arg1_page);
1366         if (arg2_gpa)
1367                 kvm_release_page_dirty(arg2_page);
1368
1369         return retval;
1370 }
1371
1372 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1373                                         void *arg1,
1374                                         void *arg2,
1375                                         void *opaque)
1376 {
1377         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1378         bool kvm_overrides = *(bool *)opaque;
1379         u32 exit_code = svm->vmcb->control.exit_code;
1380
1381         if (kvm_overrides) {
1382                 switch (exit_code) {
1383                 case SVM_EXIT_INTR:
1384                 case SVM_EXIT_NMI:
1385                         return 0;
1386                 /* For now we are always handling NPFs when using them */
1387                 case SVM_EXIT_NPF:
1388                         if (npt_enabled)
1389                                 return 0;
1390                         break;
1391                 /* When we're shadowing, trap PFs */
1392                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1393                         if (!npt_enabled)
1394                                 return 0;
1395                         break;
1396                 default:
1397                         break;
1398                 }
1399         }
1400
1401         switch (exit_code) {
1402         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1403                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1404                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1405                         return 1;
1406                 break;
1407         }
1408         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1409                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1410                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1411                         return 1;
1412                 break;
1413         }
1414         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1415                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1416                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1417                         return 1;
1418                 break;
1419         }
1420         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1421                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1422                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1423                         return 1;
1424                 break;
1425         }
1426         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1427                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1428                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1429                         return 1;
1430                 break;
1431         }
1432         default: {
1433                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1434                 nsvm_printk("exit code: 0x%x\n", exit_code);
1435                 if (nested_vmcb->control.intercept & exit_bits)
1436                         return 1;
1437         }
1438         }
1439
1440         return 0;
1441 }
1442
1443 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1444                                        void *arg1, void *arg2,
1445                                        void *opaque)
1446 {
1447         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1448         u8 *msrpm = (u8 *)arg2;
1449         u32 t0, t1;
1450         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1451         u32 param = svm->vmcb->control.exit_info_1 & 1;
1452
1453         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1454                 return 0;
1455
1456         switch(msr) {
1457         case 0 ... 0x1fff:
1458                 t0 = (msr * 2) % 8;
1459                 t1 = msr / 8;
1460                 break;
1461         case 0xc0000000 ... 0xc0001fff:
1462                 t0 = (8192 + msr - 0xc0000000) * 2;
1463                 t1 = (t0 / 8);
1464                 t0 %= 8;
1465                 break;
1466         case 0xc0010000 ... 0xc0011fff:
1467                 t0 = (16384 + msr - 0xc0010000) * 2;
1468                 t1 = (t0 / 8);
1469                 t0 %= 8;
1470                 break;
1471         default:
1472                 return 1;
1473                 break;
1474         }
1475         if (msrpm[t1] & ((1 << param) << t0))
1476                 return 1;
1477
1478         return 0;
1479 }
1480
1481 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1482 {
1483         bool k = kvm_override;
1484
1485         switch (svm->vmcb->control.exit_code) {
1486         case SVM_EXIT_MSR:
1487                 return nested_svm_do(svm, svm->nested_vmcb,
1488                                      svm->nested_vmcb_msrpm, NULL,
1489                                      nested_svm_exit_handled_msr);
1490         default: break;
1491         }
1492
1493         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1494                              nested_svm_exit_handled_real);
1495 }
1496
1497 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1498                                   void *arg2, void *opaque)
1499 {
1500         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1501         struct vmcb *hsave = svm->hsave;
1502         u64 nested_save[] = { nested_vmcb->save.cr0,
1503                               nested_vmcb->save.cr3,
1504                               nested_vmcb->save.cr4,
1505                               nested_vmcb->save.efer,
1506                               nested_vmcb->control.intercept_cr_read,
1507                               nested_vmcb->control.intercept_cr_write,
1508                               nested_vmcb->control.intercept_dr_read,
1509                               nested_vmcb->control.intercept_dr_write,
1510                               nested_vmcb->control.intercept_exceptions,
1511                               nested_vmcb->control.intercept,
1512                               nested_vmcb->control.msrpm_base_pa,
1513                               nested_vmcb->control.iopm_base_pa,
1514                               nested_vmcb->control.tsc_offset };
1515
1516         /* Give the current vmcb to the guest */
1517         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1518         nested_vmcb->save.cr0 = nested_save[0];
1519         if (!npt_enabled)
1520                 nested_vmcb->save.cr3 = nested_save[1];
1521         nested_vmcb->save.cr4 = nested_save[2];
1522         nested_vmcb->save.efer = nested_save[3];
1523         nested_vmcb->control.intercept_cr_read = nested_save[4];
1524         nested_vmcb->control.intercept_cr_write = nested_save[5];
1525         nested_vmcb->control.intercept_dr_read = nested_save[6];
1526         nested_vmcb->control.intercept_dr_write = nested_save[7];
1527         nested_vmcb->control.intercept_exceptions = nested_save[8];
1528         nested_vmcb->control.intercept = nested_save[9];
1529         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1530         nested_vmcb->control.iopm_base_pa = nested_save[11];
1531         nested_vmcb->control.tsc_offset = nested_save[12];
1532
1533         /* We always set V_INTR_MASKING and remember the old value in hflags */
1534         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1535                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1536
1537         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1538             (nested_vmcb->control.int_vector)) {
1539                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1540                                 nested_vmcb->control.int_vector);
1541         }
1542
1543         /* Restore the original control entries */
1544         svm->vmcb->control = hsave->control;
1545
1546         /* Kill any pending exceptions */
1547         if (svm->vcpu.arch.exception.pending == true)
1548                 nsvm_printk("WARNING: Pending Exception\n");
1549         svm->vcpu.arch.exception.pending = false;
1550
1551         /* Restore selected save entries */
1552         svm->vmcb->save.es = hsave->save.es;
1553         svm->vmcb->save.cs = hsave->save.cs;
1554         svm->vmcb->save.ss = hsave->save.ss;
1555         svm->vmcb->save.ds = hsave->save.ds;
1556         svm->vmcb->save.gdtr = hsave->save.gdtr;
1557         svm->vmcb->save.idtr = hsave->save.idtr;
1558         svm->vmcb->save.rflags = hsave->save.rflags;
1559         svm_set_efer(&svm->vcpu, hsave->save.efer);
1560         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1561         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1562         if (npt_enabled) {
1563                 svm->vmcb->save.cr3 = hsave->save.cr3;
1564                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1565         } else {
1566                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1567         }
1568         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1569         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1570         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1571         svm->vmcb->save.dr7 = 0;
1572         svm->vmcb->save.cpl = 0;
1573         svm->vmcb->control.exit_int_info = 0;
1574
1575         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1576         /* Exit nested SVM mode */
1577         svm->nested_vmcb = 0;
1578
1579         return 0;
1580 }
1581
1582 static int nested_svm_vmexit(struct vcpu_svm *svm)
1583 {
1584         nsvm_printk("VMexit\n");
1585         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1586                           NULL, nested_svm_vmexit_real))
1587                 return 1;
1588
1589         kvm_mmu_reset_context(&svm->vcpu);
1590         kvm_mmu_load(&svm->vcpu);
1591
1592         return 0;
1593 }
1594
1595 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1596                                   void *arg2, void *opaque)
1597 {
1598         int i;
1599         u32 *nested_msrpm = (u32*)arg1;
1600         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1601                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1602         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1603
1604         return 0;
1605 }
1606
1607 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1608                             void *arg2, void *opaque)
1609 {
1610         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1611         struct vmcb *hsave = svm->hsave;
1612
1613         /* nested_vmcb is our indicator if nested SVM is activated */
1614         svm->nested_vmcb = svm->vmcb->save.rax;
1615
1616         /* Clear internal status */
1617         svm->vcpu.arch.exception.pending = false;
1618
1619         /* Save the old vmcb, so we don't need to pick what we save, but
1620            can restore everything when a VMEXIT occurs */
1621         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1622         /* We need to remember the original CR3 in the SPT case */
1623         if (!npt_enabled)
1624                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1625         hsave->save.cr4 = svm->vcpu.arch.cr4;
1626         hsave->save.rip = svm->next_rip;
1627
1628         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1629                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1630         else
1631                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1632
1633         /* Load the nested guest state */
1634         svm->vmcb->save.es = nested_vmcb->save.es;
1635         svm->vmcb->save.cs = nested_vmcb->save.cs;
1636         svm->vmcb->save.ss = nested_vmcb->save.ss;
1637         svm->vmcb->save.ds = nested_vmcb->save.ds;
1638         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1639         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1640         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1641         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1642         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1643         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1644         if (npt_enabled) {
1645                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1646                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1647         } else {
1648                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1649                 kvm_mmu_reset_context(&svm->vcpu);
1650         }
1651         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1652         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1653         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1654         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1655         /* In case we don't even reach vcpu_run, the fields are not updated */
1656         svm->vmcb->save.rax = nested_vmcb->save.rax;
1657         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1658         svm->vmcb->save.rip = nested_vmcb->save.rip;
1659         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1660         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1661         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1662
1663         /* We don't want a nested guest to be more powerful than the guest,
1664            so all intercepts are ORed */
1665         svm->vmcb->control.intercept_cr_read |=
1666                 nested_vmcb->control.intercept_cr_read;
1667         svm->vmcb->control.intercept_cr_write |=
1668                 nested_vmcb->control.intercept_cr_write;
1669         svm->vmcb->control.intercept_dr_read |=
1670                 nested_vmcb->control.intercept_dr_read;
1671         svm->vmcb->control.intercept_dr_write |=
1672                 nested_vmcb->control.intercept_dr_write;
1673         svm->vmcb->control.intercept_exceptions |=
1674                 nested_vmcb->control.intercept_exceptions;
1675
1676         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1677
1678         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1679
1680         force_new_asid(&svm->vcpu);
1681         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1682         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1683         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1684         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1685                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1686                                 nested_vmcb->control.int_ctl);
1687         }
1688         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1689                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1690         else
1691                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1692
1693         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1694                         nested_vmcb->control.exit_int_info,
1695                         nested_vmcb->control.int_state);
1696
1697         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1698         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1699         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1700         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1701                 nsvm_printk("Injecting Event: 0x%x\n",
1702                                 nested_vmcb->control.event_inj);
1703         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1704         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1705
1706         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1707
1708         return 0;
1709 }
1710
1711 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1712 {
1713         to_vmcb->save.fs = from_vmcb->save.fs;
1714         to_vmcb->save.gs = from_vmcb->save.gs;
1715         to_vmcb->save.tr = from_vmcb->save.tr;
1716         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1717         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1718         to_vmcb->save.star = from_vmcb->save.star;
1719         to_vmcb->save.lstar = from_vmcb->save.lstar;
1720         to_vmcb->save.cstar = from_vmcb->save.cstar;
1721         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1722         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1723         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1724         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1725
1726         return 1;
1727 }
1728
1729 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1730                              void *arg2, void *opaque)
1731 {
1732         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1733 }
1734
1735 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1736                              void *arg2, void *opaque)
1737 {
1738         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1739 }
1740
1741 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1742 {
1743         if (nested_svm_check_permissions(svm))
1744                 return 1;
1745
1746         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1747         skip_emulated_instruction(&svm->vcpu);
1748
1749         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1750
1751         return 1;
1752 }
1753
1754 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1755 {
1756         if (nested_svm_check_permissions(svm))
1757                 return 1;
1758
1759         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1760         skip_emulated_instruction(&svm->vcpu);
1761
1762         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1763
1764         return 1;
1765 }
1766
1767 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1768 {
1769         nsvm_printk("VMrun\n");
1770         if (nested_svm_check_permissions(svm))
1771                 return 1;
1772
1773         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1774         skip_emulated_instruction(&svm->vcpu);
1775
1776         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1777                           NULL, nested_svm_vmrun))
1778                 return 1;
1779
1780         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1781                       NULL, nested_svm_vmrun_msrpm))
1782                 return 1;
1783
1784         return 1;
1785 }
1786
1787 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1788 {
1789         if (nested_svm_check_permissions(svm))
1790                 return 1;
1791
1792         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1793         skip_emulated_instruction(&svm->vcpu);
1794
1795         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1796
1797         return 1;
1798 }
1799
1800 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1801 {
1802         if (nested_svm_check_permissions(svm))
1803                 return 1;
1804
1805         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1806         skip_emulated_instruction(&svm->vcpu);
1807
1808         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1809
1810         /* After a CLGI no interrupts should come */
1811         svm_clear_vintr(svm);
1812         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1813
1814         return 1;
1815 }
1816
1817 static int invalid_op_interception(struct vcpu_svm *svm,
1818                                    struct kvm_run *kvm_run)
1819 {
1820         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1821         return 1;
1822 }
1823
1824 static int task_switch_interception(struct vcpu_svm *svm,
1825                                     struct kvm_run *kvm_run)
1826 {
1827         u16 tss_selector;
1828
1829         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1830         if (svm->vmcb->control.exit_info_2 &
1831             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1832                 return kvm_task_switch(&svm->vcpu, tss_selector,
1833                                        TASK_SWITCH_IRET);
1834         if (svm->vmcb->control.exit_info_2 &
1835             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1836                 return kvm_task_switch(&svm->vcpu, tss_selector,
1837                                        TASK_SWITCH_JMP);
1838         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1839 }
1840
1841 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1842 {
1843         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1844         kvm_emulate_cpuid(&svm->vcpu);
1845         return 1;
1846 }
1847
1848 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1849 {
1850         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1851                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1852         return 1;
1853 }
1854
1855 static int emulate_on_interception(struct vcpu_svm *svm,
1856                                    struct kvm_run *kvm_run)
1857 {
1858         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1859                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1860         return 1;
1861 }
1862
1863 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1864 {
1865         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1866         if (irqchip_in_kernel(svm->vcpu.kvm))
1867                 return 1;
1868         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1869         return 0;
1870 }
1871
1872 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1873 {
1874         struct vcpu_svm *svm = to_svm(vcpu);
1875
1876         switch (ecx) {
1877         case MSR_IA32_TIME_STAMP_COUNTER: {
1878                 u64 tsc;
1879
1880                 rdtscll(tsc);
1881                 *data = svm->vmcb->control.tsc_offset + tsc;
1882                 break;
1883         }
1884         case MSR_K6_STAR:
1885                 *data = svm->vmcb->save.star;
1886                 break;
1887 #ifdef CONFIG_X86_64
1888         case MSR_LSTAR:
1889                 *data = svm->vmcb->save.lstar;
1890                 break;
1891         case MSR_CSTAR:
1892                 *data = svm->vmcb->save.cstar;
1893                 break;
1894         case MSR_KERNEL_GS_BASE:
1895                 *data = svm->vmcb->save.kernel_gs_base;
1896                 break;
1897         case MSR_SYSCALL_MASK:
1898                 *data = svm->vmcb->save.sfmask;
1899                 break;
1900 #endif
1901         case MSR_IA32_SYSENTER_CS:
1902                 *data = svm->vmcb->save.sysenter_cs;
1903                 break;
1904         case MSR_IA32_SYSENTER_EIP:
1905                 *data = svm->vmcb->save.sysenter_eip;
1906                 break;
1907         case MSR_IA32_SYSENTER_ESP:
1908                 *data = svm->vmcb->save.sysenter_esp;
1909                 break;
1910         /* Nobody will change the following 5 values in the VMCB so
1911            we can safely return them on rdmsr. They will always be 0
1912            until LBRV is implemented. */
1913         case MSR_IA32_DEBUGCTLMSR:
1914                 *data = svm->vmcb->save.dbgctl;
1915                 break;
1916         case MSR_IA32_LASTBRANCHFROMIP:
1917                 *data = svm->vmcb->save.br_from;
1918                 break;
1919         case MSR_IA32_LASTBRANCHTOIP:
1920                 *data = svm->vmcb->save.br_to;
1921                 break;
1922         case MSR_IA32_LASTINTFROMIP:
1923                 *data = svm->vmcb->save.last_excp_from;
1924                 break;
1925         case MSR_IA32_LASTINTTOIP:
1926                 *data = svm->vmcb->save.last_excp_to;
1927                 break;
1928         case MSR_VM_HSAVE_PA:
1929                 *data = svm->hsave_msr;
1930                 break;
1931         case MSR_VM_CR:
1932                 *data = 0;
1933                 break;
1934         case MSR_IA32_UCODE_REV:
1935                 *data = 0x01000065;
1936                 break;
1937         default:
1938                 return kvm_get_msr_common(vcpu, ecx, data);
1939         }
1940         return 0;
1941 }
1942
1943 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1944 {
1945         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1946         u64 data;
1947
1948         if (svm_get_msr(&svm->vcpu, ecx, &data))
1949                 kvm_inject_gp(&svm->vcpu, 0);
1950         else {
1951                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1952                             (u32)(data >> 32), handler);
1953
1954                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1955                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1956                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1957                 skip_emulated_instruction(&svm->vcpu);
1958         }
1959         return 1;
1960 }
1961
1962 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1963 {
1964         struct vcpu_svm *svm = to_svm(vcpu);
1965
1966         switch (ecx) {
1967         case MSR_IA32_TIME_STAMP_COUNTER: {
1968                 u64 tsc;
1969
1970                 rdtscll(tsc);
1971                 svm->vmcb->control.tsc_offset = data - tsc;
1972                 break;
1973         }
1974         case MSR_K6_STAR:
1975                 svm->vmcb->save.star = data;
1976                 break;
1977 #ifdef CONFIG_X86_64
1978         case MSR_LSTAR:
1979                 svm->vmcb->save.lstar = data;
1980                 break;
1981         case MSR_CSTAR:
1982                 svm->vmcb->save.cstar = data;
1983                 break;
1984         case MSR_KERNEL_GS_BASE:
1985                 svm->vmcb->save.kernel_gs_base = data;
1986                 break;
1987         case MSR_SYSCALL_MASK:
1988                 svm->vmcb->save.sfmask = data;
1989                 break;
1990 #endif
1991         case MSR_IA32_SYSENTER_CS:
1992                 svm->vmcb->save.sysenter_cs = data;
1993                 break;
1994         case MSR_IA32_SYSENTER_EIP:
1995                 svm->vmcb->save.sysenter_eip = data;
1996                 break;
1997         case MSR_IA32_SYSENTER_ESP:
1998                 svm->vmcb->save.sysenter_esp = data;
1999                 break;
2000         case MSR_IA32_DEBUGCTLMSR:
2001                 if (!svm_has(SVM_FEATURE_LBRV)) {
2002                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2003                                         __func__, data);
2004                         break;
2005                 }
2006                 if (data & DEBUGCTL_RESERVED_BITS)
2007                         return 1;
2008
2009                 svm->vmcb->save.dbgctl = data;
2010                 if (data & (1ULL<<0))
2011                         svm_enable_lbrv(svm);
2012                 else
2013                         svm_disable_lbrv(svm);
2014                 break;
2015         case MSR_K7_EVNTSEL0:
2016         case MSR_K7_EVNTSEL1:
2017         case MSR_K7_EVNTSEL2:
2018         case MSR_K7_EVNTSEL3:
2019         case MSR_K7_PERFCTR0:
2020         case MSR_K7_PERFCTR1:
2021         case MSR_K7_PERFCTR2:
2022         case MSR_K7_PERFCTR3:
2023                 /*
2024                  * Just discard all writes to the performance counters; this
2025                  * should keep both older linux and windows 64-bit guests
2026                  * happy
2027                  */
2028                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2029
2030                 break;
2031         case MSR_VM_HSAVE_PA:
2032                 svm->hsave_msr = data;
2033                 break;
2034         default:
2035                 return kvm_set_msr_common(vcpu, ecx, data);
2036         }
2037         return 0;
2038 }
2039
2040 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2041 {
2042         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2043         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2044                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2045
2046         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2047                     handler);
2048
2049         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2050         if (svm_set_msr(&svm->vcpu, ecx, data))
2051                 kvm_inject_gp(&svm->vcpu, 0);
2052         else
2053                 skip_emulated_instruction(&svm->vcpu);
2054         return 1;
2055 }
2056
2057 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2058 {
2059         if (svm->vmcb->control.exit_info_1)
2060                 return wrmsr_interception(svm, kvm_run);
2061         else
2062                 return rdmsr_interception(svm, kvm_run);
2063 }
2064
2065 static int interrupt_window_interception(struct vcpu_svm *svm,
2066                                    struct kvm_run *kvm_run)
2067 {
2068         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2069
2070         svm_clear_vintr(svm);
2071         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2072         /*
2073          * If the user space waits to inject interrupts, exit as soon as
2074          * possible
2075          */
2076         if (kvm_run->request_interrupt_window &&
2077             !svm->vcpu.arch.irq_summary) {
2078                 ++svm->vcpu.stat.irq_window_exits;
2079                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2080                 return 0;
2081         }
2082
2083         return 1;
2084 }
2085
2086 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2087                                       struct kvm_run *kvm_run) = {
2088         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2089         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2090         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2091         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2092         /* for now: */
2093         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2094         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2095         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2096         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2097         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2098         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2099         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2100         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2101         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2102         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2103         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2104         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2105         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2106         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2107         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2108         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2109         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2110         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2111         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2112         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2113         [SVM_EXIT_INTR]                         = intr_interception,
2114         [SVM_EXIT_NMI]                          = nmi_interception,
2115         [SVM_EXIT_SMI]                          = nop_on_interception,
2116         [SVM_EXIT_INIT]                         = nop_on_interception,
2117         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2118         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2119         [SVM_EXIT_CPUID]                        = cpuid_interception,
2120         [SVM_EXIT_INVD]                         = emulate_on_interception,
2121         [SVM_EXIT_HLT]                          = halt_interception,
2122         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2123         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2124         [SVM_EXIT_IOIO]                         = io_interception,
2125         [SVM_EXIT_MSR]                          = msr_interception,
2126         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2127         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2128         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2129         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2130         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2131         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2132         [SVM_EXIT_STGI]                         = stgi_interception,
2133         [SVM_EXIT_CLGI]                         = clgi_interception,
2134         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2135         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2136         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2137         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2138         [SVM_EXIT_NPF]                          = pf_interception,
2139 };
2140
2141 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2142 {
2143         struct vcpu_svm *svm = to_svm(vcpu);
2144         u32 exit_code = svm->vmcb->control.exit_code;
2145
2146         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2147                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2148
2149         if (is_nested(svm)) {
2150                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2151                             exit_code, svm->vmcb->control.exit_info_1,
2152                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2153                 if (nested_svm_exit_handled(svm, true)) {
2154                         nested_svm_vmexit(svm);
2155                         nsvm_printk("-> #VMEXIT\n");
2156                         return 1;
2157                 }
2158         }
2159
2160         if (npt_enabled) {
2161                 int mmu_reload = 0;
2162                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2163                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2164                         mmu_reload = 1;
2165                 }
2166                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2167                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2168                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2169                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2170                                 kvm_inject_gp(vcpu, 0);
2171                                 return 1;
2172                         }
2173                 }
2174                 if (mmu_reload) {
2175                         kvm_mmu_reset_context(vcpu);
2176                         kvm_mmu_load(vcpu);
2177                 }
2178         }
2179
2180         kvm_reput_irq(svm);
2181
2182         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2183                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2184                 kvm_run->fail_entry.hardware_entry_failure_reason
2185                         = svm->vmcb->control.exit_code;
2186                 return 0;
2187         }
2188
2189         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2190             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2191             exit_code != SVM_EXIT_NPF)
2192                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2193                        "exit_code 0x%x\n",
2194                        __func__, svm->vmcb->control.exit_int_info,
2195                        exit_code);
2196
2197         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2198             || !svm_exit_handlers[exit_code]) {
2199                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2200                 kvm_run->hw.hardware_exit_reason = exit_code;
2201                 return 0;
2202         }
2203
2204         return svm_exit_handlers[exit_code](svm, kvm_run);
2205 }
2206
2207 static void reload_tss(struct kvm_vcpu *vcpu)
2208 {
2209         int cpu = raw_smp_processor_id();
2210
2211         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2212         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2213         load_TR_desc();
2214 }
2215
2216 static void pre_svm_run(struct vcpu_svm *svm)
2217 {
2218         int cpu = raw_smp_processor_id();
2219
2220         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2221
2222         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2223         if (svm->vcpu.cpu != cpu ||
2224             svm->asid_generation != svm_data->asid_generation)
2225                 new_asid(svm, svm_data);
2226 }
2227
2228
2229 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2230 {
2231         struct vmcb_control_area *control;
2232
2233         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2234
2235         ++svm->vcpu.stat.irq_injections;
2236         control = &svm->vmcb->control;
2237         control->int_vector = irq;
2238         control->int_ctl &= ~V_INTR_PRIO_MASK;
2239         control->int_ctl |= V_IRQ_MASK |
2240                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2241 }
2242
2243 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2244 {
2245         struct vcpu_svm *svm = to_svm(vcpu);
2246
2247         nested_svm_intr(svm);
2248
2249         svm_inject_irq(svm, irq);
2250 }
2251
2252 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2253 {
2254         struct vcpu_svm *svm = to_svm(vcpu);
2255         struct vmcb *vmcb = svm->vmcb;
2256         int max_irr, tpr;
2257
2258         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2259                 return;
2260
2261         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2262
2263         max_irr = kvm_lapic_find_highest_irr(vcpu);
2264         if (max_irr == -1)
2265                 return;
2266
2267         tpr = kvm_lapic_get_cr8(vcpu) << 4;
2268
2269         if (tpr >= (max_irr & 0xf0))
2270                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2271 }
2272
2273 static void svm_intr_assist(struct kvm_vcpu *vcpu)
2274 {
2275         struct vcpu_svm *svm = to_svm(vcpu);
2276         struct vmcb *vmcb = svm->vmcb;
2277         int intr_vector = -1;
2278
2279         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
2280             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
2281                 intr_vector = vmcb->control.exit_int_info &
2282                               SVM_EVTINJ_VEC_MASK;
2283                 vmcb->control.exit_int_info = 0;
2284                 svm_inject_irq(svm, intr_vector);
2285                 goto out;
2286         }
2287
2288         if (vmcb->control.int_ctl & V_IRQ_MASK)
2289                 goto out;
2290
2291         if (!kvm_cpu_has_interrupt(vcpu))
2292                 goto out;
2293
2294         if (nested_svm_intr(svm))
2295                 goto out;
2296
2297         if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
2298                 goto out;
2299
2300         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
2301             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
2302             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
2303                 /* unable to deliver irq, set pending irq */
2304                 svm_set_vintr(svm);
2305                 svm_inject_irq(svm, 0x0);
2306                 goto out;
2307         }
2308         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
2309         intr_vector = kvm_cpu_get_interrupt(vcpu);
2310         svm_inject_irq(svm, intr_vector);
2311 out:
2312         update_cr8_intercept(vcpu);
2313 }
2314
2315 static void kvm_reput_irq(struct vcpu_svm *svm)
2316 {
2317         struct vmcb_control_area *control = &svm->vmcb->control;
2318
2319         if ((control->int_ctl & V_IRQ_MASK)
2320             && !irqchip_in_kernel(svm->vcpu.kvm)) {
2321                 control->int_ctl &= ~V_IRQ_MASK;
2322                 push_irq(&svm->vcpu, control->int_vector);
2323         }
2324
2325         svm->vcpu.arch.interrupt_window_open =
2326                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2327                  (svm->vcpu.arch.hflags & HF_GIF_MASK);
2328 }
2329
2330 static void svm_do_inject_vector(struct vcpu_svm *svm)
2331 {
2332         struct kvm_vcpu *vcpu = &svm->vcpu;
2333         int word_index = __ffs(vcpu->arch.irq_summary);
2334         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2335         int irq = word_index * BITS_PER_LONG + bit_index;
2336
2337         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2338         if (!vcpu->arch.irq_pending[word_index])
2339                 clear_bit(word_index, &vcpu->arch.irq_summary);
2340         svm_inject_irq(svm, irq);
2341 }
2342
2343 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2344                                        struct kvm_run *kvm_run)
2345 {
2346         struct vcpu_svm *svm = to_svm(vcpu);
2347         struct vmcb_control_area *control = &svm->vmcb->control;
2348
2349         if (nested_svm_intr(svm))
2350                 return;
2351
2352         svm->vcpu.arch.interrupt_window_open =
2353                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2354                  (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
2355                  (svm->vcpu.arch.hflags & HF_GIF_MASK));
2356
2357         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
2358                 /*
2359                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2360                  */
2361                 svm_do_inject_vector(svm);
2362
2363         /*
2364          * Interrupts blocked.  Wait for unblock.
2365          */
2366         if (!svm->vcpu.arch.interrupt_window_open &&
2367             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
2368                 svm_set_vintr(svm);
2369         else
2370                 svm_clear_vintr(svm);
2371 }
2372
2373 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2374 {
2375         return 0;
2376 }
2377
2378 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2379 {
2380         force_new_asid(vcpu);
2381 }
2382
2383 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2384 {
2385 }
2386
2387 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2388 {
2389         struct vcpu_svm *svm = to_svm(vcpu);
2390
2391         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2392                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2393                 kvm_lapic_set_tpr(vcpu, cr8);
2394         }
2395 }
2396
2397 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2398 {
2399         struct vcpu_svm *svm = to_svm(vcpu);
2400         u64 cr8;
2401
2402         if (!irqchip_in_kernel(vcpu->kvm))
2403                 return;
2404
2405         cr8 = kvm_get_cr8(vcpu);
2406         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2407         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2408 }
2409
2410 #ifdef CONFIG_X86_64
2411 #define R "r"
2412 #else
2413 #define R "e"
2414 #endif
2415
2416 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2417 {
2418         struct vcpu_svm *svm = to_svm(vcpu);
2419         u16 fs_selector;
2420         u16 gs_selector;
2421         u16 ldt_selector;
2422
2423         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2424         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2425         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2426
2427         pre_svm_run(svm);
2428
2429         sync_lapic_to_cr8(vcpu);
2430
2431         save_host_msrs(vcpu);
2432         fs_selector = kvm_read_fs();
2433         gs_selector = kvm_read_gs();
2434         ldt_selector = kvm_read_ldt();
2435         svm->host_cr2 = kvm_read_cr2();
2436         if (!is_nested(svm))
2437                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2438         /* required for live migration with NPT */
2439         if (npt_enabled)
2440                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2441
2442         clgi();
2443
2444         local_irq_enable();
2445
2446         asm volatile (
2447                 "push %%"R"bp; \n\t"
2448                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2449                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2450                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2451                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2452                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2453                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2454 #ifdef CONFIG_X86_64
2455                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2456                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2457                 "mov %c[r10](%[svm]), %%r10 \n\t"
2458                 "mov %c[r11](%[svm]), %%r11 \n\t"
2459                 "mov %c[r12](%[svm]), %%r12 \n\t"
2460                 "mov %c[r13](%[svm]), %%r13 \n\t"
2461                 "mov %c[r14](%[svm]), %%r14 \n\t"
2462                 "mov %c[r15](%[svm]), %%r15 \n\t"
2463 #endif
2464
2465                 /* Enter guest mode */
2466                 "push %%"R"ax \n\t"
2467                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2468                 __ex(SVM_VMLOAD) "\n\t"
2469                 __ex(SVM_VMRUN) "\n\t"
2470                 __ex(SVM_VMSAVE) "\n\t"
2471                 "pop %%"R"ax \n\t"
2472
2473                 /* Save guest registers, load host registers */
2474                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2475                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2476                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2477                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2478                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2479                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2480 #ifdef CONFIG_X86_64
2481                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2482                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2483                 "mov %%r10, %c[r10](%[svm]) \n\t"
2484                 "mov %%r11, %c[r11](%[svm]) \n\t"
2485                 "mov %%r12, %c[r12](%[svm]) \n\t"
2486                 "mov %%r13, %c[r13](%[svm]) \n\t"
2487                 "mov %%r14, %c[r14](%[svm]) \n\t"
2488                 "mov %%r15, %c[r15](%[svm]) \n\t"
2489 #endif
2490                 "pop %%"R"bp"
2491                 :
2492                 : [svm]"a"(svm),
2493                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2494                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2495                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2496                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2497                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2498                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2499                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2500 #ifdef CONFIG_X86_64
2501                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2502                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2503                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2504                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2505                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2506                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2507                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2508                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2509 #endif
2510                 : "cc", "memory"
2511                 , R"bx", R"cx", R"dx", R"si", R"di"
2512 #ifdef CONFIG_X86_64
2513                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2514 #endif
2515                 );
2516
2517         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2518         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2519         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2520         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2521
2522         kvm_write_cr2(svm->host_cr2);
2523
2524         kvm_load_fs(fs_selector);
2525         kvm_load_gs(gs_selector);
2526         kvm_load_ldt(ldt_selector);
2527         load_host_msrs(vcpu);
2528
2529         reload_tss(vcpu);
2530
2531         local_irq_disable();
2532
2533         stgi();
2534
2535         sync_cr8_to_lapic(vcpu);
2536
2537         svm->next_rip = 0;
2538 }
2539
2540 #undef R
2541
2542 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2543 {
2544         struct vcpu_svm *svm = to_svm(vcpu);
2545
2546         if (npt_enabled) {
2547                 svm->vmcb->control.nested_cr3 = root;
2548                 force_new_asid(vcpu);
2549                 return;
2550         }
2551
2552         svm->vmcb->save.cr3 = root;
2553         force_new_asid(vcpu);
2554
2555         if (vcpu->fpu_active) {
2556                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2557                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2558                 vcpu->fpu_active = 0;
2559         }
2560 }
2561
2562 static int is_disabled(void)
2563 {
2564         u64 vm_cr;
2565
2566         rdmsrl(MSR_VM_CR, vm_cr);
2567         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2568                 return 1;
2569
2570         return 0;
2571 }
2572
2573 static void
2574 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2575 {
2576         /*
2577          * Patch in the VMMCALL instruction:
2578          */
2579         hypercall[0] = 0x0f;
2580         hypercall[1] = 0x01;
2581         hypercall[2] = 0xd9;
2582 }
2583
2584 static void svm_check_processor_compat(void *rtn)
2585 {
2586         *(int *)rtn = 0;
2587 }
2588
2589 static bool svm_cpu_has_accelerated_tpr(void)
2590 {
2591         return false;
2592 }
2593
2594 static int get_npt_level(void)
2595 {
2596 #ifdef CONFIG_X86_64
2597         return PT64_ROOT_LEVEL;
2598 #else
2599         return PT32E_ROOT_LEVEL;
2600 #endif
2601 }
2602
2603 static int svm_get_mt_mask_shift(void)
2604 {
2605         return 0;
2606 }
2607
2608 static struct kvm_x86_ops svm_x86_ops = {
2609         .cpu_has_kvm_support = has_svm,
2610         .disabled_by_bios = is_disabled,
2611         .hardware_setup = svm_hardware_setup,
2612         .hardware_unsetup = svm_hardware_unsetup,
2613         .check_processor_compatibility = svm_check_processor_compat,
2614         .hardware_enable = svm_hardware_enable,
2615         .hardware_disable = svm_hardware_disable,
2616         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2617
2618         .vcpu_create = svm_create_vcpu,
2619         .vcpu_free = svm_free_vcpu,
2620         .vcpu_reset = svm_vcpu_reset,
2621
2622         .prepare_guest_switch = svm_prepare_guest_switch,
2623         .vcpu_load = svm_vcpu_load,
2624         .vcpu_put = svm_vcpu_put,
2625
2626         .set_guest_debug = svm_guest_debug,
2627         .get_msr = svm_get_msr,
2628         .set_msr = svm_set_msr,
2629         .get_segment_base = svm_get_segment_base,
2630         .get_segment = svm_get_segment,
2631         .set_segment = svm_set_segment,
2632         .get_cpl = svm_get_cpl,
2633         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2634         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2635         .set_cr0 = svm_set_cr0,
2636         .set_cr3 = svm_set_cr3,
2637         .set_cr4 = svm_set_cr4,
2638         .set_efer = svm_set_efer,
2639         .get_idt = svm_get_idt,
2640         .set_idt = svm_set_idt,
2641         .get_gdt = svm_get_gdt,
2642         .set_gdt = svm_set_gdt,
2643         .get_dr = svm_get_dr,
2644         .set_dr = svm_set_dr,
2645         .get_rflags = svm_get_rflags,
2646         .set_rflags = svm_set_rflags,
2647
2648         .tlb_flush = svm_flush_tlb,
2649
2650         .run = svm_vcpu_run,
2651         .handle_exit = handle_exit,
2652         .skip_emulated_instruction = skip_emulated_instruction,
2653         .patch_hypercall = svm_patch_hypercall,
2654         .get_irq = svm_get_irq,
2655         .set_irq = svm_set_irq,
2656         .queue_exception = svm_queue_exception,
2657         .exception_injected = svm_exception_injected,
2658         .inject_pending_irq = svm_intr_assist,
2659         .inject_pending_vectors = do_interrupt_requests,
2660
2661         .set_tss_addr = svm_set_tss_addr,
2662         .get_tdp_level = get_npt_level,
2663         .get_mt_mask_shift = svm_get_mt_mask_shift,
2664 };
2665
2666 static int __init svm_init(void)
2667 {
2668         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2669                               THIS_MODULE);
2670 }
2671
2672 static void __exit svm_exit(void)
2673 {
2674         kvm_exit();
2675 }
2676
2677 module_init(svm_init)
2678 module_exit(svm_exit)