2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
32 #include <asm/virtext.h>
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
49 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
51 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
57 static const u32 host_save_user_msrs[] = {
59 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74 /* These are the merged vectors */
77 /* gpa pointers to the real vectors */
80 /* A VMEXIT is required but not yet emulated */
83 /* cache for intercepts of the guest */
84 u16 intercept_cr_read;
85 u16 intercept_cr_write;
86 u16 intercept_dr_read;
87 u16 intercept_dr_write;
88 u32 intercept_exceptions;
96 unsigned long vmcb_pa;
97 struct svm_cpu_data *svm_data;
98 uint64_t asid_generation;
99 uint64_t sysenter_esp;
100 uint64_t sysenter_eip;
104 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
109 struct nested_state nested;
112 /* enable NPT for AMD64 and X86 with PAE */
113 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
114 static bool npt_enabled = true;
116 static bool npt_enabled = false;
120 module_param(npt, int, S_IRUGO);
122 static int nested = 1;
123 module_param(nested, int, S_IRUGO);
125 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
126 static void svm_complete_interrupts(struct vcpu_svm *svm);
128 static int nested_svm_exit_handled(struct vcpu_svm *svm);
129 static int nested_svm_vmexit(struct vcpu_svm *svm);
130 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
131 bool has_error_code, u32 error_code);
133 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
135 return container_of(vcpu, struct vcpu_svm, vcpu);
138 static inline bool is_nested(struct vcpu_svm *svm)
140 return svm->nested.vmcb;
143 static inline void enable_gif(struct vcpu_svm *svm)
145 svm->vcpu.arch.hflags |= HF_GIF_MASK;
148 static inline void disable_gif(struct vcpu_svm *svm)
150 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
153 static inline bool gif_set(struct vcpu_svm *svm)
155 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
158 static unsigned long iopm_base;
160 struct kvm_ldttss_desc {
163 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
164 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
167 } __attribute__((packed));
169 struct svm_cpu_data {
175 struct kvm_ldttss_desc *tss_desc;
177 struct page *save_area;
180 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
181 static uint32_t svm_features;
183 struct svm_init_data {
188 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
190 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
191 #define MSRS_RANGE_SIZE 2048
192 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
194 #define MAX_INST_SIZE 15
196 static inline u32 svm_has(u32 feat)
198 return svm_features & feat;
201 static inline void clgi(void)
203 asm volatile (__ex(SVM_CLGI));
206 static inline void stgi(void)
208 asm volatile (__ex(SVM_STGI));
211 static inline void invlpga(unsigned long addr, u32 asid)
213 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
216 static inline void force_new_asid(struct kvm_vcpu *vcpu)
218 to_svm(vcpu)->asid_generation--;
221 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
223 force_new_asid(vcpu);
226 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
228 if (!npt_enabled && !(efer & EFER_LMA))
231 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
232 vcpu->arch.shadow_efer = efer;
235 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
236 bool has_error_code, u32 error_code)
238 struct vcpu_svm *svm = to_svm(vcpu);
240 /* If we are within a nested VM we'd better #VMEXIT and let the
241 guest handle the exception */
242 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
245 svm->vmcb->control.event_inj = nr
247 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
248 | SVM_EVTINJ_TYPE_EXEPT;
249 svm->vmcb->control.event_inj_err = error_code;
252 static int is_external_interrupt(u32 info)
254 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
255 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
258 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
260 struct vcpu_svm *svm = to_svm(vcpu);
263 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
264 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
268 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
270 struct vcpu_svm *svm = to_svm(vcpu);
273 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
275 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
279 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
281 struct vcpu_svm *svm = to_svm(vcpu);
283 if (!svm->next_rip) {
284 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
286 printk(KERN_DEBUG "%s: NOP\n", __func__);
289 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
290 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
291 __func__, kvm_rip_read(vcpu), svm->next_rip);
293 kvm_rip_write(vcpu, svm->next_rip);
294 svm_set_interrupt_shadow(vcpu, 0);
297 static int has_svm(void)
301 if (!cpu_has_svm(&msg)) {
302 printk(KERN_INFO "has_svm: %s\n", msg);
309 static void svm_hardware_disable(void *garbage)
314 static int svm_hardware_enable(void *garbage)
317 struct svm_cpu_data *svm_data;
319 struct descriptor_table gdt_descr;
320 struct desc_struct *gdt;
321 int me = raw_smp_processor_id();
323 rdmsrl(MSR_EFER, efer);
324 if (efer & EFER_SVME)
328 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
332 svm_data = per_cpu(svm_data, me);
335 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
340 svm_data->asid_generation = 1;
341 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
342 svm_data->next_asid = svm_data->max_asid + 1;
344 kvm_get_gdt(&gdt_descr);
345 gdt = (struct desc_struct *)gdt_descr.base;
346 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
348 wrmsrl(MSR_EFER, efer | EFER_SVME);
350 wrmsrl(MSR_VM_HSAVE_PA,
351 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
356 static void svm_cpu_uninit(int cpu)
358 struct svm_cpu_data *svm_data
359 = per_cpu(svm_data, raw_smp_processor_id());
364 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
365 __free_page(svm_data->save_area);
369 static int svm_cpu_init(int cpu)
371 struct svm_cpu_data *svm_data;
374 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
378 svm_data->save_area = alloc_page(GFP_KERNEL);
380 if (!svm_data->save_area)
383 per_cpu(svm_data, cpu) = svm_data;
393 static void set_msr_interception(u32 *msrpm, unsigned msr,
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr >= msrpm_ranges[i] &&
400 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
401 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
402 msrpm_ranges[i]) * 2;
404 u32 *base = msrpm + (msr_offset / 32);
405 u32 msr_shift = msr_offset % 32;
406 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
407 *base = (*base & ~(0x3 << msr_shift)) |
415 static void svm_vcpu_init_msrpm(u32 *msrpm)
417 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
420 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
427 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
428 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
431 static void svm_enable_lbrv(struct vcpu_svm *svm)
433 u32 *msrpm = svm->msrpm;
435 svm->vmcb->control.lbr_ctl = 1;
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
442 static void svm_disable_lbrv(struct vcpu_svm *svm)
444 u32 *msrpm = svm->msrpm;
446 svm->vmcb->control.lbr_ctl = 0;
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
453 static __init int svm_hardware_setup(void)
456 struct page *iopm_pages;
460 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
465 iopm_va = page_address(iopm_pages);
466 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
467 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
469 if (boot_cpu_has(X86_FEATURE_NX))
470 kvm_enable_efer_bits(EFER_NX);
472 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
473 kvm_enable_efer_bits(EFER_FFXSR);
476 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
477 kvm_enable_efer_bits(EFER_SVME);
480 for_each_possible_cpu(cpu) {
481 r = svm_cpu_init(cpu);
486 svm_features = cpuid_edx(SVM_CPUID_FUNC);
488 if (!svm_has(SVM_FEATURE_NPT))
491 if (npt_enabled && !npt) {
492 printk(KERN_INFO "kvm: Nested Paging disabled\n");
497 printk(KERN_INFO "kvm: Nested Paging enabled\n");
505 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
510 static __exit void svm_hardware_unsetup(void)
514 for_each_possible_cpu(cpu)
517 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
521 static void init_seg(struct vmcb_seg *seg)
524 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
525 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
530 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
533 seg->attrib = SVM_SELECTOR_P_MASK | type;
538 static void init_vmcb(struct vcpu_svm *svm)
540 struct vmcb_control_area *control = &svm->vmcb->control;
541 struct vmcb_save_area *save = &svm->vmcb->save;
543 control->intercept_cr_read = INTERCEPT_CR0_MASK |
547 control->intercept_cr_write = INTERCEPT_CR0_MASK |
552 control->intercept_dr_read = INTERCEPT_DR0_MASK |
557 control->intercept_dr_write = INTERCEPT_DR0_MASK |
564 control->intercept_exceptions = (1 << PF_VECTOR) |
569 control->intercept = (1ULL << INTERCEPT_INTR) |
570 (1ULL << INTERCEPT_NMI) |
571 (1ULL << INTERCEPT_SMI) |
572 (1ULL << INTERCEPT_CPUID) |
573 (1ULL << INTERCEPT_INVD) |
574 (1ULL << INTERCEPT_HLT) |
575 (1ULL << INTERCEPT_INVLPG) |
576 (1ULL << INTERCEPT_INVLPGA) |
577 (1ULL << INTERCEPT_IOIO_PROT) |
578 (1ULL << INTERCEPT_MSR_PROT) |
579 (1ULL << INTERCEPT_TASK_SWITCH) |
580 (1ULL << INTERCEPT_SHUTDOWN) |
581 (1ULL << INTERCEPT_VMRUN) |
582 (1ULL << INTERCEPT_VMMCALL) |
583 (1ULL << INTERCEPT_VMLOAD) |
584 (1ULL << INTERCEPT_VMSAVE) |
585 (1ULL << INTERCEPT_STGI) |
586 (1ULL << INTERCEPT_CLGI) |
587 (1ULL << INTERCEPT_SKINIT) |
588 (1ULL << INTERCEPT_WBINVD) |
589 (1ULL << INTERCEPT_MONITOR) |
590 (1ULL << INTERCEPT_MWAIT);
592 control->iopm_base_pa = iopm_base;
593 control->msrpm_base_pa = __pa(svm->msrpm);
594 control->tsc_offset = 0;
595 control->int_ctl = V_INTR_MASKING_MASK;
603 save->cs.selector = 0xf000;
604 /* Executable/Readable Code Segment */
605 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
606 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
607 save->cs.limit = 0xffff;
609 * cs.base should really be 0xffff0000, but vmx can't handle that, so
610 * be consistent with it.
612 * Replace when we have real mode working for vmx.
614 save->cs.base = 0xf0000;
616 save->gdtr.limit = 0xffff;
617 save->idtr.limit = 0xffff;
619 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
620 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
622 save->efer = EFER_SVME;
623 save->dr6 = 0xffff0ff0;
626 save->rip = 0x0000fff0;
627 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
630 * cr0 val on cpu init should be 0x60000010, we enable cpu
631 * cache by default. the orderly way is to enable cache in bios.
633 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
634 save->cr4 = X86_CR4_PAE;
638 /* Setup VMCB for Nested Paging */
639 control->nested_ctl = 1;
640 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
641 (1ULL << INTERCEPT_INVLPG));
642 control->intercept_exceptions &= ~(1 << PF_VECTOR);
643 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
645 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
647 save->g_pat = 0x0007040600070406ULL;
648 /* enable caching because the QEMU Bios doesn't enable it */
649 save->cr0 = X86_CR0_ET;
653 force_new_asid(&svm->vcpu);
655 svm->nested.vmcb = 0;
656 svm->vcpu.arch.hflags = 0;
658 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
659 control->pause_filter_count = 3000;
660 control->intercept |= (1ULL << INTERCEPT_PAUSE);
666 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
668 struct vcpu_svm *svm = to_svm(vcpu);
672 if (!kvm_vcpu_is_bsp(vcpu)) {
673 kvm_rip_write(vcpu, 0);
674 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
675 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
677 vcpu->arch.regs_avail = ~0;
678 vcpu->arch.regs_dirty = ~0;
683 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
685 struct vcpu_svm *svm;
687 struct page *msrpm_pages;
688 struct page *hsave_page;
689 struct page *nested_msrpm_pages;
692 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
698 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
702 page = alloc_page(GFP_KERNEL);
709 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
713 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
714 if (!nested_msrpm_pages)
717 svm->msrpm = page_address(msrpm_pages);
718 svm_vcpu_init_msrpm(svm->msrpm);
720 hsave_page = alloc_page(GFP_KERNEL);
723 svm->nested.hsave = page_address(hsave_page);
725 svm->nested.msrpm = page_address(nested_msrpm_pages);
727 svm->vmcb = page_address(page);
728 clear_page(svm->vmcb);
729 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
730 svm->asid_generation = 0;
734 svm->vcpu.fpu_active = 1;
735 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
736 if (kvm_vcpu_is_bsp(&svm->vcpu))
737 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
742 kvm_vcpu_uninit(&svm->vcpu);
744 kmem_cache_free(kvm_vcpu_cache, svm);
749 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
751 struct vcpu_svm *svm = to_svm(vcpu);
753 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
754 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
755 __free_page(virt_to_page(svm->nested.hsave));
756 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
757 kvm_vcpu_uninit(vcpu);
758 kmem_cache_free(kvm_vcpu_cache, svm);
761 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
763 struct vcpu_svm *svm = to_svm(vcpu);
766 if (unlikely(cpu != vcpu->cpu)) {
770 * Make sure that the guest sees a monotonically
773 delta = vcpu->arch.host_tsc - native_read_tsc();
774 svm->vmcb->control.tsc_offset += delta;
776 svm->nested.hsave->control.tsc_offset += delta;
778 kvm_migrate_timers(vcpu);
779 svm->asid_generation = 0;
782 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
783 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
786 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
788 struct vcpu_svm *svm = to_svm(vcpu);
791 ++vcpu->stat.host_state_reload;
792 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
793 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
795 vcpu->arch.host_tsc = native_read_tsc();
798 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
800 return to_svm(vcpu)->vmcb->save.rflags;
803 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
805 to_svm(vcpu)->vmcb->save.rflags = rflags;
808 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
811 case VCPU_EXREG_PDPTR:
812 BUG_ON(!npt_enabled);
813 load_pdptrs(vcpu, vcpu->arch.cr3);
820 static void svm_set_vintr(struct vcpu_svm *svm)
822 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
825 static void svm_clear_vintr(struct vcpu_svm *svm)
827 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
830 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
832 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
835 case VCPU_SREG_CS: return &save->cs;
836 case VCPU_SREG_DS: return &save->ds;
837 case VCPU_SREG_ES: return &save->es;
838 case VCPU_SREG_FS: return &save->fs;
839 case VCPU_SREG_GS: return &save->gs;
840 case VCPU_SREG_SS: return &save->ss;
841 case VCPU_SREG_TR: return &save->tr;
842 case VCPU_SREG_LDTR: return &save->ldtr;
848 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
850 struct vmcb_seg *s = svm_seg(vcpu, seg);
855 static void svm_get_segment(struct kvm_vcpu *vcpu,
856 struct kvm_segment *var, int seg)
858 struct vmcb_seg *s = svm_seg(vcpu, seg);
861 var->limit = s->limit;
862 var->selector = s->selector;
863 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
864 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
865 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
866 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
867 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
868 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
869 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
870 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
872 /* AMD's VMCB does not have an explicit unusable field, so emulate it
873 * for cross vendor migration purposes by "not present"
875 var->unusable = !var->present || (var->type == 0);
880 * SVM always stores 0 for the 'G' bit in the CS selector in
881 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
882 * Intel's VMENTRY has a check on the 'G' bit.
884 var->g = s->limit > 0xfffff;
888 * Work around a bug where the busy flag in the tr selector
898 * The accessed bit must always be set in the segment
899 * descriptor cache, although it can be cleared in the
900 * descriptor, the cached bit always remains at 1. Since
901 * Intel has a check on this, set it here to support
902 * cross-vendor migration.
908 /* On AMD CPUs sometimes the DB bit in the segment
909 * descriptor is left as 1, although the whole segment has
910 * been made unusable. Clear it here to pass an Intel VMX
911 * entry check when cross vendor migrating.
919 static int svm_get_cpl(struct kvm_vcpu *vcpu)
921 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
926 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
928 struct vcpu_svm *svm = to_svm(vcpu);
930 dt->limit = svm->vmcb->save.idtr.limit;
931 dt->base = svm->vmcb->save.idtr.base;
934 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
936 struct vcpu_svm *svm = to_svm(vcpu);
938 svm->vmcb->save.idtr.limit = dt->limit;
939 svm->vmcb->save.idtr.base = dt->base ;
942 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
944 struct vcpu_svm *svm = to_svm(vcpu);
946 dt->limit = svm->vmcb->save.gdtr.limit;
947 dt->base = svm->vmcb->save.gdtr.base;
950 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
952 struct vcpu_svm *svm = to_svm(vcpu);
954 svm->vmcb->save.gdtr.limit = dt->limit;
955 svm->vmcb->save.gdtr.base = dt->base ;
958 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
962 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
964 struct vcpu_svm *svm = to_svm(vcpu);
967 if (vcpu->arch.shadow_efer & EFER_LME) {
968 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
969 vcpu->arch.shadow_efer |= EFER_LMA;
970 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
973 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
974 vcpu->arch.shadow_efer &= ~EFER_LMA;
975 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
982 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
983 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
984 vcpu->fpu_active = 1;
987 vcpu->arch.cr0 = cr0;
988 cr0 |= X86_CR0_PG | X86_CR0_WP;
989 if (!vcpu->fpu_active) {
990 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
995 * re-enable caching here because the QEMU bios
996 * does not do it - this results in some delay at
999 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1000 svm->vmcb->save.cr0 = cr0;
1003 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1005 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1006 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1008 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1009 force_new_asid(vcpu);
1011 vcpu->arch.cr4 = cr4;
1014 cr4 |= host_cr4_mce;
1015 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1018 static void svm_set_segment(struct kvm_vcpu *vcpu,
1019 struct kvm_segment *var, int seg)
1021 struct vcpu_svm *svm = to_svm(vcpu);
1022 struct vmcb_seg *s = svm_seg(vcpu, seg);
1024 s->base = var->base;
1025 s->limit = var->limit;
1026 s->selector = var->selector;
1030 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1031 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1032 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1033 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1034 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1035 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1036 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1037 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1039 if (seg == VCPU_SREG_CS)
1041 = (svm->vmcb->save.cs.attrib
1042 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1046 static void update_db_intercept(struct kvm_vcpu *vcpu)
1048 struct vcpu_svm *svm = to_svm(vcpu);
1050 svm->vmcb->control.intercept_exceptions &=
1051 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1053 if (vcpu->arch.singlestep)
1054 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1056 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1057 if (vcpu->guest_debug &
1058 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1059 svm->vmcb->control.intercept_exceptions |=
1061 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1062 svm->vmcb->control.intercept_exceptions |=
1065 vcpu->guest_debug = 0;
1068 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1070 struct vcpu_svm *svm = to_svm(vcpu);
1072 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1073 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1075 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1077 update_db_intercept(vcpu);
1080 static void load_host_msrs(struct kvm_vcpu *vcpu)
1082 #ifdef CONFIG_X86_64
1083 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1087 static void save_host_msrs(struct kvm_vcpu *vcpu)
1089 #ifdef CONFIG_X86_64
1090 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1094 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1096 if (svm_data->next_asid > svm_data->max_asid) {
1097 ++svm_data->asid_generation;
1098 svm_data->next_asid = 1;
1099 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1102 svm->asid_generation = svm_data->asid_generation;
1103 svm->vmcb->control.asid = svm_data->next_asid++;
1106 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1108 struct vcpu_svm *svm = to_svm(vcpu);
1113 val = vcpu->arch.db[dr];
1116 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1117 val = vcpu->arch.dr6;
1119 val = svm->vmcb->save.dr6;
1122 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1123 val = vcpu->arch.dr7;
1125 val = svm->vmcb->save.dr7;
1134 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1137 struct vcpu_svm *svm = to_svm(vcpu);
1143 vcpu->arch.db[dr] = value;
1144 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1145 vcpu->arch.eff_db[dr] = value;
1148 if (vcpu->arch.cr4 & X86_CR4_DE)
1149 *exception = UD_VECTOR;
1152 if (value & 0xffffffff00000000ULL) {
1153 *exception = GP_VECTOR;
1156 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1159 if (value & 0xffffffff00000000ULL) {
1160 *exception = GP_VECTOR;
1163 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1164 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1165 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1166 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1170 /* FIXME: Possible case? */
1171 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1173 *exception = UD_VECTOR;
1178 static int pf_interception(struct vcpu_svm *svm)
1183 fault_address = svm->vmcb->control.exit_info_2;
1184 error_code = svm->vmcb->control.exit_info_1;
1186 trace_kvm_page_fault(fault_address, error_code);
1187 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1188 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1189 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1192 static int db_interception(struct vcpu_svm *svm)
1194 struct kvm_run *kvm_run = svm->vcpu.run;
1196 if (!(svm->vcpu.guest_debug &
1197 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1198 !svm->vcpu.arch.singlestep) {
1199 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1203 if (svm->vcpu.arch.singlestep) {
1204 svm->vcpu.arch.singlestep = false;
1205 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1206 svm->vmcb->save.rflags &=
1207 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1208 update_db_intercept(&svm->vcpu);
1211 if (svm->vcpu.guest_debug &
1212 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1213 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1214 kvm_run->debug.arch.pc =
1215 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1216 kvm_run->debug.arch.exception = DB_VECTOR;
1223 static int bp_interception(struct vcpu_svm *svm)
1225 struct kvm_run *kvm_run = svm->vcpu.run;
1227 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1228 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1229 kvm_run->debug.arch.exception = BP_VECTOR;
1233 static int ud_interception(struct vcpu_svm *svm)
1237 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1238 if (er != EMULATE_DONE)
1239 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1243 static int nm_interception(struct vcpu_svm *svm)
1245 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1246 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1247 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1248 svm->vcpu.fpu_active = 1;
1253 static int mc_interception(struct vcpu_svm *svm)
1256 * On an #MC intercept the MCE handler is not called automatically in
1257 * the host. So do it by hand here.
1261 /* not sure if we ever come back to this point */
1266 static int shutdown_interception(struct vcpu_svm *svm)
1268 struct kvm_run *kvm_run = svm->vcpu.run;
1271 * VMCB is undefined after a SHUTDOWN intercept
1272 * so reinitialize it.
1274 clear_page(svm->vmcb);
1277 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1281 static int io_interception(struct vcpu_svm *svm)
1283 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1284 int size, in, string;
1287 ++svm->vcpu.stat.io_exits;
1289 svm->next_rip = svm->vmcb->control.exit_info_2;
1291 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1294 if (emulate_instruction(&svm->vcpu,
1295 0, 0, 0) == EMULATE_DO_MMIO)
1300 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1301 port = io_info >> 16;
1302 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1304 skip_emulated_instruction(&svm->vcpu);
1305 return kvm_emulate_pio(&svm->vcpu, in, size, port);
1308 static int nmi_interception(struct vcpu_svm *svm)
1313 static int intr_interception(struct vcpu_svm *svm)
1315 ++svm->vcpu.stat.irq_exits;
1319 static int nop_on_interception(struct vcpu_svm *svm)
1324 static int halt_interception(struct vcpu_svm *svm)
1326 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1327 skip_emulated_instruction(&svm->vcpu);
1328 return kvm_emulate_halt(&svm->vcpu);
1331 static int vmmcall_interception(struct vcpu_svm *svm)
1333 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1334 skip_emulated_instruction(&svm->vcpu);
1335 kvm_emulate_hypercall(&svm->vcpu);
1339 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1341 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1342 || !is_paging(&svm->vcpu)) {
1343 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1347 if (svm->vmcb->save.cpl) {
1348 kvm_inject_gp(&svm->vcpu, 0);
1355 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1356 bool has_error_code, u32 error_code)
1358 if (!is_nested(svm))
1361 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1362 svm->vmcb->control.exit_code_hi = 0;
1363 svm->vmcb->control.exit_info_1 = error_code;
1364 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1366 return nested_svm_exit_handled(svm);
1369 static inline int nested_svm_intr(struct vcpu_svm *svm)
1371 if (!is_nested(svm))
1374 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1377 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1380 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1382 if (svm->nested.intercept & 1ULL) {
1384 * The #vmexit can't be emulated here directly because this
1385 * code path runs with irqs and preemtion disabled. A
1386 * #vmexit emulation might sleep. Only signal request for
1389 svm->nested.exit_required = true;
1390 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1397 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1401 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1402 if (is_error_page(page))
1405 return kmap_atomic(page, idx);
1408 kvm_release_page_clean(page);
1409 kvm_inject_gp(&svm->vcpu, 0);
1414 static void nested_svm_unmap(void *addr, enum km_type idx)
1421 page = kmap_atomic_to_page(addr);
1423 kunmap_atomic(addr, idx);
1424 kvm_release_page_dirty(page);
1427 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1429 u32 param = svm->vmcb->control.exit_info_1 & 1;
1430 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1435 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1438 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1448 case 0xc0000000 ... 0xc0001fff:
1449 t0 = (8192 + msr - 0xc0000000) * 2;
1453 case 0xc0010000 ... 0xc0011fff:
1454 t0 = (16384 + msr - 0xc0010000) * 2;
1463 ret = msrpm[t1] & ((1 << param) << t0);
1466 nested_svm_unmap(msrpm, KM_USER0);
1471 static int nested_svm_exit_special(struct vcpu_svm *svm)
1473 u32 exit_code = svm->vmcb->control.exit_code;
1475 switch (exit_code) {
1478 return NESTED_EXIT_HOST;
1479 /* For now we are always handling NPFs when using them */
1482 return NESTED_EXIT_HOST;
1484 /* When we're shadowing, trap PFs */
1485 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1487 return NESTED_EXIT_HOST;
1493 return NESTED_EXIT_CONTINUE;
1497 * If this function returns true, this #vmexit was already handled
1499 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1501 u32 exit_code = svm->vmcb->control.exit_code;
1502 int vmexit = NESTED_EXIT_HOST;
1504 switch (exit_code) {
1506 vmexit = nested_svm_exit_handled_msr(svm);
1508 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1509 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1510 if (svm->nested.intercept_cr_read & cr_bits)
1511 vmexit = NESTED_EXIT_DONE;
1514 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1515 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1516 if (svm->nested.intercept_cr_write & cr_bits)
1517 vmexit = NESTED_EXIT_DONE;
1520 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1521 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1522 if (svm->nested.intercept_dr_read & dr_bits)
1523 vmexit = NESTED_EXIT_DONE;
1526 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1527 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1528 if (svm->nested.intercept_dr_write & dr_bits)
1529 vmexit = NESTED_EXIT_DONE;
1532 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1533 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1534 if (svm->nested.intercept_exceptions & excp_bits)
1535 vmexit = NESTED_EXIT_DONE;
1539 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1540 if (svm->nested.intercept & exit_bits)
1541 vmexit = NESTED_EXIT_DONE;
1545 if (vmexit == NESTED_EXIT_DONE) {
1546 nested_svm_vmexit(svm);
1552 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1554 struct vmcb_control_area *dst = &dst_vmcb->control;
1555 struct vmcb_control_area *from = &from_vmcb->control;
1557 dst->intercept_cr_read = from->intercept_cr_read;
1558 dst->intercept_cr_write = from->intercept_cr_write;
1559 dst->intercept_dr_read = from->intercept_dr_read;
1560 dst->intercept_dr_write = from->intercept_dr_write;
1561 dst->intercept_exceptions = from->intercept_exceptions;
1562 dst->intercept = from->intercept;
1563 dst->iopm_base_pa = from->iopm_base_pa;
1564 dst->msrpm_base_pa = from->msrpm_base_pa;
1565 dst->tsc_offset = from->tsc_offset;
1566 dst->asid = from->asid;
1567 dst->tlb_ctl = from->tlb_ctl;
1568 dst->int_ctl = from->int_ctl;
1569 dst->int_vector = from->int_vector;
1570 dst->int_state = from->int_state;
1571 dst->exit_code = from->exit_code;
1572 dst->exit_code_hi = from->exit_code_hi;
1573 dst->exit_info_1 = from->exit_info_1;
1574 dst->exit_info_2 = from->exit_info_2;
1575 dst->exit_int_info = from->exit_int_info;
1576 dst->exit_int_info_err = from->exit_int_info_err;
1577 dst->nested_ctl = from->nested_ctl;
1578 dst->event_inj = from->event_inj;
1579 dst->event_inj_err = from->event_inj_err;
1580 dst->nested_cr3 = from->nested_cr3;
1581 dst->lbr_ctl = from->lbr_ctl;
1584 static int nested_svm_vmexit(struct vcpu_svm *svm)
1586 struct vmcb *nested_vmcb;
1587 struct vmcb *hsave = svm->nested.hsave;
1588 struct vmcb *vmcb = svm->vmcb;
1590 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1591 vmcb->control.exit_info_1,
1592 vmcb->control.exit_info_2,
1593 vmcb->control.exit_int_info,
1594 vmcb->control.exit_int_info_err);
1596 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1600 /* Give the current vmcb to the guest */
1603 nested_vmcb->save.es = vmcb->save.es;
1604 nested_vmcb->save.cs = vmcb->save.cs;
1605 nested_vmcb->save.ss = vmcb->save.ss;
1606 nested_vmcb->save.ds = vmcb->save.ds;
1607 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1608 nested_vmcb->save.idtr = vmcb->save.idtr;
1610 nested_vmcb->save.cr3 = vmcb->save.cr3;
1611 nested_vmcb->save.cr2 = vmcb->save.cr2;
1612 nested_vmcb->save.rflags = vmcb->save.rflags;
1613 nested_vmcb->save.rip = vmcb->save.rip;
1614 nested_vmcb->save.rsp = vmcb->save.rsp;
1615 nested_vmcb->save.rax = vmcb->save.rax;
1616 nested_vmcb->save.dr7 = vmcb->save.dr7;
1617 nested_vmcb->save.dr6 = vmcb->save.dr6;
1618 nested_vmcb->save.cpl = vmcb->save.cpl;
1620 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1621 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1622 nested_vmcb->control.int_state = vmcb->control.int_state;
1623 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1624 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1625 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1626 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1627 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1628 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1631 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1632 * to make sure that we do not lose injected events. So check event_inj
1633 * here and copy it to exit_int_info if it is valid.
1634 * Exit_int_info and event_inj can't be both valid because the case
1635 * below only happens on a VMRUN instruction intercept which has
1636 * no valid exit_int_info set.
1638 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1639 struct vmcb_control_area *nc = &nested_vmcb->control;
1641 nc->exit_int_info = vmcb->control.event_inj;
1642 nc->exit_int_info_err = vmcb->control.event_inj_err;
1645 nested_vmcb->control.tlb_ctl = 0;
1646 nested_vmcb->control.event_inj = 0;
1647 nested_vmcb->control.event_inj_err = 0;
1649 /* We always set V_INTR_MASKING and remember the old value in hflags */
1650 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1651 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1653 /* Restore the original control entries */
1654 copy_vmcb_control_area(vmcb, hsave);
1656 kvm_clear_exception_queue(&svm->vcpu);
1657 kvm_clear_interrupt_queue(&svm->vcpu);
1659 /* Restore selected save entries */
1660 svm->vmcb->save.es = hsave->save.es;
1661 svm->vmcb->save.cs = hsave->save.cs;
1662 svm->vmcb->save.ss = hsave->save.ss;
1663 svm->vmcb->save.ds = hsave->save.ds;
1664 svm->vmcb->save.gdtr = hsave->save.gdtr;
1665 svm->vmcb->save.idtr = hsave->save.idtr;
1666 svm->vmcb->save.rflags = hsave->save.rflags;
1667 svm_set_efer(&svm->vcpu, hsave->save.efer);
1668 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1669 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1671 svm->vmcb->save.cr3 = hsave->save.cr3;
1672 svm->vcpu.arch.cr3 = hsave->save.cr3;
1674 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1676 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1677 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1678 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1679 svm->vmcb->save.dr7 = 0;
1680 svm->vmcb->save.cpl = 0;
1681 svm->vmcb->control.exit_int_info = 0;
1683 /* Exit nested SVM mode */
1684 svm->nested.vmcb = 0;
1686 nested_svm_unmap(nested_vmcb, KM_USER0);
1688 kvm_mmu_reset_context(&svm->vcpu);
1689 kvm_mmu_load(&svm->vcpu);
1694 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1699 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1703 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1704 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1706 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1708 nested_svm_unmap(nested_msrpm, KM_USER0);
1713 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1715 struct vmcb *nested_vmcb;
1716 struct vmcb *hsave = svm->nested.hsave;
1717 struct vmcb *vmcb = svm->vmcb;
1719 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1723 /* nested_vmcb is our indicator if nested SVM is activated */
1724 svm->nested.vmcb = svm->vmcb->save.rax;
1726 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1727 nested_vmcb->save.rip,
1728 nested_vmcb->control.int_ctl,
1729 nested_vmcb->control.event_inj,
1730 nested_vmcb->control.nested_ctl);
1732 /* Clear internal status */
1733 kvm_clear_exception_queue(&svm->vcpu);
1734 kvm_clear_interrupt_queue(&svm->vcpu);
1736 /* Save the old vmcb, so we don't need to pick what we save, but
1737 can restore everything when a VMEXIT occurs */
1738 hsave->save.es = vmcb->save.es;
1739 hsave->save.cs = vmcb->save.cs;
1740 hsave->save.ss = vmcb->save.ss;
1741 hsave->save.ds = vmcb->save.ds;
1742 hsave->save.gdtr = vmcb->save.gdtr;
1743 hsave->save.idtr = vmcb->save.idtr;
1744 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1745 hsave->save.cr0 = svm->vcpu.arch.cr0;
1746 hsave->save.cr4 = svm->vcpu.arch.cr4;
1747 hsave->save.rflags = vmcb->save.rflags;
1748 hsave->save.rip = svm->next_rip;
1749 hsave->save.rsp = vmcb->save.rsp;
1750 hsave->save.rax = vmcb->save.rax;
1752 hsave->save.cr3 = vmcb->save.cr3;
1754 hsave->save.cr3 = svm->vcpu.arch.cr3;
1756 copy_vmcb_control_area(hsave, vmcb);
1758 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1759 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1761 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1763 /* Load the nested guest state */
1764 svm->vmcb->save.es = nested_vmcb->save.es;
1765 svm->vmcb->save.cs = nested_vmcb->save.cs;
1766 svm->vmcb->save.ss = nested_vmcb->save.ss;
1767 svm->vmcb->save.ds = nested_vmcb->save.ds;
1768 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1769 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1770 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1771 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1772 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1773 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1775 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1776 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1778 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1779 kvm_mmu_reset_context(&svm->vcpu);
1781 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1782 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1783 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1784 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1785 /* In case we don't even reach vcpu_run, the fields are not updated */
1786 svm->vmcb->save.rax = nested_vmcb->save.rax;
1787 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1788 svm->vmcb->save.rip = nested_vmcb->save.rip;
1789 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1790 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1791 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1793 /* We don't want a nested guest to be more powerful than the guest,
1794 so all intercepts are ORed */
1795 svm->vmcb->control.intercept_cr_read |=
1796 nested_vmcb->control.intercept_cr_read;
1797 svm->vmcb->control.intercept_cr_write |=
1798 nested_vmcb->control.intercept_cr_write;
1799 svm->vmcb->control.intercept_dr_read |=
1800 nested_vmcb->control.intercept_dr_read;
1801 svm->vmcb->control.intercept_dr_write |=
1802 nested_vmcb->control.intercept_dr_write;
1803 svm->vmcb->control.intercept_exceptions |=
1804 nested_vmcb->control.intercept_exceptions;
1806 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1808 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1810 /* cache intercepts */
1811 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1812 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1813 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1814 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1815 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1816 svm->nested.intercept = nested_vmcb->control.intercept;
1818 force_new_asid(&svm->vcpu);
1819 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1820 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1821 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1823 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1825 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1826 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1827 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1828 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1829 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1831 nested_svm_unmap(nested_vmcb, KM_USER0);
1838 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1840 to_vmcb->save.fs = from_vmcb->save.fs;
1841 to_vmcb->save.gs = from_vmcb->save.gs;
1842 to_vmcb->save.tr = from_vmcb->save.tr;
1843 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1844 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1845 to_vmcb->save.star = from_vmcb->save.star;
1846 to_vmcb->save.lstar = from_vmcb->save.lstar;
1847 to_vmcb->save.cstar = from_vmcb->save.cstar;
1848 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1849 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1850 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1851 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1854 static int vmload_interception(struct vcpu_svm *svm)
1856 struct vmcb *nested_vmcb;
1858 if (nested_svm_check_permissions(svm))
1861 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1862 skip_emulated_instruction(&svm->vcpu);
1864 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1868 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1869 nested_svm_unmap(nested_vmcb, KM_USER0);
1874 static int vmsave_interception(struct vcpu_svm *svm)
1876 struct vmcb *nested_vmcb;
1878 if (nested_svm_check_permissions(svm))
1881 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1882 skip_emulated_instruction(&svm->vcpu);
1884 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1888 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1889 nested_svm_unmap(nested_vmcb, KM_USER0);
1894 static int vmrun_interception(struct vcpu_svm *svm)
1896 if (nested_svm_check_permissions(svm))
1899 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1900 skip_emulated_instruction(&svm->vcpu);
1902 if (!nested_svm_vmrun(svm))
1905 if (!nested_svm_vmrun_msrpm(svm))
1912 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1913 svm->vmcb->control.exit_code_hi = 0;
1914 svm->vmcb->control.exit_info_1 = 0;
1915 svm->vmcb->control.exit_info_2 = 0;
1917 nested_svm_vmexit(svm);
1922 static int stgi_interception(struct vcpu_svm *svm)
1924 if (nested_svm_check_permissions(svm))
1927 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1928 skip_emulated_instruction(&svm->vcpu);
1935 static int clgi_interception(struct vcpu_svm *svm)
1937 if (nested_svm_check_permissions(svm))
1940 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1941 skip_emulated_instruction(&svm->vcpu);
1945 /* After a CLGI no interrupts should come */
1946 svm_clear_vintr(svm);
1947 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1952 static int invlpga_interception(struct vcpu_svm *svm)
1954 struct kvm_vcpu *vcpu = &svm->vcpu;
1956 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1957 vcpu->arch.regs[VCPU_REGS_RAX]);
1959 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1960 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1962 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1963 skip_emulated_instruction(&svm->vcpu);
1967 static int skinit_interception(struct vcpu_svm *svm)
1969 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1971 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1975 static int invalid_op_interception(struct vcpu_svm *svm)
1977 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1981 static int task_switch_interception(struct vcpu_svm *svm)
1985 int int_type = svm->vmcb->control.exit_int_info &
1986 SVM_EXITINTINFO_TYPE_MASK;
1987 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1989 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1991 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1993 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1995 if (svm->vmcb->control.exit_info_2 &
1996 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1997 reason = TASK_SWITCH_IRET;
1998 else if (svm->vmcb->control.exit_info_2 &
1999 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2000 reason = TASK_SWITCH_JMP;
2002 reason = TASK_SWITCH_GATE;
2004 reason = TASK_SWITCH_CALL;
2006 if (reason == TASK_SWITCH_GATE) {
2008 case SVM_EXITINTINFO_TYPE_NMI:
2009 svm->vcpu.arch.nmi_injected = false;
2011 case SVM_EXITINTINFO_TYPE_EXEPT:
2012 kvm_clear_exception_queue(&svm->vcpu);
2014 case SVM_EXITINTINFO_TYPE_INTR:
2015 kvm_clear_interrupt_queue(&svm->vcpu);
2022 if (reason != TASK_SWITCH_GATE ||
2023 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2024 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2025 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2026 skip_emulated_instruction(&svm->vcpu);
2028 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2031 static int cpuid_interception(struct vcpu_svm *svm)
2033 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2034 kvm_emulate_cpuid(&svm->vcpu);
2038 static int iret_interception(struct vcpu_svm *svm)
2040 ++svm->vcpu.stat.nmi_window_exits;
2041 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2042 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2046 static int invlpg_interception(struct vcpu_svm *svm)
2048 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2049 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2053 static int emulate_on_interception(struct vcpu_svm *svm)
2055 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2056 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2060 static int cr8_write_interception(struct vcpu_svm *svm)
2062 struct kvm_run *kvm_run = svm->vcpu.run;
2064 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2065 /* instruction emulation calls kvm_set_cr8() */
2066 emulate_instruction(&svm->vcpu, 0, 0, 0);
2067 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2068 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2071 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2073 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2077 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2079 struct vcpu_svm *svm = to_svm(vcpu);
2082 case MSR_IA32_TSC: {
2086 tsc_offset = svm->nested.hsave->control.tsc_offset;
2088 tsc_offset = svm->vmcb->control.tsc_offset;
2090 *data = tsc_offset + native_read_tsc();
2094 *data = svm->vmcb->save.star;
2096 #ifdef CONFIG_X86_64
2098 *data = svm->vmcb->save.lstar;
2101 *data = svm->vmcb->save.cstar;
2103 case MSR_KERNEL_GS_BASE:
2104 *data = svm->vmcb->save.kernel_gs_base;
2106 case MSR_SYSCALL_MASK:
2107 *data = svm->vmcb->save.sfmask;
2110 case MSR_IA32_SYSENTER_CS:
2111 *data = svm->vmcb->save.sysenter_cs;
2113 case MSR_IA32_SYSENTER_EIP:
2114 *data = svm->sysenter_eip;
2116 case MSR_IA32_SYSENTER_ESP:
2117 *data = svm->sysenter_esp;
2119 /* Nobody will change the following 5 values in the VMCB so
2120 we can safely return them on rdmsr. They will always be 0
2121 until LBRV is implemented. */
2122 case MSR_IA32_DEBUGCTLMSR:
2123 *data = svm->vmcb->save.dbgctl;
2125 case MSR_IA32_LASTBRANCHFROMIP:
2126 *data = svm->vmcb->save.br_from;
2128 case MSR_IA32_LASTBRANCHTOIP:
2129 *data = svm->vmcb->save.br_to;
2131 case MSR_IA32_LASTINTFROMIP:
2132 *data = svm->vmcb->save.last_excp_from;
2134 case MSR_IA32_LASTINTTOIP:
2135 *data = svm->vmcb->save.last_excp_to;
2137 case MSR_VM_HSAVE_PA:
2138 *data = svm->nested.hsave_msr;
2143 case MSR_IA32_UCODE_REV:
2147 return kvm_get_msr_common(vcpu, ecx, data);
2152 static int rdmsr_interception(struct vcpu_svm *svm)
2154 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2157 if (svm_get_msr(&svm->vcpu, ecx, &data))
2158 kvm_inject_gp(&svm->vcpu, 0);
2160 trace_kvm_msr_read(ecx, data);
2162 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2163 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2164 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2165 skip_emulated_instruction(&svm->vcpu);
2170 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2172 struct vcpu_svm *svm = to_svm(vcpu);
2175 case MSR_IA32_TSC: {
2176 u64 tsc_offset = data - native_read_tsc();
2177 u64 g_tsc_offset = 0;
2179 if (is_nested(svm)) {
2180 g_tsc_offset = svm->vmcb->control.tsc_offset -
2181 svm->nested.hsave->control.tsc_offset;
2182 svm->nested.hsave->control.tsc_offset = tsc_offset;
2185 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2190 svm->vmcb->save.star = data;
2192 #ifdef CONFIG_X86_64
2194 svm->vmcb->save.lstar = data;
2197 svm->vmcb->save.cstar = data;
2199 case MSR_KERNEL_GS_BASE:
2200 svm->vmcb->save.kernel_gs_base = data;
2202 case MSR_SYSCALL_MASK:
2203 svm->vmcb->save.sfmask = data;
2206 case MSR_IA32_SYSENTER_CS:
2207 svm->vmcb->save.sysenter_cs = data;
2209 case MSR_IA32_SYSENTER_EIP:
2210 svm->sysenter_eip = data;
2211 svm->vmcb->save.sysenter_eip = data;
2213 case MSR_IA32_SYSENTER_ESP:
2214 svm->sysenter_esp = data;
2215 svm->vmcb->save.sysenter_esp = data;
2217 case MSR_IA32_DEBUGCTLMSR:
2218 if (!svm_has(SVM_FEATURE_LBRV)) {
2219 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2223 if (data & DEBUGCTL_RESERVED_BITS)
2226 svm->vmcb->save.dbgctl = data;
2227 if (data & (1ULL<<0))
2228 svm_enable_lbrv(svm);
2230 svm_disable_lbrv(svm);
2232 case MSR_VM_HSAVE_PA:
2233 svm->nested.hsave_msr = data;
2237 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2240 return kvm_set_msr_common(vcpu, ecx, data);
2245 static int wrmsr_interception(struct vcpu_svm *svm)
2247 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2248 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2249 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2251 trace_kvm_msr_write(ecx, data);
2253 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2254 if (svm_set_msr(&svm->vcpu, ecx, data))
2255 kvm_inject_gp(&svm->vcpu, 0);
2257 skip_emulated_instruction(&svm->vcpu);
2261 static int msr_interception(struct vcpu_svm *svm)
2263 if (svm->vmcb->control.exit_info_1)
2264 return wrmsr_interception(svm);
2266 return rdmsr_interception(svm);
2269 static int interrupt_window_interception(struct vcpu_svm *svm)
2271 struct kvm_run *kvm_run = svm->vcpu.run;
2273 svm_clear_vintr(svm);
2274 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2276 * If the user space waits to inject interrupts, exit as soon as
2279 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2280 kvm_run->request_interrupt_window &&
2281 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2282 ++svm->vcpu.stat.irq_window_exits;
2283 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2290 static int pause_interception(struct vcpu_svm *svm)
2292 kvm_vcpu_on_spin(&(svm->vcpu));
2296 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2297 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2298 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2299 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2300 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2302 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2303 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2304 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2305 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2306 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2307 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2308 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2309 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2310 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2311 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2312 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2313 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2314 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2315 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2316 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2317 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2318 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2319 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2320 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2321 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2322 [SVM_EXIT_INTR] = intr_interception,
2323 [SVM_EXIT_NMI] = nmi_interception,
2324 [SVM_EXIT_SMI] = nop_on_interception,
2325 [SVM_EXIT_INIT] = nop_on_interception,
2326 [SVM_EXIT_VINTR] = interrupt_window_interception,
2327 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2328 [SVM_EXIT_CPUID] = cpuid_interception,
2329 [SVM_EXIT_IRET] = iret_interception,
2330 [SVM_EXIT_INVD] = emulate_on_interception,
2331 [SVM_EXIT_PAUSE] = pause_interception,
2332 [SVM_EXIT_HLT] = halt_interception,
2333 [SVM_EXIT_INVLPG] = invlpg_interception,
2334 [SVM_EXIT_INVLPGA] = invlpga_interception,
2335 [SVM_EXIT_IOIO] = io_interception,
2336 [SVM_EXIT_MSR] = msr_interception,
2337 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2338 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2339 [SVM_EXIT_VMRUN] = vmrun_interception,
2340 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2341 [SVM_EXIT_VMLOAD] = vmload_interception,
2342 [SVM_EXIT_VMSAVE] = vmsave_interception,
2343 [SVM_EXIT_STGI] = stgi_interception,
2344 [SVM_EXIT_CLGI] = clgi_interception,
2345 [SVM_EXIT_SKINIT] = skinit_interception,
2346 [SVM_EXIT_WBINVD] = emulate_on_interception,
2347 [SVM_EXIT_MONITOR] = invalid_op_interception,
2348 [SVM_EXIT_MWAIT] = invalid_op_interception,
2349 [SVM_EXIT_NPF] = pf_interception,
2352 static int handle_exit(struct kvm_vcpu *vcpu)
2354 struct vcpu_svm *svm = to_svm(vcpu);
2355 struct kvm_run *kvm_run = vcpu->run;
2356 u32 exit_code = svm->vmcb->control.exit_code;
2358 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2360 if (unlikely(svm->nested.exit_required)) {
2361 nested_svm_vmexit(svm);
2362 svm->nested.exit_required = false;
2367 if (is_nested(svm)) {
2370 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2371 svm->vmcb->control.exit_info_1,
2372 svm->vmcb->control.exit_info_2,
2373 svm->vmcb->control.exit_int_info,
2374 svm->vmcb->control.exit_int_info_err);
2376 vmexit = nested_svm_exit_special(svm);
2378 if (vmexit == NESTED_EXIT_CONTINUE)
2379 vmexit = nested_svm_exit_handled(svm);
2381 if (vmexit == NESTED_EXIT_DONE)
2385 svm_complete_interrupts(svm);
2389 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2390 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2393 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2394 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2396 kvm_mmu_reset_context(vcpu);
2402 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2403 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2404 kvm_run->fail_entry.hardware_entry_failure_reason
2405 = svm->vmcb->control.exit_code;
2409 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2410 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2411 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2412 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2414 __func__, svm->vmcb->control.exit_int_info,
2417 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2418 || !svm_exit_handlers[exit_code]) {
2419 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2420 kvm_run->hw.hardware_exit_reason = exit_code;
2424 return svm_exit_handlers[exit_code](svm);
2427 static void reload_tss(struct kvm_vcpu *vcpu)
2429 int cpu = raw_smp_processor_id();
2431 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2432 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2436 static void pre_svm_run(struct vcpu_svm *svm)
2438 int cpu = raw_smp_processor_id();
2440 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2442 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2443 /* FIXME: handle wraparound of asid_generation */
2444 if (svm->asid_generation != svm_data->asid_generation)
2445 new_asid(svm, svm_data);
2448 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2450 struct vcpu_svm *svm = to_svm(vcpu);
2452 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2453 vcpu->arch.hflags |= HF_NMI_MASK;
2454 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2455 ++vcpu->stat.nmi_injections;
2458 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2460 struct vmcb_control_area *control;
2462 trace_kvm_inj_virq(irq);
2464 ++svm->vcpu.stat.irq_injections;
2465 control = &svm->vmcb->control;
2466 control->int_vector = irq;
2467 control->int_ctl &= ~V_INTR_PRIO_MASK;
2468 control->int_ctl |= V_IRQ_MASK |
2469 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2472 static void svm_set_irq(struct kvm_vcpu *vcpu)
2474 struct vcpu_svm *svm = to_svm(vcpu);
2476 BUG_ON(!(gif_set(svm)));
2478 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2479 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2482 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2484 struct vcpu_svm *svm = to_svm(vcpu);
2490 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2493 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2495 struct vcpu_svm *svm = to_svm(vcpu);
2496 struct vmcb *vmcb = svm->vmcb;
2497 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2498 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2501 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2503 struct vcpu_svm *svm = to_svm(vcpu);
2504 struct vmcb *vmcb = svm->vmcb;
2507 if (!gif_set(svm) ||
2508 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2511 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2514 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2519 static void enable_irq_window(struct kvm_vcpu *vcpu)
2521 struct vcpu_svm *svm = to_svm(vcpu);
2523 nested_svm_intr(svm);
2525 /* In case GIF=0 we can't rely on the CPU to tell us when
2526 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2527 * The next time we get that intercept, this function will be
2528 * called again though and we'll get the vintr intercept. */
2531 svm_inject_irq(svm, 0x0);
2535 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2537 struct vcpu_svm *svm = to_svm(vcpu);
2539 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2541 return; /* IRET will cause a vm exit */
2543 /* Something prevents NMI from been injected. Single step over
2544 possible problem (IRET or exception injection or interrupt
2546 vcpu->arch.singlestep = true;
2547 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2548 update_db_intercept(vcpu);
2551 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2556 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2558 force_new_asid(vcpu);
2561 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2565 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2567 struct vcpu_svm *svm = to_svm(vcpu);
2569 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2570 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2571 kvm_set_cr8(vcpu, cr8);
2575 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2577 struct vcpu_svm *svm = to_svm(vcpu);
2580 cr8 = kvm_get_cr8(vcpu);
2581 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2582 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2585 static void svm_complete_interrupts(struct vcpu_svm *svm)
2589 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2591 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2592 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2594 svm->vcpu.arch.nmi_injected = false;
2595 kvm_clear_exception_queue(&svm->vcpu);
2596 kvm_clear_interrupt_queue(&svm->vcpu);
2598 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2601 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2602 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2605 case SVM_EXITINTINFO_TYPE_NMI:
2606 svm->vcpu.arch.nmi_injected = true;
2608 case SVM_EXITINTINFO_TYPE_EXEPT:
2609 /* In case of software exception do not reinject an exception
2610 vector, but re-execute and instruction instead */
2613 if (kvm_exception_is_soft(vector))
2615 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2616 u32 err = svm->vmcb->control.exit_int_info_err;
2617 kvm_queue_exception_e(&svm->vcpu, vector, err);
2620 kvm_queue_exception(&svm->vcpu, vector);
2622 case SVM_EXITINTINFO_TYPE_INTR:
2623 kvm_queue_interrupt(&svm->vcpu, vector, false);
2630 #ifdef CONFIG_X86_64
2636 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2638 struct vcpu_svm *svm = to_svm(vcpu);
2644 * A vmexit emulation is required before the vcpu can be executed
2647 if (unlikely(svm->nested.exit_required))
2650 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2651 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2652 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2656 sync_lapic_to_cr8(vcpu);
2658 save_host_msrs(vcpu);
2659 fs_selector = kvm_read_fs();
2660 gs_selector = kvm_read_gs();
2661 ldt_selector = kvm_read_ldt();
2662 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2663 /* required for live migration with NPT */
2665 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2672 "push %%"R"bp; \n\t"
2673 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2674 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2675 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2676 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2677 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2678 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2679 #ifdef CONFIG_X86_64
2680 "mov %c[r8](%[svm]), %%r8 \n\t"
2681 "mov %c[r9](%[svm]), %%r9 \n\t"
2682 "mov %c[r10](%[svm]), %%r10 \n\t"
2683 "mov %c[r11](%[svm]), %%r11 \n\t"
2684 "mov %c[r12](%[svm]), %%r12 \n\t"
2685 "mov %c[r13](%[svm]), %%r13 \n\t"
2686 "mov %c[r14](%[svm]), %%r14 \n\t"
2687 "mov %c[r15](%[svm]), %%r15 \n\t"
2690 /* Enter guest mode */
2692 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2693 __ex(SVM_VMLOAD) "\n\t"
2694 __ex(SVM_VMRUN) "\n\t"
2695 __ex(SVM_VMSAVE) "\n\t"
2698 /* Save guest registers, load host registers */
2699 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2700 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2701 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2702 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2703 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2704 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2705 #ifdef CONFIG_X86_64
2706 "mov %%r8, %c[r8](%[svm]) \n\t"
2707 "mov %%r9, %c[r9](%[svm]) \n\t"
2708 "mov %%r10, %c[r10](%[svm]) \n\t"
2709 "mov %%r11, %c[r11](%[svm]) \n\t"
2710 "mov %%r12, %c[r12](%[svm]) \n\t"
2711 "mov %%r13, %c[r13](%[svm]) \n\t"
2712 "mov %%r14, %c[r14](%[svm]) \n\t"
2713 "mov %%r15, %c[r15](%[svm]) \n\t"
2718 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2719 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2720 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2721 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2722 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2723 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2724 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2725 #ifdef CONFIG_X86_64
2726 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2727 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2728 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2729 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2730 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2731 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2732 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2733 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2736 , R"bx", R"cx", R"dx", R"si", R"di"
2737 #ifdef CONFIG_X86_64
2738 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2742 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2743 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2744 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2745 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2747 kvm_load_fs(fs_selector);
2748 kvm_load_gs(gs_selector);
2749 kvm_load_ldt(ldt_selector);
2750 load_host_msrs(vcpu);
2754 local_irq_disable();
2758 sync_cr8_to_lapic(vcpu);
2763 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2764 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2770 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2772 struct vcpu_svm *svm = to_svm(vcpu);
2775 svm->vmcb->control.nested_cr3 = root;
2776 force_new_asid(vcpu);
2780 svm->vmcb->save.cr3 = root;
2781 force_new_asid(vcpu);
2783 if (vcpu->fpu_active) {
2784 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2785 svm->vmcb->save.cr0 |= X86_CR0_TS;
2786 vcpu->fpu_active = 0;
2790 static int is_disabled(void)
2794 rdmsrl(MSR_VM_CR, vm_cr);
2795 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2802 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2805 * Patch in the VMMCALL instruction:
2807 hypercall[0] = 0x0f;
2808 hypercall[1] = 0x01;
2809 hypercall[2] = 0xd9;
2812 static void svm_check_processor_compat(void *rtn)
2817 static bool svm_cpu_has_accelerated_tpr(void)
2822 static int get_npt_level(void)
2824 #ifdef CONFIG_X86_64
2825 return PT64_ROOT_LEVEL;
2827 return PT32E_ROOT_LEVEL;
2831 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2836 static const struct trace_print_flags svm_exit_reasons_str[] = {
2837 { SVM_EXIT_READ_CR0, "read_cr0" },
2838 { SVM_EXIT_READ_CR3, "read_cr3" },
2839 { SVM_EXIT_READ_CR4, "read_cr4" },
2840 { SVM_EXIT_READ_CR8, "read_cr8" },
2841 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2842 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2843 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2844 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2845 { SVM_EXIT_READ_DR0, "read_dr0" },
2846 { SVM_EXIT_READ_DR1, "read_dr1" },
2847 { SVM_EXIT_READ_DR2, "read_dr2" },
2848 { SVM_EXIT_READ_DR3, "read_dr3" },
2849 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2850 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2851 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2852 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2853 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2854 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2855 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2856 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2857 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2858 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2859 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2860 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2861 { SVM_EXIT_INTR, "interrupt" },
2862 { SVM_EXIT_NMI, "nmi" },
2863 { SVM_EXIT_SMI, "smi" },
2864 { SVM_EXIT_INIT, "init" },
2865 { SVM_EXIT_VINTR, "vintr" },
2866 { SVM_EXIT_CPUID, "cpuid" },
2867 { SVM_EXIT_INVD, "invd" },
2868 { SVM_EXIT_HLT, "hlt" },
2869 { SVM_EXIT_INVLPG, "invlpg" },
2870 { SVM_EXIT_INVLPGA, "invlpga" },
2871 { SVM_EXIT_IOIO, "io" },
2872 { SVM_EXIT_MSR, "msr" },
2873 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2874 { SVM_EXIT_SHUTDOWN, "shutdown" },
2875 { SVM_EXIT_VMRUN, "vmrun" },
2876 { SVM_EXIT_VMMCALL, "hypercall" },
2877 { SVM_EXIT_VMLOAD, "vmload" },
2878 { SVM_EXIT_VMSAVE, "vmsave" },
2879 { SVM_EXIT_STGI, "stgi" },
2880 { SVM_EXIT_CLGI, "clgi" },
2881 { SVM_EXIT_SKINIT, "skinit" },
2882 { SVM_EXIT_WBINVD, "wbinvd" },
2883 { SVM_EXIT_MONITOR, "monitor" },
2884 { SVM_EXIT_MWAIT, "mwait" },
2885 { SVM_EXIT_NPF, "npf" },
2889 static bool svm_gb_page_enable(void)
2894 static struct kvm_x86_ops svm_x86_ops = {
2895 .cpu_has_kvm_support = has_svm,
2896 .disabled_by_bios = is_disabled,
2897 .hardware_setup = svm_hardware_setup,
2898 .hardware_unsetup = svm_hardware_unsetup,
2899 .check_processor_compatibility = svm_check_processor_compat,
2900 .hardware_enable = svm_hardware_enable,
2901 .hardware_disable = svm_hardware_disable,
2902 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2904 .vcpu_create = svm_create_vcpu,
2905 .vcpu_free = svm_free_vcpu,
2906 .vcpu_reset = svm_vcpu_reset,
2908 .prepare_guest_switch = svm_prepare_guest_switch,
2909 .vcpu_load = svm_vcpu_load,
2910 .vcpu_put = svm_vcpu_put,
2912 .set_guest_debug = svm_guest_debug,
2913 .get_msr = svm_get_msr,
2914 .set_msr = svm_set_msr,
2915 .get_segment_base = svm_get_segment_base,
2916 .get_segment = svm_get_segment,
2917 .set_segment = svm_set_segment,
2918 .get_cpl = svm_get_cpl,
2919 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2920 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2921 .set_cr0 = svm_set_cr0,
2922 .set_cr3 = svm_set_cr3,
2923 .set_cr4 = svm_set_cr4,
2924 .set_efer = svm_set_efer,
2925 .get_idt = svm_get_idt,
2926 .set_idt = svm_set_idt,
2927 .get_gdt = svm_get_gdt,
2928 .set_gdt = svm_set_gdt,
2929 .get_dr = svm_get_dr,
2930 .set_dr = svm_set_dr,
2931 .cache_reg = svm_cache_reg,
2932 .get_rflags = svm_get_rflags,
2933 .set_rflags = svm_set_rflags,
2935 .tlb_flush = svm_flush_tlb,
2937 .run = svm_vcpu_run,
2938 .handle_exit = handle_exit,
2939 .skip_emulated_instruction = skip_emulated_instruction,
2940 .set_interrupt_shadow = svm_set_interrupt_shadow,
2941 .get_interrupt_shadow = svm_get_interrupt_shadow,
2942 .patch_hypercall = svm_patch_hypercall,
2943 .set_irq = svm_set_irq,
2944 .set_nmi = svm_inject_nmi,
2945 .queue_exception = svm_queue_exception,
2946 .interrupt_allowed = svm_interrupt_allowed,
2947 .nmi_allowed = svm_nmi_allowed,
2948 .enable_nmi_window = enable_nmi_window,
2949 .enable_irq_window = enable_irq_window,
2950 .update_cr8_intercept = update_cr8_intercept,
2952 .set_tss_addr = svm_set_tss_addr,
2953 .get_tdp_level = get_npt_level,
2954 .get_mt_mask = svm_get_mt_mask,
2956 .exit_reasons_str = svm_exit_reasons_str,
2957 .gb_page_enable = svm_gb_page_enable,
2960 static int __init svm_init(void)
2962 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2966 static void __exit svm_exit(void)
2971 module_init(svm_init)
2972 module_exit(svm_exit)