arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affilates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34
  35 #include <asm/virtext.h>
  36 #include "trace.h"
  37
  38 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  39
  40 MODULE_AUTHOR("Qumranet");
  41 MODULE_LICENSE("GPL");
  42
  43 #define IOPM_ALLOC_ORDER 2
  44 #define MSRPM_ALLOC_ORDER 1
  45
  46 #define SEG_TYPE_LDT 2
  47 #define SEG_TYPE_BUSY_TSS16 3
  48
  49 #define SVM_FEATURE_NPT            (1 <<  0)
  50 #define SVM_FEATURE_LBRV           (1 <<  1)
  51 #define SVM_FEATURE_SVML           (1 <<  2)
  52 #define SVM_FEATURE_NRIP           (1 <<  3)
  53 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  54
  55 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  56 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  57 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  58
  59 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  60
  61 static bool erratum_383_found __read_mostly;
  62
  63 static const u32 host_save_user_msrs[] = {
  64 #ifdef CONFIG_X86_64
  65         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  66         MSR_FS_BASE,
  67 #endif
  68         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  69 };
  70
  71 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  72
  73 struct kvm_vcpu;
  74
  75 struct nested_state {
  76         struct vmcb *hsave;
  77         u64 hsave_msr;
  78         u64 vm_cr_msr;
  79         u64 vmcb;
  80
  81         /* These are the merged vectors */
  82         u32 *msrpm;
  83
  84         /* gpa pointers to the real vectors */
  85         u64 vmcb_msrpm;
  86         u64 vmcb_iopm;
  87
  88         /* A VMEXIT is required but not yet emulated */
  89         bool exit_required;
  90
  91         /* cache for intercepts of the guest */
  92         u16 intercept_cr_read;
  93         u16 intercept_cr_write;
  94         u16 intercept_dr_read;
  95         u16 intercept_dr_write;
  96         u32 intercept_exceptions;
  97         u64 intercept;
  98
  99 };
 100
 101 #define MSRPM_OFFSETS   16
 102 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 103
 104 struct vcpu_svm {
 105         struct kvm_vcpu vcpu;
 106         struct vmcb *vmcb;
 107         unsigned long vmcb_pa;
 108         struct svm_cpu_data *svm_data;
 109         uint64_t asid_generation;
 110         uint64_t sysenter_esp;
 111         uint64_t sysenter_eip;
 112
 113         u64 next_rip;
 114
 115         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 116         u64 host_gs_base;
 117
 118         u32 *msrpm;
 119
 120         struct nested_state nested;
 121
 122         bool nmi_singlestep;
 123
 124         unsigned int3_injected;
 125         unsigned long int3_rip;
 126 };
 127
 128 #define MSR_INVALID                     0xffffffffU
 129
 130 static struct svm_direct_access_msrs {
 131         u32 index;   /* Index of the MSR */
 132         bool always; /* True if intercept is always on */
 133 } direct_access_msrs[] = {
 134         { .index = MSR_K6_STAR,                         .always = true  },
 135         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 136 #ifdef CONFIG_X86_64
 137         { .index = MSR_GS_BASE,                         .always = true  },
 138         { .index = MSR_FS_BASE,                         .always = true  },
 139         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 140         { .index = MSR_LSTAR,                           .always = true  },
 141         { .index = MSR_CSTAR,                           .always = true  },
 142         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 143 #endif
 144         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 145         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 146         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 147         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 148         { .index = MSR_INVALID,                         .always = false },
 149 };
 150
 151 /* enable NPT for AMD64 and X86 with PAE */
 152 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 153 static bool npt_enabled = true;
 154 #else
 155 static bool npt_enabled;
 156 #endif
 157 static int npt = 1;
 158
 159 module_param(npt, int, S_IRUGO);
 160
 161 static int nested = 1;
 162 module_param(nested, int, S_IRUGO);
 163
 164 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 165 static void svm_complete_interrupts(struct vcpu_svm *svm);
 166
 167 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 168 static int nested_svm_intercept(struct vcpu_svm *svm);
 169 static int nested_svm_vmexit(struct vcpu_svm *svm);
 170 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 171                                       bool has_error_code, u32 error_code);
 172
 173 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 174 {
 175         return container_of(vcpu, struct vcpu_svm, vcpu);
 176 }
 177
 178 static inline bool is_nested(struct vcpu_svm *svm)
 179 {
 180         return svm->nested.vmcb;
 181 }
 182
 183 static inline void enable_gif(struct vcpu_svm *svm)
 184 {
 185         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 186 }
 187
 188 static inline void disable_gif(struct vcpu_svm *svm)
 189 {
 190         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 191 }
 192
 193 static inline bool gif_set(struct vcpu_svm *svm)
 194 {
 195         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 196 }
 197
 198 static unsigned long iopm_base;
 199
 200 struct kvm_ldttss_desc {
 201         u16 limit0;
 202         u16 base0;
 203         unsigned base1:8, type:5, dpl:2, p:1;
 204         unsigned limit1:4, zero0:3, g:1, base2:8;
 205         u32 base3;
 206         u32 zero1;
 207 } __attribute__((packed));
 208
 209 struct svm_cpu_data {
 210         int cpu;
 211
 212         u64 asid_generation;
 213         u32 max_asid;
 214         u32 next_asid;
 215         struct kvm_ldttss_desc *tss_desc;
 216
 217         struct page *save_area;
 218 };
 219
 220 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 221 static uint32_t svm_features;
 222
 223 struct svm_init_data {
 224         int cpu;
 225         int r;
 226 };
 227
 228 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 229
 230 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 231 #define MSRS_RANGE_SIZE 2048
 232 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 233
 234 static u32 svm_msrpm_offset(u32 msr)
 235 {
 236         u32 offset;
 237         int i;
 238
 239         for (i = 0; i < NUM_MSR_MAPS; i++) {
 240                 if (msr < msrpm_ranges[i] ||
 241                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 242                         continue;
 243
 244                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 245                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 246
 247                 /* Now we have the u8 offset - but need the u32 offset */
 248                 return offset / 4;
 249         }
 250
 251         /* MSR not in any range */
 252         return MSR_INVALID;
 253 }
 254
 255 #define MAX_INST_SIZE 15
 256
 257 static inline u32 svm_has(u32 feat)
 258 {
 259         return svm_features & feat;
 260 }
 261
 262 static inline void clgi(void)
 263 {
 264         asm volatile (__ex(SVM_CLGI));
 265 }
 266
 267 static inline void stgi(void)
 268 {
 269         asm volatile (__ex(SVM_STGI));
 270 }
 271
 272 static inline void invlpga(unsigned long addr, u32 asid)
 273 {
 274         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 275 }
 276
 277 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 278 {
 279         to_svm(vcpu)->asid_generation--;
 280 }
 281
 282 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 283 {
 284         force_new_asid(vcpu);
 285 }
 286
 287 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 288 {
 289         if (!npt_enabled && !(efer & EFER_LMA))
 290                 efer &= ~EFER_LME;
 291
 292         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 293         vcpu->arch.efer = efer;
 294 }
 295
 296 static int is_external_interrupt(u32 info)
 297 {
 298         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 299         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 300 }
 301
 302 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 303 {
 304         struct vcpu_svm *svm = to_svm(vcpu);
 305         u32 ret = 0;
 306
 307         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 308                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 309         return ret & mask;
 310 }
 311
 312 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 313 {
 314         struct vcpu_svm *svm = to_svm(vcpu);
 315
 316         if (mask == 0)
 317                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 318         else
 319                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 320
 321 }
 322
 323 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 324 {
 325         struct vcpu_svm *svm = to_svm(vcpu);
 326
 327         if (svm->vmcb->control.next_rip != 0)
 328                 svm->next_rip = svm->vmcb->control.next_rip;
 329
 330         if (!svm->next_rip) {
 331                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 332                                 EMULATE_DONE)
 333                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 334                 return;
 335         }
 336         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 337                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 338                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 339
 340         kvm_rip_write(vcpu, svm->next_rip);
 341         svm_set_interrupt_shadow(vcpu, 0);
 342 }
 343
 344 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 345                                 bool has_error_code, u32 error_code,
 346                                 bool reinject)
 347 {
 348         struct vcpu_svm *svm = to_svm(vcpu);
 349
 350         /*
 351          * If we are within a nested VM we'd better #VMEXIT and let the guest
 352          * handle the exception
 353          */
 354         if (!reinject &&
 355             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 356                 return;
 357
 358         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 359                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 360
 361                 /*
 362                  * For guest debugging where we have to reinject #BP if some
 363                  * INT3 is guest-owned:
 364                  * Emulate nRIP by moving RIP forward. Will fail if injection
 365                  * raises a fault that is not intercepted. Still better than
 366                  * failing in all cases.
 367                  */
 368                 skip_emulated_instruction(&svm->vcpu);
 369                 rip = kvm_rip_read(&svm->vcpu);
 370                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 371                 svm->int3_injected = rip - old_rip;
 372         }
 373
 374         svm->vmcb->control.event_inj = nr
 375                 | SVM_EVTINJ_VALID
 376                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 377                 | SVM_EVTINJ_TYPE_EXEPT;
 378         svm->vmcb->control.event_inj_err = error_code;
 379 }
 380
 381 static void svm_init_erratum_383(void)
 382 {
 383         u32 low, high;
 384         int err;
 385         u64 val;
 386
 387         /* Only Fam10h is affected */
 388         if (boot_cpu_data.x86 != 0x10)
 389                 return;
 390
 391         /* Use _safe variants to not break nested virtualization */
 392         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 393         if (err)
 394                 return;
 395
 396         val |= (1ULL << 47);
 397
 398         low  = lower_32_bits(val);
 399         high = upper_32_bits(val);
 400
 401         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 402
 403         erratum_383_found = true;
 404 }
 405
 406 static int has_svm(void)
 407 {
 408         const char *msg;
 409
 410         if (!cpu_has_svm(&msg)) {
 411                 printk(KERN_INFO "has_svm: %s\n", msg);
 412                 return 0;
 413         }
 414
 415         return 1;
 416 }
 417
 418 static void svm_hardware_disable(void *garbage)
 419 {
 420         cpu_svm_disable();
 421 }
 422
 423 static int svm_hardware_enable(void *garbage)
 424 {
 425
 426         struct svm_cpu_data *sd;
 427         uint64_t efer;
 428         struct desc_ptr gdt_descr;
 429         struct desc_struct *gdt;
 430         int me = raw_smp_processor_id();
 431
 432         rdmsrl(MSR_EFER, efer);
 433         if (efer & EFER_SVME)
 434                 return -EBUSY;
 435
 436         if (!has_svm()) {
 437                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 438                        me);
 439                 return -EINVAL;
 440         }
 441         sd = per_cpu(svm_data, me);
 442
 443         if (!sd) {
 444                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 445                        me);
 446                 return -EINVAL;
 447         }
 448
 449         sd->asid_generation = 1;
 450         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 451         sd->next_asid = sd->max_asid + 1;
 452
 453         native_store_gdt(&gdt_descr);
 454         gdt = (struct desc_struct *)gdt_descr.address;
 455         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 456
 457         wrmsrl(MSR_EFER, efer | EFER_SVME);
 458
 459         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 460
 461         svm_init_erratum_383();
 462
 463         return 0;
 464 }
 465
 466 static void svm_cpu_uninit(int cpu)
 467 {
 468         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 469
 470         if (!sd)
 471                 return;
 472
 473         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 474         __free_page(sd->save_area);
 475         kfree(sd);
 476 }
 477
 478 static int svm_cpu_init(int cpu)
 479 {
 480         struct svm_cpu_data *sd;
 481         int r;
 482
 483         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 484         if (!sd)
 485                 return -ENOMEM;
 486         sd->cpu = cpu;
 487         sd->save_area = alloc_page(GFP_KERNEL);
 488         r = -ENOMEM;
 489         if (!sd->save_area)
 490                 goto err_1;
 491
 492         per_cpu(svm_data, cpu) = sd;
 493
 494         return 0;
 495
 496 err_1:
 497         kfree(sd);
 498         return r;
 499
 500 }
 501
 502 static bool valid_msr_intercept(u32 index)
 503 {
 504         int i;
 505
 506         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 507                 if (direct_access_msrs[i].index == index)
 508                         return true;
 509
 510         return false;
 511 }
 512
 513 static void set_msr_interception(u32 *msrpm, unsigned msr,
 514                                  int read, int write)
 515 {
 516         u8 bit_read, bit_write;
 517         unsigned long tmp;
 518         u32 offset;
 519
 520         /*
 521          * If this warning triggers extend the direct_access_msrs list at the
 522          * beginning of the file
 523          */
 524         WARN_ON(!valid_msr_intercept(msr));
 525
 526         offset    = svm_msrpm_offset(msr);
 527         bit_read  = 2 * (msr & 0x0f);
 528         bit_write = 2 * (msr & 0x0f) + 1;
 529         tmp       = msrpm[offset];
 530
 531         BUG_ON(offset == MSR_INVALID);
 532
 533         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 534         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 535
 536         msrpm[offset] = tmp;
 537 }
 538
 539 static void svm_vcpu_init_msrpm(u32 *msrpm)
 540 {
 541         int i;
 542
 543         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 544
 545         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 546                 if (!direct_access_msrs[i].always)
 547                         continue;
 548
 549                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 550         }
 551 }
 552
 553 static void add_msr_offset(u32 offset)
 554 {
 555         int i;
 556
 557         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 558
 559                 /* Offset already in list? */
 560                 if (msrpm_offsets[i] == offset)
 561                         return;
 562
 563                 /* Slot used by another offset? */
 564                 if (msrpm_offsets[i] != MSR_INVALID)
 565                         continue;
 566
 567                 /* Add offset to list */
 568                 msrpm_offsets[i] = offset;
 569
 570                 return;
 571         }
 572
 573         /*
 574          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 575          * increase MSRPM_OFFSETS in this case.
 576          */
 577         BUG();
 578 }
 579
 580 static void init_msrpm_offsets(void)
 581 {
 582         int i;
 583
 584         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 585
 586         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 587                 u32 offset;
 588
 589                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 590                 BUG_ON(offset == MSR_INVALID);
 591
 592                 add_msr_offset(offset);
 593         }
 594 }
 595
 596 static void svm_enable_lbrv(struct vcpu_svm *svm)
 597 {
 598         u32 *msrpm = svm->msrpm;
 599
 600         svm->vmcb->control.lbr_ctl = 1;
 601         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 602         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 603         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 604         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 605 }
 606
 607 static void svm_disable_lbrv(struct vcpu_svm *svm)
 608 {
 609         u32 *msrpm = svm->msrpm;
 610
 611         svm->vmcb->control.lbr_ctl = 0;
 612         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 613         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 614         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 615         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 616 }
 617
 618 static __init int svm_hardware_setup(void)
 619 {
 620         int cpu;
 621         struct page *iopm_pages;
 622         void *iopm_va;
 623         int r;
 624
 625         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 626
 627         if (!iopm_pages)
 628                 return -ENOMEM;
 629
 630         iopm_va = page_address(iopm_pages);
 631         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 632         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 633
 634         init_msrpm_offsets();
 635
 636         if (boot_cpu_has(X86_FEATURE_NX))
 637                 kvm_enable_efer_bits(EFER_NX);
 638
 639         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 640                 kvm_enable_efer_bits(EFER_FFXSR);
 641
 642         if (nested) {
 643                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 644                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 645         }
 646
 647         for_each_possible_cpu(cpu) {
 648                 r = svm_cpu_init(cpu);
 649                 if (r)
 650                         goto err;
 651         }
 652
 653         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 654
 655         if (!svm_has(SVM_FEATURE_NPT))
 656                 npt_enabled = false;
 657
 658         if (npt_enabled && !npt) {
 659                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 660                 npt_enabled = false;
 661         }
 662
 663         if (npt_enabled) {
 664                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 665                 kvm_enable_tdp();
 666         } else
 667                 kvm_disable_tdp();
 668
 669         return 0;
 670
 671 err:
 672         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 673         iopm_base = 0;
 674         return r;
 675 }
 676
 677 static __exit void svm_hardware_unsetup(void)
 678 {
 679         int cpu;
 680
 681         for_each_possible_cpu(cpu)
 682                 svm_cpu_uninit(cpu);
 683
 684         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 685         iopm_base = 0;
 686 }
 687
 688 static void init_seg(struct vmcb_seg *seg)
 689 {
 690         seg->selector = 0;
 691         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 692                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 693         seg->limit = 0xffff;
 694         seg->base = 0;
 695 }
 696
 697 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 698 {
 699         seg->selector = 0;
 700         seg->attrib = SVM_SELECTOR_P_MASK | type;
 701         seg->limit = 0xffff;
 702         seg->base = 0;
 703 }
 704
 705 static void init_vmcb(struct vcpu_svm *svm)
 706 {
 707         struct vmcb_control_area *control = &svm->vmcb->control;
 708         struct vmcb_save_area *save = &svm->vmcb->save;
 709
 710         svm->vcpu.fpu_active = 1;
 711
 712         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 713                                         INTERCEPT_CR3_MASK |
 714                                         INTERCEPT_CR4_MASK;
 715
 716         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 717                                         INTERCEPT_CR3_MASK |
 718                                         INTERCEPT_CR4_MASK |
 719                                         INTERCEPT_CR8_MASK;
 720
 721         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 722                                         INTERCEPT_DR1_MASK |
 723                                         INTERCEPT_DR2_MASK |
 724                                         INTERCEPT_DR3_MASK |
 725                                         INTERCEPT_DR4_MASK |
 726                                         INTERCEPT_DR5_MASK |
 727                                         INTERCEPT_DR6_MASK |
 728                                         INTERCEPT_DR7_MASK;
 729
 730         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 731                                         INTERCEPT_DR1_MASK |
 732                                         INTERCEPT_DR2_MASK |
 733                                         INTERCEPT_DR3_MASK |
 734                                         INTERCEPT_DR4_MASK |
 735                                         INTERCEPT_DR5_MASK |
 736                                         INTERCEPT_DR6_MASK |
 737                                         INTERCEPT_DR7_MASK;
 738
 739         control->intercept_exceptions = (1 << PF_VECTOR) |
 740                                         (1 << UD_VECTOR) |
 741                                         (1 << MC_VECTOR);
 742
 743
 744         control->intercept =    (1ULL << INTERCEPT_INTR) |
 745                                 (1ULL << INTERCEPT_NMI) |
 746                                 (1ULL << INTERCEPT_SMI) |
 747                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 748                                 (1ULL << INTERCEPT_CPUID) |
 749                                 (1ULL << INTERCEPT_INVD) |
 750                                 (1ULL << INTERCEPT_HLT) |
 751                                 (1ULL << INTERCEPT_INVLPG) |
 752                                 (1ULL << INTERCEPT_INVLPGA) |
 753                                 (1ULL << INTERCEPT_IOIO_PROT) |
 754                                 (1ULL << INTERCEPT_MSR_PROT) |
 755                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 756                                 (1ULL << INTERCEPT_SHUTDOWN) |
 757                                 (1ULL << INTERCEPT_VMRUN) |
 758                                 (1ULL << INTERCEPT_VMMCALL) |
 759                                 (1ULL << INTERCEPT_VMLOAD) |
 760                                 (1ULL << INTERCEPT_VMSAVE) |
 761                                 (1ULL << INTERCEPT_STGI) |
 762                                 (1ULL << INTERCEPT_CLGI) |
 763                                 (1ULL << INTERCEPT_SKINIT) |
 764                                 (1ULL << INTERCEPT_WBINVD) |
 765                                 (1ULL << INTERCEPT_MONITOR) |
 766                                 (1ULL << INTERCEPT_MWAIT);
 767
 768         control->iopm_base_pa = iopm_base;
 769         control->msrpm_base_pa = __pa(svm->msrpm);
 770         control->tsc_offset = 0;
 771         control->int_ctl = V_INTR_MASKING_MASK;
 772
 773         init_seg(&save->es);
 774         init_seg(&save->ss);
 775         init_seg(&save->ds);
 776         init_seg(&save->fs);
 777         init_seg(&save->gs);
 778
 779         save->cs.selector = 0xf000;
 780         /* Executable/Readable Code Segment */
 781         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 782                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 783         save->cs.limit = 0xffff;
 784         /*
 785          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 786          * be consistent with it.
 787          *
 788          * Replace when we have real mode working for vmx.
 789          */
 790         save->cs.base = 0xf0000;
 791
 792         save->gdtr.limit = 0xffff;
 793         save->idtr.limit = 0xffff;
 794
 795         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 796         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 797
 798         save->efer = EFER_SVME;
 799         save->dr6 = 0xffff0ff0;
 800         save->dr7 = 0x400;
 801         save->rflags = 2;
 802         save->rip = 0x0000fff0;
 803         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 804
 805         /*
 806          * This is the guest-visible cr0 value.
 807          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 808          */
 809         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 810         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 811
 812         save->cr4 = X86_CR4_PAE;
 813         /* rdx = ?? */
 814
 815         if (npt_enabled) {
 816                 /* Setup VMCB for Nested Paging */
 817                 control->nested_ctl = 1;
 818                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 819                                         (1ULL << INTERCEPT_INVLPG));
 820                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 821                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 822                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 823                 save->g_pat = 0x0007040600070406ULL;
 824                 save->cr3 = 0;
 825                 save->cr4 = 0;
 826         }
 827         force_new_asid(&svm->vcpu);
 828
 829         svm->nested.vmcb = 0;
 830         svm->vcpu.arch.hflags = 0;
 831
 832         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 833                 control->pause_filter_count = 3000;
 834                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 835         }
 836
 837         enable_gif(svm);
 838 }
 839
 840 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 841 {
 842         struct vcpu_svm *svm = to_svm(vcpu);
 843
 844         init_vmcb(svm);
 845
 846         if (!kvm_vcpu_is_bsp(vcpu)) {
 847                 kvm_rip_write(vcpu, 0);
 848                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 849                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 850         }
 851         vcpu->arch.regs_avail = ~0;
 852         vcpu->arch.regs_dirty = ~0;
 853
 854         return 0;
 855 }
 856
 857 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 858 {
 859         struct vcpu_svm *svm;
 860         struct page *page;
 861         struct page *msrpm_pages;
 862         struct page *hsave_page;
 863         struct page *nested_msrpm_pages;
 864         int err;
 865
 866         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 867         if (!svm) {
 868                 err = -ENOMEM;
 869                 goto out;
 870         }
 871
 872         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 873         if (err)
 874                 goto free_svm;
 875
 876         err = -ENOMEM;
 877         page = alloc_page(GFP_KERNEL);
 878         if (!page)
 879                 goto uninit;
 880
 881         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 882         if (!msrpm_pages)
 883                 goto free_page1;
 884
 885         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 886         if (!nested_msrpm_pages)
 887                 goto free_page2;
 888
 889         hsave_page = alloc_page(GFP_KERNEL);
 890         if (!hsave_page)
 891                 goto free_page3;
 892
 893         svm->nested.hsave = page_address(hsave_page);
 894
 895         svm->msrpm = page_address(msrpm_pages);
 896         svm_vcpu_init_msrpm(svm->msrpm);
 897
 898         svm->nested.msrpm = page_address(nested_msrpm_pages);
 899         svm_vcpu_init_msrpm(svm->nested.msrpm);
 900
 901         svm->vmcb = page_address(page);
 902         clear_page(svm->vmcb);
 903         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 904         svm->asid_generation = 0;
 905         init_vmcb(svm);
 906
 907         fx_init(&svm->vcpu);
 908         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 909         if (kvm_vcpu_is_bsp(&svm->vcpu))
 910                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 911
 912         return &svm->vcpu;
 913
 914 free_page3:
 915         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 916 free_page2:
 917         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 918 free_page1:
 919         __free_page(page);
 920 uninit:
 921         kvm_vcpu_uninit(&svm->vcpu);
 922 free_svm:
 923         kmem_cache_free(kvm_vcpu_cache, svm);
 924 out:
 925         return ERR_PTR(err);
 926 }
 927
 928 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 929 {
 930         struct vcpu_svm *svm = to_svm(vcpu);
 931
 932         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 933         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 934         __free_page(virt_to_page(svm->nested.hsave));
 935         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 936         kvm_vcpu_uninit(vcpu);
 937         kmem_cache_free(kvm_vcpu_cache, svm);
 938 }
 939
 940 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 941 {
 942         struct vcpu_svm *svm = to_svm(vcpu);
 943         int i;
 944
 945         if (unlikely(cpu != vcpu->cpu)) {
 946                 u64 delta;
 947
 948                 if (check_tsc_unstable()) {
 949                         /*
 950                          * Make sure that the guest sees a monotonically
 951                          * increasing TSC.
 952                          */
 953                         delta = vcpu->arch.host_tsc - native_read_tsc();
 954                         svm->vmcb->control.tsc_offset += delta;
 955                         if (is_nested(svm))
 956                                 svm->nested.hsave->control.tsc_offset += delta;
 957                 }
 958                 vcpu->cpu = cpu;
 959                 kvm_migrate_timers(vcpu);
 960                 svm->asid_generation = 0;
 961         }
 962
 963         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 964                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 965 }
 966
 967 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 968 {
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970         int i;
 971
 972         ++vcpu->stat.host_state_reload;
 973         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 974                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 975
 976         vcpu->arch.host_tsc = native_read_tsc();
 977 }
 978
 979 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 980 {
 981         return to_svm(vcpu)->vmcb->save.rflags;
 982 }
 983
 984 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 985 {
 986         to_svm(vcpu)->vmcb->save.rflags = rflags;
 987 }
 988
 989 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 990 {
 991         switch (reg) {
 992         case VCPU_EXREG_PDPTR:
 993                 BUG_ON(!npt_enabled);
 994                 load_pdptrs(vcpu, vcpu->arch.cr3);
 995                 break;
 996         default:
 997                 BUG();
 998         }
 999 }
1000
1001 static void svm_set_vintr(struct vcpu_svm *svm)
1002 {
1003         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1004 }
1005
1006 static void svm_clear_vintr(struct vcpu_svm *svm)
1007 {
1008         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1009 }
1010
1011 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1012 {
1013         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1014
1015         switch (seg) {
1016         case VCPU_SREG_CS: return &save->cs;
1017         case VCPU_SREG_DS: return &save->ds;
1018         case VCPU_SREG_ES: return &save->es;
1019         case VCPU_SREG_FS: return &save->fs;
1020         case VCPU_SREG_GS: return &save->gs;
1021         case VCPU_SREG_SS: return &save->ss;
1022         case VCPU_SREG_TR: return &save->tr;
1023         case VCPU_SREG_LDTR: return &save->ldtr;
1024         }
1025         BUG();
1026         return NULL;
1027 }
1028
1029 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1030 {
1031         struct vmcb_seg *s = svm_seg(vcpu, seg);
1032
1033         return s->base;
1034 }
1035
1036 static void svm_get_segment(struct kvm_vcpu *vcpu,
1037                             struct kvm_segment *var, int seg)
1038 {
1039         struct vmcb_seg *s = svm_seg(vcpu, seg);
1040
1041         var->base = s->base;
1042         var->limit = s->limit;
1043         var->selector = s->selector;
1044         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1045         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1046         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1047         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1048         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1049         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1050         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1051         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1052
1053         /*
1054          * AMD's VMCB does not have an explicit unusable field, so emulate it
1055          * for cross vendor migration purposes by "not present"
1056          */
1057         var->unusable = !var->present || (var->type == 0);
1058
1059         switch (seg) {
1060         case VCPU_SREG_CS:
1061                 /*
1062                  * SVM always stores 0 for the 'G' bit in the CS selector in
1063                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1064                  * Intel's VMENTRY has a check on the 'G' bit.
1065                  */
1066                 var->g = s->limit > 0xfffff;
1067                 break;
1068         case VCPU_SREG_TR:
1069                 /*
1070                  * Work around a bug where the busy flag in the tr selector
1071                  * isn't exposed
1072                  */
1073                 var->type |= 0x2;
1074                 break;
1075         case VCPU_SREG_DS:
1076         case VCPU_SREG_ES:
1077         case VCPU_SREG_FS:
1078         case VCPU_SREG_GS:
1079                 /*
1080                  * The accessed bit must always be set in the segment
1081                  * descriptor cache, although it can be cleared in the
1082                  * descriptor, the cached bit always remains at 1. Since
1083                  * Intel has a check on this, set it here to support
1084                  * cross-vendor migration.
1085                  */
1086                 if (!var->unusable)
1087                         var->type |= 0x1;
1088                 break;
1089         case VCPU_SREG_SS:
1090                 /*
1091                  * On AMD CPUs sometimes the DB bit in the segment
1092                  * descriptor is left as 1, although the whole segment has
1093                  * been made unusable. Clear it here to pass an Intel VMX
1094                  * entry check when cross vendor migrating.
1095                  */
1096                 if (var->unusable)
1097                         var->db = 0;
1098                 break;
1099         }
1100 }
1101
1102 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1103 {
1104         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1105
1106         return save->cpl;
1107 }
1108
1109 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1110 {
1111         struct vcpu_svm *svm = to_svm(vcpu);
1112
1113         dt->size = svm->vmcb->save.idtr.limit;
1114         dt->address = svm->vmcb->save.idtr.base;
1115 }
1116
1117 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1118 {
1119         struct vcpu_svm *svm = to_svm(vcpu);
1120
1121         svm->vmcb->save.idtr.limit = dt->size;
1122         svm->vmcb->save.idtr.base = dt->address ;
1123 }
1124
1125 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1126 {
1127         struct vcpu_svm *svm = to_svm(vcpu);
1128
1129         dt->size = svm->vmcb->save.gdtr.limit;
1130         dt->address = svm->vmcb->save.gdtr.base;
1131 }
1132
1133 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1134 {
1135         struct vcpu_svm *svm = to_svm(vcpu);
1136
1137         svm->vmcb->save.gdtr.limit = dt->size;
1138         svm->vmcb->save.gdtr.base = dt->address ;
1139 }
1140
1141 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1142 {
1143 }
1144
1145 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1146 {
1147 }
1148
1149 static void update_cr0_intercept(struct vcpu_svm *svm)
1150 {
1151         struct vmcb *vmcb = svm->vmcb;
1152         ulong gcr0 = svm->vcpu.arch.cr0;
1153         u64 *hcr0 = &svm->vmcb->save.cr0;
1154
1155         if (!svm->vcpu.fpu_active)
1156                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1157         else
1158                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1159                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1160
1161
1162         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1163                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1164                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1165                 if (is_nested(svm)) {
1166                         struct vmcb *hsave = svm->nested.hsave;
1167
1168                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1169                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1170                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1171                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1172                 }
1173         } else {
1174                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1175                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1176                 if (is_nested(svm)) {
1177                         struct vmcb *hsave = svm->nested.hsave;
1178
1179                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1180                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1181                 }
1182         }
1183 }
1184
1185 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1186 {
1187         struct vcpu_svm *svm = to_svm(vcpu);
1188
1189         if (is_nested(svm)) {
1190                 /*
1191                  * We are here because we run in nested mode, the host kvm
1192                  * intercepts cr0 writes but the l1 hypervisor does not.
1193                  * But the L1 hypervisor may intercept selective cr0 writes.
1194                  * This needs to be checked here.
1195                  */
1196                 unsigned long old, new;
1197
1198                 /* Remove bits that would trigger a real cr0 write intercept */
1199                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1200                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1201
1202                 if (old == new) {
1203                         /* cr0 write with ts and mp unchanged */
1204                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1205                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1206                                 return;
1207                 }
1208         }
1209
1210 #ifdef CONFIG_X86_64
1211         if (vcpu->arch.efer & EFER_LME) {
1212                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1213                         vcpu->arch.efer |= EFER_LMA;
1214                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1215                 }
1216
1217                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1218                         vcpu->arch.efer &= ~EFER_LMA;
1219                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1220                 }
1221         }
1222 #endif
1223         vcpu->arch.cr0 = cr0;
1224
1225         if (!npt_enabled)
1226                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1227
1228         if (!vcpu->fpu_active)
1229                 cr0 |= X86_CR0_TS;
1230         /*
1231          * re-enable caching here because the QEMU bios
1232          * does not do it - this results in some delay at
1233          * reboot
1234          */
1235         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1236         svm->vmcb->save.cr0 = cr0;
1237         update_cr0_intercept(svm);
1238 }
1239
1240 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1241 {
1242         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1243         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1244
1245         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1246                 force_new_asid(vcpu);
1247
1248         vcpu->arch.cr4 = cr4;
1249         if (!npt_enabled)
1250                 cr4 |= X86_CR4_PAE;
1251         cr4 |= host_cr4_mce;
1252         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1253 }
1254
1255 static void svm_set_segment(struct kvm_vcpu *vcpu,
1256                             struct kvm_segment *var, int seg)
1257 {
1258         struct vcpu_svm *svm = to_svm(vcpu);
1259         struct vmcb_seg *s = svm_seg(vcpu, seg);
1260
1261         s->base = var->base;
1262         s->limit = var->limit;
1263         s->selector = var->selector;
1264         if (var->unusable)
1265                 s->attrib = 0;
1266         else {
1267                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1268                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1269                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1270                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1271                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1272                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1273                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1274                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1275         }
1276         if (seg == VCPU_SREG_CS)
1277                 svm->vmcb->save.cpl
1278                         = (svm->vmcb->save.cs.attrib
1279                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1280
1281 }
1282
1283 static void update_db_intercept(struct kvm_vcpu *vcpu)
1284 {
1285         struct vcpu_svm *svm = to_svm(vcpu);
1286
1287         svm->vmcb->control.intercept_exceptions &=
1288                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1289
1290         if (svm->nmi_singlestep)
1291                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1292
1293         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1294                 if (vcpu->guest_debug &
1295                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1296                         svm->vmcb->control.intercept_exceptions |=
1297                                 1 << DB_VECTOR;
1298                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1299                         svm->vmcb->control.intercept_exceptions |=
1300                                 1 << BP_VECTOR;
1301         } else
1302                 vcpu->guest_debug = 0;
1303 }
1304
1305 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1306 {
1307         struct vcpu_svm *svm = to_svm(vcpu);
1308
1309         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1310                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1311         else
1312                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1313
1314         update_db_intercept(vcpu);
1315 }
1316
1317 static void load_host_msrs(struct kvm_vcpu *vcpu)
1318 {
1319 #ifdef CONFIG_X86_64
1320         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1321 #endif
1322 }
1323
1324 static void save_host_msrs(struct kvm_vcpu *vcpu)
1325 {
1326 #ifdef CONFIG_X86_64
1327         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1328 #endif
1329 }
1330
1331 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1332 {
1333         if (sd->next_asid > sd->max_asid) {
1334                 ++sd->asid_generation;
1335                 sd->next_asid = 1;
1336                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1337         }
1338
1339         svm->asid_generation = sd->asid_generation;
1340         svm->vmcb->control.asid = sd->next_asid++;
1341 }
1342
1343 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1344 {
1345         struct vcpu_svm *svm = to_svm(vcpu);
1346
1347         svm->vmcb->save.dr7 = value;
1348 }
1349
1350 static int pf_interception(struct vcpu_svm *svm)
1351 {
1352         u64 fault_address;
1353         u32 error_code;
1354
1355         fault_address  = svm->vmcb->control.exit_info_2;
1356         error_code = svm->vmcb->control.exit_info_1;
1357
1358         trace_kvm_page_fault(fault_address, error_code);
1359         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1360                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1361         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1362 }
1363
1364 static int db_interception(struct vcpu_svm *svm)
1365 {
1366         struct kvm_run *kvm_run = svm->vcpu.run;
1367
1368         if (!(svm->vcpu.guest_debug &
1369               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1370                 !svm->nmi_singlestep) {
1371                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1372                 return 1;
1373         }
1374
1375         if (svm->nmi_singlestep) {
1376                 svm->nmi_singlestep = false;
1377                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1378                         svm->vmcb->save.rflags &=
1379                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1380                 update_db_intercept(&svm->vcpu);
1381         }
1382
1383         if (svm->vcpu.guest_debug &
1384             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1385                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1386                 kvm_run->debug.arch.pc =
1387                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1388                 kvm_run->debug.arch.exception = DB_VECTOR;
1389                 return 0;
1390         }
1391
1392         return 1;
1393 }
1394
1395 static int bp_interception(struct vcpu_svm *svm)
1396 {
1397         struct kvm_run *kvm_run = svm->vcpu.run;
1398
1399         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1400         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1401         kvm_run->debug.arch.exception = BP_VECTOR;
1402         return 0;
1403 }
1404
1405 static int ud_interception(struct vcpu_svm *svm)
1406 {
1407         int er;
1408
1409         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1410         if (er != EMULATE_DONE)
1411                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1412         return 1;
1413 }
1414
1415 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1416 {
1417         struct vcpu_svm *svm = to_svm(vcpu);
1418         u32 excp;
1419
1420         if (is_nested(svm)) {
1421                 u32 h_excp, n_excp;
1422
1423                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1424                 n_excp  = svm->nested.intercept_exceptions;
1425                 h_excp &= ~(1 << NM_VECTOR);
1426                 excp    = h_excp | n_excp;
1427         } else {
1428                 excp  = svm->vmcb->control.intercept_exceptions;
1429                 excp &= ~(1 << NM_VECTOR);
1430         }
1431
1432         svm->vmcb->control.intercept_exceptions = excp;
1433
1434         svm->vcpu.fpu_active = 1;
1435         update_cr0_intercept(svm);
1436 }
1437
1438 static int nm_interception(struct vcpu_svm *svm)
1439 {
1440         svm_fpu_activate(&svm->vcpu);
1441         return 1;
1442 }
1443
1444 static bool is_erratum_383(void)
1445 {
1446         int err, i;
1447         u64 value;
1448
1449         if (!erratum_383_found)
1450                 return false;
1451
1452         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1453         if (err)
1454                 return false;
1455
1456         /* Bit 62 may or may not be set for this mce */
1457         value &= ~(1ULL << 62);
1458
1459         if (value != 0xb600000000010015ULL)
1460                 return false;
1461
1462         /* Clear MCi_STATUS registers */
1463         for (i = 0; i < 6; ++i)
1464                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1465
1466         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1467         if (!err) {
1468                 u32 low, high;
1469
1470                 value &= ~(1ULL << 2);
1471                 low    = lower_32_bits(value);
1472                 high   = upper_32_bits(value);
1473
1474                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1475         }
1476
1477         /* Flush tlb to evict multi-match entries */
1478         __flush_tlb_all();
1479
1480         return true;
1481 }
1482
1483 static void svm_handle_mce(struct vcpu_svm *svm)
1484 {
1485         if (is_erratum_383()) {
1486                 /*
1487                  * Erratum 383 triggered. Guest state is corrupt so kill the
1488                  * guest.
1489                  */
1490                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1491
1492                 set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests);
1493
1494                 return;
1495         }
1496
1497         /*
1498          * On an #MC intercept the MCE handler is not called automatically in
1499          * the host. So do it by hand here.
1500          */
1501         asm volatile (
1502                 "int $0x12\n");
1503         /* not sure if we ever come back to this point */
1504
1505         return;
1506 }
1507
1508 static int mc_interception(struct vcpu_svm *svm)
1509 {
1510         return 1;
1511 }
1512
1513 static int shutdown_interception(struct vcpu_svm *svm)
1514 {
1515         struct kvm_run *kvm_run = svm->vcpu.run;
1516
1517         /*
1518          * VMCB is undefined after a SHUTDOWN intercept
1519          * so reinitialize it.
1520          */
1521         clear_page(svm->vmcb);
1522         init_vmcb(svm);
1523
1524         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1525         return 0;
1526 }
1527
1528 static int io_interception(struct vcpu_svm *svm)
1529 {
1530         struct kvm_vcpu *vcpu = &svm->vcpu;
1531         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1532         int size, in, string;
1533         unsigned port;
1534
1535         ++svm->vcpu.stat.io_exits;
1536         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1537         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1538         if (string || in)
1539                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1540
1541         port = io_info >> 16;
1542         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1543         svm->next_rip = svm->vmcb->control.exit_info_2;
1544         skip_emulated_instruction(&svm->vcpu);
1545
1546         return kvm_fast_pio_out(vcpu, size, port);
1547 }
1548
1549 static int nmi_interception(struct vcpu_svm *svm)
1550 {
1551         return 1;
1552 }
1553
1554 static int intr_interception(struct vcpu_svm *svm)
1555 {
1556         ++svm->vcpu.stat.irq_exits;
1557         return 1;
1558 }
1559
1560 static int nop_on_interception(struct vcpu_svm *svm)
1561 {
1562         return 1;
1563 }
1564
1565 static int halt_interception(struct vcpu_svm *svm)
1566 {
1567         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1568         skip_emulated_instruction(&svm->vcpu);
1569         return kvm_emulate_halt(&svm->vcpu);
1570 }
1571
1572 static int vmmcall_interception(struct vcpu_svm *svm)
1573 {
1574         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1575         skip_emulated_instruction(&svm->vcpu);
1576         kvm_emulate_hypercall(&svm->vcpu);
1577         return 1;
1578 }
1579
1580 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1581 {
1582         if (!(svm->vcpu.arch.efer & EFER_SVME)
1583             || !is_paging(&svm->vcpu)) {
1584                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1585                 return 1;
1586         }
1587
1588         if (svm->vmcb->save.cpl) {
1589                 kvm_inject_gp(&svm->vcpu, 0);
1590                 return 1;
1591         }
1592
1593        return 0;
1594 }
1595
1596 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1597                                       bool has_error_code, u32 error_code)
1598 {
1599         int vmexit;
1600
1601         if (!is_nested(svm))
1602                 return 0;
1603
1604         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1605         svm->vmcb->control.exit_code_hi = 0;
1606         svm->vmcb->control.exit_info_1 = error_code;
1607         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1608
1609         vmexit = nested_svm_intercept(svm);
1610         if (vmexit == NESTED_EXIT_DONE)
1611                 svm->nested.exit_required = true;
1612
1613         return vmexit;
1614 }
1615
1616 /* This function returns true if it is save to enable the irq window */
1617 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1618 {
1619         if (!is_nested(svm))
1620                 return true;
1621
1622         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1623                 return true;
1624
1625         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1626                 return false;
1627
1628         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1629         svm->vmcb->control.exit_info_1 = 0;
1630         svm->vmcb->control.exit_info_2 = 0;
1631
1632         if (svm->nested.intercept & 1ULL) {
1633                 /*
1634                  * The #vmexit can't be emulated here directly because this
1635                  * code path runs with irqs and preemtion disabled. A
1636                  * #vmexit emulation might sleep. Only signal request for
1637                  * the #vmexit here.
1638                  */
1639                 svm->nested.exit_required = true;
1640                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1641                 return false;
1642         }
1643
1644         return true;
1645 }
1646
1647 /* This function returns true if it is save to enable the nmi window */
1648 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1649 {
1650         if (!is_nested(svm))
1651                 return true;
1652
1653         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1654                 return true;
1655
1656         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1657         svm->nested.exit_required = true;
1658
1659         return false;
1660 }
1661
1662 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1663 {
1664         struct page *page;
1665
1666         might_sleep();
1667
1668         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1669         if (is_error_page(page))
1670                 goto error;
1671
1672         *_page = page;
1673
1674         return kmap(page);
1675
1676 error:
1677         kvm_release_page_clean(page);
1678         kvm_inject_gp(&svm->vcpu, 0);
1679
1680         return NULL;
1681 }
1682
1683 static void nested_svm_unmap(struct page *page)
1684 {
1685         kunmap(page);
1686         kvm_release_page_dirty(page);
1687 }
1688
1689 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1690 {
1691         unsigned port;
1692         u8 val, bit;
1693         u64 gpa;
1694
1695         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1696                 return NESTED_EXIT_HOST;
1697
1698         port = svm->vmcb->control.exit_info_1 >> 16;
1699         gpa  = svm->nested.vmcb_iopm + (port / 8);
1700         bit  = port % 8;
1701         val  = 0;
1702
1703         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1704                 val &= (1 << bit);
1705
1706         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1707 }
1708
1709 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1710 {
1711         u32 offset, msr, value;
1712         int write, mask;
1713
1714         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1715                 return NESTED_EXIT_HOST;
1716
1717         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1718         offset = svm_msrpm_offset(msr);
1719         write  = svm->vmcb->control.exit_info_1 & 1;
1720         mask   = 1 << ((2 * (msr & 0xf)) + write);
1721
1722         if (offset == MSR_INVALID)
1723                 return NESTED_EXIT_DONE;
1724
1725         /* Offset is in 32 bit units but need in 8 bit units */
1726         offset *= 4;
1727
1728         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1729                 return NESTED_EXIT_DONE;
1730
1731         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1732 }
1733
1734 static int nested_svm_exit_special(struct vcpu_svm *svm)
1735 {
1736         u32 exit_code = svm->vmcb->control.exit_code;
1737
1738         switch (exit_code) {
1739         case SVM_EXIT_INTR:
1740         case SVM_EXIT_NMI:
1741         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1742                 return NESTED_EXIT_HOST;
1743         case SVM_EXIT_NPF:
1744                 /* For now we are always handling NPFs when using them */
1745                 if (npt_enabled)
1746                         return NESTED_EXIT_HOST;
1747                 break;
1748         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1749                 /* When we're shadowing, trap PFs */
1750                 if (!npt_enabled)
1751                         return NESTED_EXIT_HOST;
1752                 break;
1753         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1754                 nm_interception(svm);
1755                 break;
1756         default:
1757                 break;
1758         }
1759
1760         return NESTED_EXIT_CONTINUE;
1761 }
1762
1763 /*
1764  * If this function returns true, this #vmexit was already handled
1765  */
1766 static int nested_svm_intercept(struct vcpu_svm *svm)
1767 {
1768         u32 exit_code = svm->vmcb->control.exit_code;
1769         int vmexit = NESTED_EXIT_HOST;
1770
1771         switch (exit_code) {
1772         case SVM_EXIT_MSR:
1773                 vmexit = nested_svm_exit_handled_msr(svm);
1774                 break;
1775         case SVM_EXIT_IOIO:
1776                 vmexit = nested_svm_intercept_ioio(svm);
1777                 break;
1778         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1779                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1780                 if (svm->nested.intercept_cr_read & cr_bits)
1781                         vmexit = NESTED_EXIT_DONE;
1782                 break;
1783         }
1784         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1785                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1786                 if (svm->nested.intercept_cr_write & cr_bits)
1787                         vmexit = NESTED_EXIT_DONE;
1788                 break;
1789         }
1790         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1791                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1792                 if (svm->nested.intercept_dr_read & dr_bits)
1793                         vmexit = NESTED_EXIT_DONE;
1794                 break;
1795         }
1796         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1797                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1798                 if (svm->nested.intercept_dr_write & dr_bits)
1799                         vmexit = NESTED_EXIT_DONE;
1800                 break;
1801         }
1802         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1803                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1804                 if (svm->nested.intercept_exceptions & excp_bits)
1805                         vmexit = NESTED_EXIT_DONE;
1806                 break;
1807         }
1808         case SVM_EXIT_ERR: {
1809                 vmexit = NESTED_EXIT_DONE;
1810                 break;
1811         }
1812         default: {
1813                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1814                 if (svm->nested.intercept & exit_bits)
1815                         vmexit = NESTED_EXIT_DONE;
1816         }
1817         }
1818
1819         return vmexit;
1820 }
1821
1822 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1823 {
1824         int vmexit;
1825
1826         vmexit = nested_svm_intercept(svm);
1827
1828         if (vmexit == NESTED_EXIT_DONE)
1829                 nested_svm_vmexit(svm);
1830
1831         return vmexit;
1832 }
1833
1834 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1835 {
1836         struct vmcb_control_area *dst  = &dst_vmcb->control;
1837         struct vmcb_control_area *from = &from_vmcb->control;
1838
1839         dst->intercept_cr_read    = from->intercept_cr_read;
1840         dst->intercept_cr_write   = from->intercept_cr_write;
1841         dst->intercept_dr_read    = from->intercept_dr_read;
1842         dst->intercept_dr_write   = from->intercept_dr_write;
1843         dst->intercept_exceptions = from->intercept_exceptions;
1844         dst->intercept            = from->intercept;
1845         dst->iopm_base_pa         = from->iopm_base_pa;
1846         dst->msrpm_base_pa        = from->msrpm_base_pa;
1847         dst->tsc_offset           = from->tsc_offset;
1848         dst->asid                 = from->asid;
1849         dst->tlb_ctl              = from->tlb_ctl;
1850         dst->int_ctl              = from->int_ctl;
1851         dst->int_vector           = from->int_vector;
1852         dst->int_state            = from->int_state;
1853         dst->exit_code            = from->exit_code;
1854         dst->exit_code_hi         = from->exit_code_hi;
1855         dst->exit_info_1          = from->exit_info_1;
1856         dst->exit_info_2          = from->exit_info_2;
1857         dst->exit_int_info        = from->exit_int_info;
1858         dst->exit_int_info_err    = from->exit_int_info_err;
1859         dst->nested_ctl           = from->nested_ctl;
1860         dst->event_inj            = from->event_inj;
1861         dst->event_inj_err        = from->event_inj_err;
1862         dst->nested_cr3           = from->nested_cr3;
1863         dst->lbr_ctl              = from->lbr_ctl;
1864 }
1865
1866 static int nested_svm_vmexit(struct vcpu_svm *svm)
1867 {
1868         struct vmcb *nested_vmcb;
1869         struct vmcb *hsave = svm->nested.hsave;
1870         struct vmcb *vmcb = svm->vmcb;
1871         struct page *page;
1872
1873         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1874                                        vmcb->control.exit_info_1,
1875                                        vmcb->control.exit_info_2,
1876                                        vmcb->control.exit_int_info,
1877                                        vmcb->control.exit_int_info_err);
1878
1879         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1880         if (!nested_vmcb)
1881                 return 1;
1882
1883         /* Exit nested SVM mode */
1884         svm->nested.vmcb = 0;
1885
1886         /* Give the current vmcb to the guest */
1887         disable_gif(svm);
1888
1889         nested_vmcb->save.es     = vmcb->save.es;
1890         nested_vmcb->save.cs     = vmcb->save.cs;
1891         nested_vmcb->save.ss     = vmcb->save.ss;
1892         nested_vmcb->save.ds     = vmcb->save.ds;
1893         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1894         nested_vmcb->save.idtr   = vmcb->save.idtr;
1895         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1896         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1897         nested_vmcb->save.cr2    = vmcb->save.cr2;
1898         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1899         nested_vmcb->save.rflags = vmcb->save.rflags;
1900         nested_vmcb->save.rip    = vmcb->save.rip;
1901         nested_vmcb->save.rsp    = vmcb->save.rsp;
1902         nested_vmcb->save.rax    = vmcb->save.rax;
1903         nested_vmcb->save.dr7    = vmcb->save.dr7;
1904         nested_vmcb->save.dr6    = vmcb->save.dr6;
1905         nested_vmcb->save.cpl    = vmcb->save.cpl;
1906
1907         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1908         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1909         nested_vmcb->control.int_state         = vmcb->control.int_state;
1910         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1911         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1912         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1913         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1914         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1915         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1916
1917         /*
1918          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1919          * to make sure that we do not lose injected events. So check event_inj
1920          * here and copy it to exit_int_info if it is valid.
1921          * Exit_int_info and event_inj can't be both valid because the case
1922          * below only happens on a VMRUN instruction intercept which has
1923          * no valid exit_int_info set.
1924          */
1925         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1926                 struct vmcb_control_area *nc = &nested_vmcb->control;
1927
1928                 nc->exit_int_info     = vmcb->control.event_inj;
1929                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1930         }
1931
1932         nested_vmcb->control.tlb_ctl           = 0;
1933         nested_vmcb->control.event_inj         = 0;
1934         nested_vmcb->control.event_inj_err     = 0;
1935
1936         /* We always set V_INTR_MASKING and remember the old value in hflags */
1937         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1938                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1939
1940         /* Restore the original control entries */
1941         copy_vmcb_control_area(vmcb, hsave);
1942
1943         kvm_clear_exception_queue(&svm->vcpu);
1944         kvm_clear_interrupt_queue(&svm->vcpu);
1945
1946         /* Restore selected save entries */
1947         svm->vmcb->save.es = hsave->save.es;
1948         svm->vmcb->save.cs = hsave->save.cs;
1949         svm->vmcb->save.ss = hsave->save.ss;
1950         svm->vmcb->save.ds = hsave->save.ds;
1951         svm->vmcb->save.gdtr = hsave->save.gdtr;
1952         svm->vmcb->save.idtr = hsave->save.idtr;
1953         svm->vmcb->save.rflags = hsave->save.rflags;
1954         svm_set_efer(&svm->vcpu, hsave->save.efer);
1955         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1956         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1957         if (npt_enabled) {
1958                 svm->vmcb->save.cr3 = hsave->save.cr3;
1959                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1960         } else {
1961                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1962         }
1963         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1964         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1965         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1966         svm->vmcb->save.dr7 = 0;
1967         svm->vmcb->save.cpl = 0;
1968         svm->vmcb->control.exit_int_info = 0;
1969
1970         nested_svm_unmap(page);
1971
1972         kvm_mmu_reset_context(&svm->vcpu);
1973         kvm_mmu_load(&svm->vcpu);
1974
1975         return 0;
1976 }
1977
1978 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1979 {
1980         /*
1981          * This function merges the msr permission bitmaps of kvm and the
1982          * nested vmcb. It is omptimized in that it only merges the parts where
1983          * the kvm msr permission bitmap may contain zero bits
1984          */
1985         int i;
1986
1987         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1988                 return true;
1989
1990         for (i = 0; i < MSRPM_OFFSETS; i++) {
1991                 u32 value, p;
1992                 u64 offset;
1993
1994                 if (msrpm_offsets[i] == 0xffffffff)
1995                         break;
1996
1997                 p      = msrpm_offsets[i];
1998                 offset = svm->nested.vmcb_msrpm + (p * 4);
1999
2000                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2001                         return false;
2002
2003                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2004         }
2005
2006         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2007
2008         return true;
2009 }
2010
2011 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2012 {
2013         struct vmcb *nested_vmcb;
2014         struct vmcb *hsave = svm->nested.hsave;
2015         struct vmcb *vmcb = svm->vmcb;
2016         struct page *page;
2017         u64 vmcb_gpa;
2018
2019         vmcb_gpa = svm->vmcb->save.rax;
2020
2021         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2022         if (!nested_vmcb)
2023                 return false;
2024
2025         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
2026                                nested_vmcb->save.rip,
2027                                nested_vmcb->control.int_ctl,
2028                                nested_vmcb->control.event_inj,
2029                                nested_vmcb->control.nested_ctl);
2030
2031         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2032                                     nested_vmcb->control.intercept_cr_write,
2033                                     nested_vmcb->control.intercept_exceptions,
2034                                     nested_vmcb->control.intercept);
2035
2036         /* Clear internal status */
2037         kvm_clear_exception_queue(&svm->vcpu);
2038         kvm_clear_interrupt_queue(&svm->vcpu);
2039
2040         /*
2041          * Save the old vmcb, so we don't need to pick what we save, but can
2042          * restore everything when a VMEXIT occurs
2043          */
2044         hsave->save.es     = vmcb->save.es;
2045         hsave->save.cs     = vmcb->save.cs;
2046         hsave->save.ss     = vmcb->save.ss;
2047         hsave->save.ds     = vmcb->save.ds;
2048         hsave->save.gdtr   = vmcb->save.gdtr;
2049         hsave->save.idtr   = vmcb->save.idtr;
2050         hsave->save.efer   = svm->vcpu.arch.efer;
2051         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2052         hsave->save.cr4    = svm->vcpu.arch.cr4;
2053         hsave->save.rflags = vmcb->save.rflags;
2054         hsave->save.rip    = svm->next_rip;
2055         hsave->save.rsp    = vmcb->save.rsp;
2056         hsave->save.rax    = vmcb->save.rax;
2057         if (npt_enabled)
2058                 hsave->save.cr3    = vmcb->save.cr3;
2059         else
2060                 hsave->save.cr3    = svm->vcpu.arch.cr3;
2061
2062         copy_vmcb_control_area(hsave, vmcb);
2063
2064         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2065                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2066         else
2067                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2068
2069         /* Load the nested guest state */
2070         svm->vmcb->save.es = nested_vmcb->save.es;
2071         svm->vmcb->save.cs = nested_vmcb->save.cs;
2072         svm->vmcb->save.ss = nested_vmcb->save.ss;
2073         svm->vmcb->save.ds = nested_vmcb->save.ds;
2074         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2075         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2076         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2077         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2078         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2079         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2080         if (npt_enabled) {
2081                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2082                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2083         } else
2084                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2085
2086         /* Guest paging mode is active - reset mmu */
2087         kvm_mmu_reset_context(&svm->vcpu);
2088
2089         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2090         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2091         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2092         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2093
2094         /* In case we don't even reach vcpu_run, the fields are not updated */
2095         svm->vmcb->save.rax = nested_vmcb->save.rax;
2096         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2097         svm->vmcb->save.rip = nested_vmcb->save.rip;
2098         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2099         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2100         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2101
2102         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2103         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2104
2105         /* cache intercepts */
2106         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2107         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2108         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2109         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2110         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2111         svm->nested.intercept            = nested_vmcb->control.intercept;
2112
2113         force_new_asid(&svm->vcpu);
2114         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2115         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2116                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2117         else
2118                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2119
2120         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2121                 /* We only want the cr8 intercept bits of the guest */
2122                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2123                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2124         }
2125
2126         /* We don't want to see VMMCALLs from a nested guest */
2127         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2128
2129         /*
2130          * We don't want a nested guest to be more powerful than the guest, so
2131          * all intercepts are ORed
2132          */
2133         svm->vmcb->control.intercept_cr_read |=
2134                 nested_vmcb->control.intercept_cr_read;
2135         svm->vmcb->control.intercept_cr_write |=
2136                 nested_vmcb->control.intercept_cr_write;
2137         svm->vmcb->control.intercept_dr_read |=
2138                 nested_vmcb->control.intercept_dr_read;
2139         svm->vmcb->control.intercept_dr_write |=
2140                 nested_vmcb->control.intercept_dr_write;
2141         svm->vmcb->control.intercept_exceptions |=
2142                 nested_vmcb->control.intercept_exceptions;
2143
2144         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2145
2146         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2147         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2148         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2149         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2150         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2151         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2152
2153         nested_svm_unmap(page);
2154
2155         /* nested_vmcb is our indicator if nested SVM is activated */
2156         svm->nested.vmcb = vmcb_gpa;
2157
2158         enable_gif(svm);
2159
2160         return true;
2161 }
2162
2163 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2164 {
2165         to_vmcb->save.fs = from_vmcb->save.fs;
2166         to_vmcb->save.gs = from_vmcb->save.gs;
2167         to_vmcb->save.tr = from_vmcb->save.tr;
2168         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2169         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2170         to_vmcb->save.star = from_vmcb->save.star;
2171         to_vmcb->save.lstar = from_vmcb->save.lstar;
2172         to_vmcb->save.cstar = from_vmcb->save.cstar;
2173         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2174         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2175         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2176         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2177 }
2178
2179 static int vmload_interception(struct vcpu_svm *svm)
2180 {
2181         struct vmcb *nested_vmcb;
2182         struct page *page;
2183
2184         if (nested_svm_check_permissions(svm))
2185                 return 1;
2186
2187         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2188         skip_emulated_instruction(&svm->vcpu);
2189
2190         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2191         if (!nested_vmcb)
2192                 return 1;
2193
2194         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2195         nested_svm_unmap(page);
2196
2197         return 1;
2198 }
2199
2200 static int vmsave_interception(struct vcpu_svm *svm)
2201 {
2202         struct vmcb *nested_vmcb;
2203         struct page *page;
2204
2205         if (nested_svm_check_permissions(svm))
2206                 return 1;
2207
2208         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2209         skip_emulated_instruction(&svm->vcpu);
2210
2211         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2212         if (!nested_vmcb)
2213                 return 1;
2214
2215         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2216         nested_svm_unmap(page);
2217
2218         return 1;
2219 }
2220
2221 static int vmrun_interception(struct vcpu_svm *svm)
2222 {
2223         if (nested_svm_check_permissions(svm))
2224                 return 1;
2225
2226         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2227         skip_emulated_instruction(&svm->vcpu);
2228
2229         if (!nested_svm_vmrun(svm))
2230                 return 1;
2231
2232         if (!nested_svm_vmrun_msrpm(svm))
2233                 goto failed;
2234
2235         return 1;
2236
2237 failed:
2238
2239         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2240         svm->vmcb->control.exit_code_hi = 0;
2241         svm->vmcb->control.exit_info_1  = 0;
2242         svm->vmcb->control.exit_info_2  = 0;
2243
2244         nested_svm_vmexit(svm);
2245
2246         return 1;
2247 }
2248
2249 static int stgi_interception(struct vcpu_svm *svm)
2250 {
2251         if (nested_svm_check_permissions(svm))
2252                 return 1;
2253
2254         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2255         skip_emulated_instruction(&svm->vcpu);
2256
2257         enable_gif(svm);
2258
2259         return 1;
2260 }
2261
2262 static int clgi_interception(struct vcpu_svm *svm)
2263 {
2264         if (nested_svm_check_permissions(svm))
2265                 return 1;
2266
2267         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2268         skip_emulated_instruction(&svm->vcpu);
2269
2270         disable_gif(svm);
2271
2272         /* After a CLGI no interrupts should come */
2273         svm_clear_vintr(svm);
2274         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2275
2276         return 1;
2277 }
2278
2279 static int invlpga_interception(struct vcpu_svm *svm)
2280 {
2281         struct kvm_vcpu *vcpu = &svm->vcpu;
2282
2283         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2284                           vcpu->arch.regs[VCPU_REGS_RAX]);
2285
2286         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2287         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2288
2289         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2290         skip_emulated_instruction(&svm->vcpu);
2291         return 1;
2292 }
2293
2294 static int skinit_interception(struct vcpu_svm *svm)
2295 {
2296         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2297
2298         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2299         return 1;
2300 }
2301
2302 static int invalid_op_interception(struct vcpu_svm *svm)
2303 {
2304         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2305         return 1;
2306 }
2307
2308 static int task_switch_interception(struct vcpu_svm *svm)
2309 {
2310         u16 tss_selector;
2311         int reason;
2312         int int_type = svm->vmcb->control.exit_int_info &
2313                 SVM_EXITINTINFO_TYPE_MASK;
2314         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2315         uint32_t type =
2316                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2317         uint32_t idt_v =
2318                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2319         bool has_error_code = false;
2320         u32 error_code = 0;
2321
2322         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2323
2324         if (svm->vmcb->control.exit_info_2 &
2325             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2326                 reason = TASK_SWITCH_IRET;
2327         else if (svm->vmcb->control.exit_info_2 &
2328                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2329                 reason = TASK_SWITCH_JMP;
2330         else if (idt_v)
2331                 reason = TASK_SWITCH_GATE;
2332         else
2333                 reason = TASK_SWITCH_CALL;
2334
2335         if (reason == TASK_SWITCH_GATE) {
2336                 switch (type) {
2337                 case SVM_EXITINTINFO_TYPE_NMI:
2338                         svm->vcpu.arch.nmi_injected = false;
2339                         break;
2340                 case SVM_EXITINTINFO_TYPE_EXEPT:
2341                         if (svm->vmcb->control.exit_info_2 &
2342                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2343                                 has_error_code = true;
2344                                 error_code =
2345                                         (u32)svm->vmcb->control.exit_info_2;
2346                         }
2347                         kvm_clear_exception_queue(&svm->vcpu);
2348                         break;
2349                 case SVM_EXITINTINFO_TYPE_INTR:
2350                         kvm_clear_interrupt_queue(&svm->vcpu);
2351                         break;
2352                 default:
2353                         break;
2354                 }
2355         }
2356
2357         if (reason != TASK_SWITCH_GATE ||
2358             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2359             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2360              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2361                 skip_emulated_instruction(&svm->vcpu);
2362
2363         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2364                                 has_error_code, error_code) == EMULATE_FAIL) {
2365                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2366                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2367                 svm->vcpu.run->internal.ndata = 0;
2368                 return 0;
2369         }
2370         return 1;
2371 }
2372
2373 static int cpuid_interception(struct vcpu_svm *svm)
2374 {
2375         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2376         kvm_emulate_cpuid(&svm->vcpu);
2377         return 1;
2378 }
2379
2380 static int iret_interception(struct vcpu_svm *svm)
2381 {
2382         ++svm->vcpu.stat.nmi_window_exits;
2383         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2384         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2385         return 1;
2386 }
2387
2388 static int invlpg_interception(struct vcpu_svm *svm)
2389 {
2390         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2391 }
2392
2393 static int emulate_on_interception(struct vcpu_svm *svm)
2394 {
2395         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2396 }
2397
2398 static int cr8_write_interception(struct vcpu_svm *svm)
2399 {
2400         struct kvm_run *kvm_run = svm->vcpu.run;
2401
2402         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2403         /* instruction emulation calls kvm_set_cr8() */
2404         emulate_instruction(&svm->vcpu, 0, 0, 0);
2405         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2406                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2407                 return 1;
2408         }
2409         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2410                 return 1;
2411         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2412         return 0;
2413 }
2414
2415 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2416 {
2417         struct vcpu_svm *svm = to_svm(vcpu);
2418
2419         switch (ecx) {
2420         case MSR_IA32_TSC: {
2421                 u64 tsc_offset;
2422
2423                 if (is_nested(svm))
2424                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2425                 else
2426                         tsc_offset = svm->vmcb->control.tsc_offset;
2427
2428                 *data = tsc_offset + native_read_tsc();
2429                 break;
2430         }
2431         case MSR_K6_STAR:
2432                 *data = svm->vmcb->save.star;
2433                 break;
2434 #ifdef CONFIG_X86_64
2435         case MSR_LSTAR:
2436                 *data = svm->vmcb->save.lstar;
2437                 break;
2438         case MSR_CSTAR:
2439                 *data = svm->vmcb->save.cstar;
2440                 break;
2441         case MSR_KERNEL_GS_BASE:
2442                 *data = svm->vmcb->save.kernel_gs_base;
2443                 break;
2444         case MSR_SYSCALL_MASK:
2445                 *data = svm->vmcb->save.sfmask;
2446                 break;
2447 #endif
2448         case MSR_IA32_SYSENTER_CS:
2449                 *data = svm->vmcb->save.sysenter_cs;
2450                 break;
2451         case MSR_IA32_SYSENTER_EIP:
2452                 *data = svm->sysenter_eip;
2453                 break;
2454         case MSR_IA32_SYSENTER_ESP:
2455                 *data = svm->sysenter_esp;
2456                 break;
2457         /*
2458          * Nobody will change the following 5 values in the VMCB so we can
2459          * safely return them on rdmsr. They will always be 0 until LBRV is
2460          * implemented.
2461          */
2462         case MSR_IA32_DEBUGCTLMSR:
2463                 *data = svm->vmcb->save.dbgctl;
2464                 break;
2465         case MSR_IA32_LASTBRANCHFROMIP:
2466                 *data = svm->vmcb->save.br_from;
2467                 break;
2468         case MSR_IA32_LASTBRANCHTOIP:
2469                 *data = svm->vmcb->save.br_to;
2470                 break;
2471         case MSR_IA32_LASTINTFROMIP:
2472                 *data = svm->vmcb->save.last_excp_from;
2473                 break;
2474         case MSR_IA32_LASTINTTOIP:
2475                 *data = svm->vmcb->save.last_excp_to;
2476                 break;
2477         case MSR_VM_HSAVE_PA:
2478                 *data = svm->nested.hsave_msr;
2479                 break;
2480         case MSR_VM_CR:
2481                 *data = svm->nested.vm_cr_msr;
2482                 break;
2483         case MSR_IA32_UCODE_REV:
2484                 *data = 0x01000065;
2485                 break;
2486         default:
2487                 return kvm_get_msr_common(vcpu, ecx, data);
2488         }
2489         return 0;
2490 }
2491
2492 static int rdmsr_interception(struct vcpu_svm *svm)
2493 {
2494         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2495         u64 data;
2496
2497         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2498                 trace_kvm_msr_read_ex(ecx);
2499                 kvm_inject_gp(&svm->vcpu, 0);
2500         } else {
2501                 trace_kvm_msr_read(ecx, data);
2502
2503                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2504                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2505                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2506                 skip_emulated_instruction(&svm->vcpu);
2507         }
2508         return 1;
2509 }
2510
2511 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2512 {
2513         struct vcpu_svm *svm = to_svm(vcpu);
2514         int svm_dis, chg_mask;
2515
2516         if (data & ~SVM_VM_CR_VALID_MASK)
2517                 return 1;
2518
2519         chg_mask = SVM_VM_CR_VALID_MASK;
2520
2521         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2522                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2523
2524         svm->nested.vm_cr_msr &= ~chg_mask;
2525         svm->nested.vm_cr_msr |= (data & chg_mask);
2526
2527         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2528
2529         /* check for svm_disable while efer.svme is set */
2530         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2531                 return 1;
2532
2533         return 0;
2534 }
2535
2536 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2537 {
2538         struct vcpu_svm *svm = to_svm(vcpu);
2539
2540         switch (ecx) {
2541         case MSR_IA32_TSC: {
2542                 u64 tsc_offset = data - native_read_tsc();
2543                 u64 g_tsc_offset = 0;
2544
2545                 if (is_nested(svm)) {
2546                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2547                                        svm->nested.hsave->control.tsc_offset;
2548                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2549                 }
2550
2551                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2552
2553                 break;
2554         }
2555         case MSR_K6_STAR:
2556                 svm->vmcb->save.star = data;
2557                 break;
2558 #ifdef CONFIG_X86_64
2559         case MSR_LSTAR:
2560                 svm->vmcb->save.lstar = data;
2561                 break;
2562         case MSR_CSTAR:
2563                 svm->vmcb->save.cstar = data;
2564                 break;
2565         case MSR_KERNEL_GS_BASE:
2566                 svm->vmcb->save.kernel_gs_base = data;
2567                 break;
2568         case MSR_SYSCALL_MASK:
2569                 svm->vmcb->save.sfmask = data;
2570                 break;
2571 #endif
2572         case MSR_IA32_SYSENTER_CS:
2573                 svm->vmcb->save.sysenter_cs = data;
2574                 break;
2575         case MSR_IA32_SYSENTER_EIP:
2576                 svm->sysenter_eip = data;
2577                 svm->vmcb->save.sysenter_eip = data;
2578                 break;
2579         case MSR_IA32_SYSENTER_ESP:
2580                 svm->sysenter_esp = data;
2581                 svm->vmcb->save.sysenter_esp = data;
2582                 break;
2583         case MSR_IA32_DEBUGCTLMSR:
2584                 if (!svm_has(SVM_FEATURE_LBRV)) {
2585                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2586                                         __func__, data);
2587                         break;
2588                 }
2589                 if (data & DEBUGCTL_RESERVED_BITS)
2590                         return 1;
2591
2592                 svm->vmcb->save.dbgctl = data;
2593                 if (data & (1ULL<<0))
2594                         svm_enable_lbrv(svm);
2595                 else
2596                         svm_disable_lbrv(svm);
2597                 break;
2598         case MSR_VM_HSAVE_PA:
2599                 svm->nested.hsave_msr = data;
2600                 break;
2601         case MSR_VM_CR:
2602                 return svm_set_vm_cr(vcpu, data);
2603         case MSR_VM_IGNNE:
2604                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2605                 break;
2606         default:
2607                 return kvm_set_msr_common(vcpu, ecx, data);
2608         }
2609         return 0;
2610 }
2611
2612 static int wrmsr_interception(struct vcpu_svm *svm)
2613 {
2614         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2615         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2616                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2617
2618
2619         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2620         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2621                 trace_kvm_msr_write_ex(ecx, data);
2622                 kvm_inject_gp(&svm->vcpu, 0);
2623         } else {
2624                 trace_kvm_msr_write(ecx, data);
2625                 skip_emulated_instruction(&svm->vcpu);
2626         }
2627         return 1;
2628 }
2629
2630 static int msr_interception(struct vcpu_svm *svm)
2631 {
2632         if (svm->vmcb->control.exit_info_1)
2633                 return wrmsr_interception(svm);
2634         else
2635                 return rdmsr_interception(svm);
2636 }
2637
2638 static int interrupt_window_interception(struct vcpu_svm *svm)
2639 {
2640         struct kvm_run *kvm_run = svm->vcpu.run;
2641
2642         svm_clear_vintr(svm);
2643         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2644         /*
2645          * If the user space waits to inject interrupts, exit as soon as
2646          * possible
2647          */
2648         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2649             kvm_run->request_interrupt_window &&
2650             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2651                 ++svm->vcpu.stat.irq_window_exits;
2652                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2653                 return 0;
2654         }
2655
2656         return 1;
2657 }
2658
2659 static int pause_interception(struct vcpu_svm *svm)
2660 {
2661         kvm_vcpu_on_spin(&(svm->vcpu));
2662         return 1;
2663 }
2664
2665 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2666         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2667         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2668         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2669         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2670         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2671         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2672         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2673         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2674         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2675         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2676         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2677         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2678         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2679         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2680         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2681         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2682         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2683         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2684         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2685         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2686         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2687         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2688         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2689         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2690         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2691         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2692         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2693         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2694         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2695         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2696         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2697         [SVM_EXIT_INTR]                         = intr_interception,
2698         [SVM_EXIT_NMI]                          = nmi_interception,
2699         [SVM_EXIT_SMI]                          = nop_on_interception,
2700         [SVM_EXIT_INIT]                         = nop_on_interception,
2701         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2702         [SVM_EXIT_CPUID]                        = cpuid_interception,
2703         [SVM_EXIT_IRET]                         = iret_interception,
2704         [SVM_EXIT_INVD]                         = emulate_on_interception,
2705         [SVM_EXIT_PAUSE]                        = pause_interception,
2706         [SVM_EXIT_HLT]                          = halt_interception,
2707         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2708         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2709         [SVM_EXIT_IOIO]                         = io_interception,
2710         [SVM_EXIT_MSR]                          = msr_interception,
2711         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2712         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2713         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2714         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2715         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2716         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2717         [SVM_EXIT_STGI]                         = stgi_interception,
2718         [SVM_EXIT_CLGI]                         = clgi_interception,
2719         [SVM_EXIT_SKINIT]                       = skinit_interception,
2720         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2721         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2722         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2723         [SVM_EXIT_NPF]                          = pf_interception,
2724 };
2725
2726 void dump_vmcb(struct kvm_vcpu *vcpu)
2727 {
2728         struct vcpu_svm *svm = to_svm(vcpu);
2729         struct vmcb_control_area *control = &svm->vmcb->control;
2730         struct vmcb_save_area *save = &svm->vmcb->save;
2731
2732         pr_err("VMCB Control Area:\n");
2733         pr_err("cr_read:            %04x\n", control->intercept_cr_read);
2734         pr_err("cr_write:           %04x\n", control->intercept_cr_write);
2735         pr_err("dr_read:            %04x\n", control->intercept_dr_read);
2736         pr_err("dr_write:           %04x\n", control->intercept_dr_write);
2737         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
2738         pr_err("intercepts:         %016llx\n", control->intercept);
2739         pr_err("pause filter count: %d\n", control->pause_filter_count);
2740         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
2741         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
2742         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
2743         pr_err("asid:               %d\n", control->asid);
2744         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
2745         pr_err("int_ctl:            %08x\n", control->int_ctl);
2746         pr_err("int_vector:         %08x\n", control->int_vector);
2747         pr_err("int_state:          %08x\n", control->int_state);
2748         pr_err("exit_code:          %08x\n", control->exit_code);
2749         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
2750         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
2751         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
2752         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
2753         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
2754         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
2755         pr_err("event_inj:          %08x\n", control->event_inj);
2756         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
2757         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
2758         pr_err("next_rip:           %016llx\n", control->next_rip);
2759         pr_err("VMCB State Save Area:\n");
2760         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
2761                 save->es.selector, save->es.attrib,
2762                 save->es.limit, save->es.base);
2763         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
2764                 save->cs.selector, save->cs.attrib,
2765                 save->cs.limit, save->cs.base);
2766         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
2767                 save->ss.selector, save->ss.attrib,
2768                 save->ss.limit, save->ss.base);
2769         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
2770                 save->ds.selector, save->ds.attrib,
2771                 save->ds.limit, save->ds.base);
2772         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
2773                 save->fs.selector, save->fs.attrib,
2774                 save->fs.limit, save->fs.base);
2775         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
2776                 save->gs.selector, save->gs.attrib,
2777                 save->gs.limit, save->gs.base);
2778         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2779                 save->gdtr.selector, save->gdtr.attrib,
2780                 save->gdtr.limit, save->gdtr.base);
2781         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2782                 save->ldtr.selector, save->ldtr.attrib,
2783                 save->ldtr.limit, save->ldtr.base);
2784         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2785                 save->idtr.selector, save->idtr.attrib,
2786                 save->idtr.limit, save->idtr.base);
2787         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
2788                 save->tr.selector, save->tr.attrib,
2789                 save->tr.limit, save->tr.base);
2790         pr_err("cpl:            %d                efer:         %016llx\n",
2791                 save->cpl, save->efer);
2792         pr_err("cr0:            %016llx cr2:          %016llx\n",
2793                 save->cr0, save->cr2);
2794         pr_err("cr3:            %016llx cr4:          %016llx\n",
2795                 save->cr3, save->cr4);
2796         pr_err("dr6:            %016llx dr7:          %016llx\n",
2797                 save->dr6, save->dr7);
2798         pr_err("rip:            %016llx rflags:       %016llx\n",
2799                 save->rip, save->rflags);
2800         pr_err("rsp:            %016llx rax:          %016llx\n",
2801                 save->rsp, save->rax);
2802         pr_err("star:           %016llx lstar:        %016llx\n",
2803                 save->star, save->lstar);
2804         pr_err("cstar:          %016llx sfmask:       %016llx\n",
2805                 save->cstar, save->sfmask);
2806         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
2807                 save->kernel_gs_base, save->sysenter_cs);
2808         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
2809                 save->sysenter_esp, save->sysenter_eip);
2810         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
2811                 save->g_pat, save->dbgctl);
2812         pr_err("br_from:        %016llx br_to:        %016llx\n",
2813                 save->br_from, save->br_to);
2814         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
2815                 save->last_excp_from, save->last_excp_to);
2816
2817 }
2818
2819 static int handle_exit(struct kvm_vcpu *vcpu)
2820 {
2821         struct vcpu_svm *svm = to_svm(vcpu);
2822         struct kvm_run *kvm_run = vcpu->run;
2823         u32 exit_code = svm->vmcb->control.exit_code;
2824
2825         trace_kvm_exit(exit_code, vcpu);
2826
2827         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2828                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2829         if (npt_enabled)
2830                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2831
2832         if (unlikely(svm->nested.exit_required)) {
2833                 nested_svm_vmexit(svm);
2834                 svm->nested.exit_required = false;
2835
2836                 return 1;
2837         }
2838
2839         if (is_nested(svm)) {
2840                 int vmexit;
2841
2842                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2843                                         svm->vmcb->control.exit_info_1,
2844                                         svm->vmcb->control.exit_info_2,
2845                                         svm->vmcb->control.exit_int_info,
2846                                         svm->vmcb->control.exit_int_info_err);
2847
2848                 vmexit = nested_svm_exit_special(svm);
2849
2850                 if (vmexit == NESTED_EXIT_CONTINUE)
2851                         vmexit = nested_svm_exit_handled(svm);
2852
2853                 if (vmexit == NESTED_EXIT_DONE)
2854                         return 1;
2855         }
2856
2857         svm_complete_interrupts(svm);
2858
2859         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2860                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2861                 kvm_run->fail_entry.hardware_entry_failure_reason
2862                         = svm->vmcb->control.exit_code;
2863                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2864                 dump_vmcb(vcpu);
2865                 return 0;
2866         }
2867
2868         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2869             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2870             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2871                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2872                        "exit_code 0x%x\n",
2873                        __func__, svm->vmcb->control.exit_int_info,
2874                        exit_code);
2875
2876         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2877             || !svm_exit_handlers[exit_code]) {
2878                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2879                 kvm_run->hw.hardware_exit_reason = exit_code;
2880                 return 0;
2881         }
2882
2883         return svm_exit_handlers[exit_code](svm);
2884 }
2885
2886 static void reload_tss(struct kvm_vcpu *vcpu)
2887 {
2888         int cpu = raw_smp_processor_id();
2889
2890         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2891         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2892         load_TR_desc();
2893 }
2894
2895 static void pre_svm_run(struct vcpu_svm *svm)
2896 {
2897         int cpu = raw_smp_processor_id();
2898
2899         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2900
2901         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2902         /* FIXME: handle wraparound of asid_generation */
2903         if (svm->asid_generation != sd->asid_generation)
2904                 new_asid(svm, sd);
2905 }
2906
2907 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2908 {
2909         struct vcpu_svm *svm = to_svm(vcpu);
2910
2911         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2912         vcpu->arch.hflags |= HF_NMI_MASK;
2913         svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2914         ++vcpu->stat.nmi_injections;
2915 }
2916
2917 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2918 {
2919         struct vmcb_control_area *control;
2920
2921         control = &svm->vmcb->control;
2922         control->int_vector = irq;
2923         control->int_ctl &= ~V_INTR_PRIO_MASK;
2924         control->int_ctl |= V_IRQ_MASK |
2925                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2926 }
2927
2928 static void svm_set_irq(struct kvm_vcpu *vcpu)
2929 {
2930         struct vcpu_svm *svm = to_svm(vcpu);
2931
2932         BUG_ON(!(gif_set(svm)));
2933
2934         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
2935         ++vcpu->stat.irq_injections;
2936
2937         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2938                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2939 }
2940
2941 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2942 {
2943         struct vcpu_svm *svm = to_svm(vcpu);
2944
2945         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2946                 return;
2947
2948         if (irr == -1)
2949                 return;
2950
2951         if (tpr >= irr)
2952                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2953 }
2954
2955 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2956 {
2957         struct vcpu_svm *svm = to_svm(vcpu);
2958         struct vmcb *vmcb = svm->vmcb;
2959         int ret;
2960         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2961               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2962         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2963
2964         return ret;
2965 }
2966
2967 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2968 {
2969         struct vcpu_svm *svm = to_svm(vcpu);
2970
2971         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2972 }
2973
2974 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2975 {
2976         struct vcpu_svm *svm = to_svm(vcpu);
2977
2978         if (masked) {
2979                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2980                 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2981         } else {
2982                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2983                 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2984         }
2985 }
2986
2987 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2988 {
2989         struct vcpu_svm *svm = to_svm(vcpu);
2990         struct vmcb *vmcb = svm->vmcb;
2991         int ret;
2992
2993         if (!gif_set(svm) ||
2994              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2995                 return 0;
2996
2997         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2998
2999         if (is_nested(svm))
3000                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3001
3002         return ret;
3003 }
3004
3005 static void enable_irq_window(struct kvm_vcpu *vcpu)
3006 {
3007         struct vcpu_svm *svm = to_svm(vcpu);
3008
3009         /*
3010          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3011          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3012          * get that intercept, this function will be called again though and
3013          * we'll get the vintr intercept.
3014          */
3015         if (gif_set(svm) && nested_svm_intr(svm)) {
3016                 svm_set_vintr(svm);
3017                 svm_inject_irq(svm, 0x0);
3018         }
3019 }
3020
3021 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3022 {
3023         struct vcpu_svm *svm = to_svm(vcpu);
3024
3025         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3026             == HF_NMI_MASK)
3027                 return; /* IRET will cause a vm exit */
3028
3029         /*
3030          * Something prevents NMI from been injected. Single step over possible
3031          * problem (IRET or exception injection or interrupt shadow)
3032          */
3033         svm->nmi_singlestep = true;
3034         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3035         update_db_intercept(vcpu);
3036 }
3037
3038 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3039 {
3040         return 0;
3041 }
3042
3043 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3044 {
3045         force_new_asid(vcpu);
3046 }
3047
3048 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3049 {
3050 }
3051
3052 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3053 {
3054         struct vcpu_svm *svm = to_svm(vcpu);
3055
3056         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3057                 return;
3058
3059         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3060                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3061                 kvm_set_cr8(vcpu, cr8);
3062         }
3063 }
3064
3065 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3066 {
3067         struct vcpu_svm *svm = to_svm(vcpu);
3068         u64 cr8;
3069
3070         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3071                 return;
3072
3073         cr8 = kvm_get_cr8(vcpu);
3074         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3075         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3076 }
3077
3078 static void svm_complete_interrupts(struct vcpu_svm *svm)
3079 {
3080         u8 vector;
3081         int type;
3082         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3083         unsigned int3_injected = svm->int3_injected;
3084
3085         svm->int3_injected = 0;
3086
3087         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3088                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3089
3090         svm->vcpu.arch.nmi_injected = false;
3091         kvm_clear_exception_queue(&svm->vcpu);
3092         kvm_clear_interrupt_queue(&svm->vcpu);
3093
3094         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3095                 return;
3096
3097         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3098         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3099
3100         switch (type) {
3101         case SVM_EXITINTINFO_TYPE_NMI:
3102                 svm->vcpu.arch.nmi_injected = true;
3103                 break;
3104         case SVM_EXITINTINFO_TYPE_EXEPT:
3105                 /*
3106                  * In case of software exceptions, do not reinject the vector,
3107                  * but re-execute the instruction instead. Rewind RIP first
3108                  * if we emulated INT3 before.
3109                  */
3110                 if (kvm_exception_is_soft(vector)) {
3111                         if (vector == BP_VECTOR && int3_injected &&
3112                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3113                                 kvm_rip_write(&svm->vcpu,
3114                                               kvm_rip_read(&svm->vcpu) -
3115                                               int3_injected);
3116                         break;
3117                 }
3118                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3119                         u32 err = svm->vmcb->control.exit_int_info_err;
3120                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3121
3122                 } else
3123                         kvm_requeue_exception(&svm->vcpu, vector);
3124                 break;
3125         case SVM_EXITINTINFO_TYPE_INTR:
3126                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3127                 break;
3128         default:
3129                 break;
3130         }
3131 }
3132
3133 #ifdef CONFIG_X86_64
3134 #define R "r"
3135 #else
3136 #define R "e"
3137 #endif
3138
3139 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3140 {
3141         struct vcpu_svm *svm = to_svm(vcpu);
3142         u16 fs_selector;
3143         u16 gs_selector;
3144         u16 ldt_selector;
3145
3146         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3147         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3148         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3149
3150         /*
3151          * A vmexit emulation is required before the vcpu can be executed
3152          * again.
3153          */
3154         if (unlikely(svm->nested.exit_required))
3155                 return;
3156
3157         pre_svm_run(svm);
3158
3159         sync_lapic_to_cr8(vcpu);
3160
3161         save_host_msrs(vcpu);
3162         fs_selector = kvm_read_fs();
3163         gs_selector = kvm_read_gs();
3164         ldt_selector = kvm_read_ldt();
3165         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3166         /* required for live migration with NPT */
3167         if (npt_enabled)
3168                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3169
3170         clgi();
3171
3172         local_irq_enable();
3173
3174         asm volatile (
3175                 "push %%"R"bp; \n\t"
3176                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3177                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3178                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3179                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3180                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3181                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3182 #ifdef CONFIG_X86_64
3183                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3184                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3185                 "mov %c[r10](%[svm]), %%r10 \n\t"
3186                 "mov %c[r11](%[svm]), %%r11 \n\t"
3187                 "mov %c[r12](%[svm]), %%r12 \n\t"
3188                 "mov %c[r13](%[svm]), %%r13 \n\t"
3189                 "mov %c[r14](%[svm]), %%r14 \n\t"
3190                 "mov %c[r15](%[svm]), %%r15 \n\t"
3191 #endif
3192
3193                 /* Enter guest mode */
3194                 "push %%"R"ax \n\t"
3195                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3196                 __ex(SVM_VMLOAD) "\n\t"
3197                 __ex(SVM_VMRUN) "\n\t"
3198                 __ex(SVM_VMSAVE) "\n\t"
3199                 "pop %%"R"ax \n\t"
3200
3201                 /* Save guest registers, load host registers */
3202                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3203                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3204                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3205                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3206                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3207                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3208 #ifdef CONFIG_X86_64
3209                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3210                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3211                 "mov %%r10, %c[r10](%[svm]) \n\t"
3212                 "mov %%r11, %c[r11](%[svm]) \n\t"
3213                 "mov %%r12, %c[r12](%[svm]) \n\t"
3214                 "mov %%r13, %c[r13](%[svm]) \n\t"
3215                 "mov %%r14, %c[r14](%[svm]) \n\t"
3216                 "mov %%r15, %c[r15](%[svm]) \n\t"
3217 #endif
3218                 "pop %%"R"bp"
3219                 :
3220                 : [svm]"a"(svm),
3221                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3222                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3223                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3224                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3225                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3226                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3227                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3228 #ifdef CONFIG_X86_64
3229                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3230                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3231                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3232                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3233                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3234                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3235                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3236                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3237 #endif
3238                 : "cc", "memory"
3239                 , R"bx", R"cx", R"dx", R"si", R"di"
3240 #ifdef CONFIG_X86_64
3241                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3242 #endif
3243                 );
3244
3245         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3246         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3247         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3248         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3249
3250         kvm_load_fs(fs_selector);
3251         kvm_load_gs(gs_selector);
3252         kvm_load_ldt(ldt_selector);
3253         load_host_msrs(vcpu);
3254
3255         reload_tss(vcpu);
3256
3257         local_irq_disable();
3258
3259         stgi();
3260
3261         sync_cr8_to_lapic(vcpu);
3262
3263         svm->next_rip = 0;
3264
3265         if (npt_enabled) {
3266                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3267                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3268         }
3269
3270         /*
3271          * We need to handle MC intercepts here before the vcpu has a chance to
3272          * change the physical cpu
3273          */
3274         if (unlikely(svm->vmcb->control.exit_code ==
3275                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3276                 svm_handle_mce(svm);
3277 }
3278
3279 #undef R
3280
3281 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3282 {
3283         struct vcpu_svm *svm = to_svm(vcpu);
3284
3285         if (npt_enabled) {
3286                 svm->vmcb->control.nested_cr3 = root;
3287                 force_new_asid(vcpu);
3288                 return;
3289         }
3290
3291         svm->vmcb->save.cr3 = root;
3292         force_new_asid(vcpu);
3293 }
3294
3295 static int is_disabled(void)
3296 {
3297         u64 vm_cr;
3298
3299         rdmsrl(MSR_VM_CR, vm_cr);
3300         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3301                 return 1;
3302
3303         return 0;
3304 }
3305
3306 static void
3307 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3308 {
3309         /*
3310          * Patch in the VMMCALL instruction:
3311          */
3312         hypercall[0] = 0x0f;
3313         hypercall[1] = 0x01;
3314         hypercall[2] = 0xd9;
3315 }
3316
3317 static void svm_check_processor_compat(void *rtn)
3318 {
3319         *(int *)rtn = 0;
3320 }
3321
3322 static bool svm_cpu_has_accelerated_tpr(void)
3323 {
3324         return false;
3325 }
3326
3327 static int get_npt_level(void)
3328 {
3329 #ifdef CONFIG_X86_64
3330         return PT64_ROOT_LEVEL;
3331 #else
3332         return PT32E_ROOT_LEVEL;
3333 #endif
3334 }
3335
3336 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3337 {
3338         return 0;
3339 }
3340
3341 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3342 {
3343 }
3344
3345 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3346 {
3347         switch (func) {
3348         case 0x8000000A:
3349                 entry->eax = 1; /* SVM revision 1 */
3350                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3351                                    ASID emulation to nested SVM */
3352                 entry->ecx = 0; /* Reserved */
3353                 entry->edx = 0; /* Do not support any additional features */
3354
3355                 break;
3356         }
3357 }
3358
3359 static const struct trace_print_flags svm_exit_reasons_str[] = {
3360         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3361         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3362         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3363         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3364         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3365         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3366         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3367         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3368         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3369         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3370         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3371         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3372         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3373         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3374         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3375         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3376         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3377         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3378         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3379         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3380         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3381         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3382         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3383         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3384         { SVM_EXIT_INTR,                        "interrupt" },
3385         { SVM_EXIT_NMI,                         "nmi" },
3386         { SVM_EXIT_SMI,                         "smi" },
3387         { SVM_EXIT_INIT,                        "init" },
3388         { SVM_EXIT_VINTR,                       "vintr" },
3389         { SVM_EXIT_CPUID,                       "cpuid" },
3390         { SVM_EXIT_INVD,                        "invd" },
3391         { SVM_EXIT_HLT,                         "hlt" },
3392         { SVM_EXIT_INVLPG,                      "invlpg" },
3393         { SVM_EXIT_INVLPGA,                     "invlpga" },
3394         { SVM_EXIT_IOIO,                        "io" },
3395         { SVM_EXIT_MSR,                         "msr" },
3396         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3397         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3398         { SVM_EXIT_VMRUN,                       "vmrun" },
3399         { SVM_EXIT_VMMCALL,                     "hypercall" },
3400         { SVM_EXIT_VMLOAD,                      "vmload" },
3401         { SVM_EXIT_VMSAVE,                      "vmsave" },
3402         { SVM_EXIT_STGI,                        "stgi" },
3403         { SVM_EXIT_CLGI,                        "clgi" },
3404         { SVM_EXIT_SKINIT,                      "skinit" },
3405         { SVM_EXIT_WBINVD,                      "wbinvd" },
3406         { SVM_EXIT_MONITOR,                     "monitor" },
3407         { SVM_EXIT_MWAIT,                       "mwait" },
3408         { SVM_EXIT_NPF,                         "npf" },
3409         { -1, NULL }
3410 };
3411
3412 static int svm_get_lpage_level(void)
3413 {
3414         return PT_PDPE_LEVEL;
3415 }
3416
3417 static bool svm_rdtscp_supported(void)
3418 {
3419         return false;
3420 }
3421
3422 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3423 {
3424         struct vcpu_svm *svm = to_svm(vcpu);
3425
3426         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3427         if (is_nested(svm))
3428                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3429         update_cr0_intercept(svm);
3430 }
3431
3432 static struct kvm_x86_ops svm_x86_ops = {
3433         .cpu_has_kvm_support = has_svm,
3434         .disabled_by_bios = is_disabled,
3435         .hardware_setup = svm_hardware_setup,
3436         .hardware_unsetup = svm_hardware_unsetup,
3437         .check_processor_compatibility = svm_check_processor_compat,
3438         .hardware_enable = svm_hardware_enable,
3439         .hardware_disable = svm_hardware_disable,
3440         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3441
3442         .vcpu_create = svm_create_vcpu,
3443         .vcpu_free = svm_free_vcpu,
3444         .vcpu_reset = svm_vcpu_reset,
3445
3446         .prepare_guest_switch = svm_prepare_guest_switch,
3447         .vcpu_load = svm_vcpu_load,
3448         .vcpu_put = svm_vcpu_put,
3449
3450         .set_guest_debug = svm_guest_debug,
3451         .get_msr = svm_get_msr,
3452         .set_msr = svm_set_msr,
3453         .get_segment_base = svm_get_segment_base,
3454         .get_segment = svm_get_segment,
3455         .set_segment = svm_set_segment,
3456         .get_cpl = svm_get_cpl,
3457         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3458         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3459         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3460         .set_cr0 = svm_set_cr0,
3461         .set_cr3 = svm_set_cr3,
3462         .set_cr4 = svm_set_cr4,
3463         .set_efer = svm_set_efer,
3464         .get_idt = svm_get_idt,
3465         .set_idt = svm_set_idt,
3466         .get_gdt = svm_get_gdt,
3467         .set_gdt = svm_set_gdt,
3468         .set_dr7 = svm_set_dr7,
3469         .cache_reg = svm_cache_reg,
3470         .get_rflags = svm_get_rflags,
3471         .set_rflags = svm_set_rflags,
3472         .fpu_activate = svm_fpu_activate,
3473         .fpu_deactivate = svm_fpu_deactivate,
3474
3475         .tlb_flush = svm_flush_tlb,
3476
3477         .run = svm_vcpu_run,
3478         .handle_exit = handle_exit,
3479         .skip_emulated_instruction = skip_emulated_instruction,
3480         .set_interrupt_shadow = svm_set_interrupt_shadow,
3481         .get_interrupt_shadow = svm_get_interrupt_shadow,
3482         .patch_hypercall = svm_patch_hypercall,
3483         .set_irq = svm_set_irq,
3484         .set_nmi = svm_inject_nmi,
3485         .queue_exception = svm_queue_exception,
3486         .interrupt_allowed = svm_interrupt_allowed,
3487         .nmi_allowed = svm_nmi_allowed,
3488         .get_nmi_mask = svm_get_nmi_mask,
3489         .set_nmi_mask = svm_set_nmi_mask,
3490         .enable_nmi_window = enable_nmi_window,
3491         .enable_irq_window = enable_irq_window,
3492         .update_cr8_intercept = update_cr8_intercept,
3493
3494         .set_tss_addr = svm_set_tss_addr,
3495         .get_tdp_level = get_npt_level,
3496         .get_mt_mask = svm_get_mt_mask,
3497
3498         .exit_reasons_str = svm_exit_reasons_str,
3499         .get_lpage_level = svm_get_lpage_level,
3500
3501         .cpuid_update = svm_cpuid_update,
3502
3503         .rdtscp_supported = svm_rdtscp_supported,
3504
3505         .set_supported_cpuid = svm_set_supported_cpuid,
3506 };
3507
3508 static int __init svm_init(void)
3509 {
3510         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3511                         __alignof__(struct vcpu_svm), THIS_MODULE);
3512 }
3513
3514 static void __exit svm_exit(void)
3515 {
3516         kvm_exit();
3517 }
3518
3519 module_init(svm_init)
3520 module_exit(svm_exit)