1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/init.h>
4 #include <linux/module.h>
5 #include <linux/timer.h>
6 #include <linux/acpi_pmtmr.h>
7 #include <linux/cpufreq.h>
9 #include <linux/delay.h>
10 #include <linux/clocksource.h>
11 #include <linux/percpu.h>
14 #include <asm/timer.h>
15 #include <asm/vgtod.h>
17 #include <asm/delay.h>
19 unsigned int cpu_khz; /* TSC clocks / usec, not used here */
20 EXPORT_SYMBOL(cpu_khz);
22 EXPORT_SYMBOL(tsc_khz);
25 * TSC can be unstable due to cpufreq or due to unsynced TSCs
27 static int tsc_unstable;
29 /* native_sched_clock() is called before tsc_init(), so
30 we must start with the TSC soft disabled to prevent
31 erroneous rdtsc usage on !cpu_has_tsc processors */
32 static int tsc_disabled = -1;
35 * Scheduler clock - returns current time in nanosec units.
37 u64 native_sched_clock(void)
42 * Fall back to jiffies if there's no TSC available:
43 * ( But note that we still use it if the TSC is marked
44 * unstable. We do this because unlike Time Of Day,
45 * the scheduler clock tolerates small errors and it's
46 * very important for it to be as fast as the platform
49 if (unlikely(tsc_disabled)) {
50 /* No locking but a rare wrong value is not a big deal: */
51 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
54 /* read the Time Stamp Counter: */
57 /* return the value in ns */
58 return cycles_2_ns(this_offset);
61 /* We need to define a real function for sched_clock, to override the
62 weak default version */
63 #ifdef CONFIG_PARAVIRT
64 unsigned long long sched_clock(void)
66 return paravirt_sched_clock();
70 sched_clock(void) __attribute__((alias("native_sched_clock")));
73 int check_tsc_unstable(void)
77 EXPORT_SYMBOL_GPL(check_tsc_unstable);
80 int __init notsc_setup(char *str)
82 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
83 "cannot disable TSC completely.\n");
89 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
92 int __init notsc_setup(char *str)
94 setup_clear_cpu_cap(X86_FEATURE_TSC);
99 __setup("notsc", notsc_setup);
101 #define MAX_RETRIES 5
102 #define SMI_TRESHOLD 50000
105 * Read TSC and the reference counters. Take care of SMI disturbance
107 static u64 tsc_read_refs(u64 *pm, u64 *hpet)
112 for (i = 0; i < MAX_RETRIES; i++) {
115 *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
117 *pm = acpi_pm_read_early();
119 if ((t2 - t1) < SMI_TRESHOLD)
126 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
127 #define CAL_PIT_LOOPS 5000
130 * Try to calibrate the TSC against the Programmable
131 * Interrupt Timer and return the frequency of the TSC
134 * Return ULONG_MAX on failure to calibrate.
136 static unsigned long pit_calibrate_tsc(void)
138 u64 tsc, t1, t2, delta;
139 unsigned long tscmin, tscmax;
142 /* Set the Gate high, disable speaker */
143 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
146 * Setup CTC channel 2* for mode 0, (interrupt on terminal
147 * count mode), binary count. Set the latch register to 50ms
148 * (LSB then MSB) to begin countdown.
151 outb(CAL_LATCH & 0xff, 0x42);
152 outb(CAL_LATCH >> 8, 0x42);
154 tsc = t1 = t2 = get_cycles();
159 while ((inb(0x61) & 0x20) == 0) {
163 if ((unsigned long) delta < tscmin)
164 tscmin = (unsigned int) delta;
165 if ((unsigned long) delta > tscmax)
166 tscmax = (unsigned int) delta;
173 * If we were not able to read the PIT more than PIT_MIN_LOOPS
174 * times, then we have been hit by a massive SMI
176 * If the maximum is 10 times larger than the minimum,
177 * then we got hit by an SMI as well.
179 if (pitcnt < CAL_PIT_LOOPS || tscmax > 10 * tscmin)
182 /* Calculate the PIT value */
184 do_div(delta, CAL_MS);
190 * native_calibrate_tsc - calibrate the tsc on boot
192 unsigned long native_calibrate_tsc(void)
194 u64 tsc1, tsc2, delta, pm1, pm2, hpet1, hpet2;
195 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
197 int hpet = is_hpet_enabled(), i;
200 * Run 5 calibration loops to get the lowest frequency value
201 * (the best estimate). We use two different calibration modes
204 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
205 * load a timeout of 50ms. We read the time right after we
206 * started the timer and wait until the PIT count down reaches
207 * zero. In each wait loop iteration we read the TSC and check
208 * the delta to the previous read. We keep track of the min
209 * and max values of that delta. The delta is mostly defined
210 * by the IO time of the PIT access, so we can detect when a
211 * SMI/SMM disturbance happend between the two reads. If the
212 * maximum time is significantly larger than the minimum time,
213 * then we discard the result and have another try.
215 * 2) Reference counter. If available we use the HPET or the
216 * PMTIMER as a reference to check the sanity of that value.
217 * We use separate TSC readouts and check inside of the
218 * reference read for a SMI/SMM disturbance. We dicard
219 * disturbed values here as well. We do that around the PIT
220 * calibration delay loop as we have to wait for a certain
221 * amount of time anyway.
223 for (i = 0; i < 5; i++) {
224 unsigned long tsc_pit_khz;
227 * Read the start value and the reference count of
228 * hpet/pmtimer when available. Then do the PIT
229 * calibration, which will take at least 50ms, and
230 * read the end value.
232 local_irq_save(flags);
233 tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
234 tsc_pit_khz = pit_calibrate_tsc();
235 tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
236 local_irq_restore(flags);
238 /* Pick the lowest PIT TSC calibration so far */
239 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
241 /* hpet or pmtimer available ? */
242 if (!hpet && !pm1 && !pm2)
245 /* Check, whether the sampling was disturbed by an SMI */
246 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
249 tsc2 = (tsc2 - tsc1) * 1000000LL;
253 hpet2 += 0x100000000ULL;
255 tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
256 do_div(tsc1, 1000000);
259 pm2 += (u64)ACPI_PM_OVRRUN;
261 tsc1 = pm2 * 1000000000LL;
262 do_div(tsc1, PMTMR_TICKS_PER_SEC);
266 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
270 * Now check the results.
272 if (tsc_pit_min == ULONG_MAX) {
273 /* PIT gave no useful value */
274 printk(KERN_WARNING "TSC: PIT calibration failed due to "
275 "SMI disturbance.\n");
277 /* We don't have an alternative source, disable TSC */
278 if (!hpet && !pm1 && !pm2) {
279 printk("TSC: No reference (HPET/PMTIMER) available\n");
283 /* The alternative source failed as well, disable TSC */
284 if (tsc_ref_min == ULONG_MAX) {
285 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
286 "failed due to SMI disturbance.\n");
290 /* Use the alternative source */
291 printk(KERN_INFO "TSC: using %s reference calibration\n",
292 hpet ? "HPET" : "PMTIMER");
297 /* We don't have an alternative source, use the PIT calibration value */
298 if (!hpet && !pm1 && !pm2) {
299 printk(KERN_INFO "TSC: Using PIT calibration value\n");
303 /* The alternative source failed, use the PIT calibration value */
304 if (tsc_ref_min == ULONG_MAX) {
305 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed due "
306 "to SMI disturbance. Using PIT calibration\n");
310 /* Check the reference deviation */
311 delta = ((u64) tsc_pit_min) * 100;
312 do_div(delta, tsc_ref_min);
315 * If both calibration results are inside a 5% window, the we
316 * use the lower frequency of those as it is probably the
319 if (delta >= 95 && delta <= 105) {
320 printk(KERN_INFO "TSC: PIT calibration confirmed by %s.\n",
321 hpet ? "HPET" : "PMTIMER");
322 printk(KERN_INFO "TSC: using %s calibration value\n",
323 tsc_pit_min <= tsc_ref_min ? "PIT" :
324 hpet ? "HPET" : "PMTIMER");
325 return tsc_pit_min <= tsc_ref_min ? tsc_pit_min : tsc_ref_min;
328 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
329 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
332 * The calibration values differ too much. In doubt, we use
333 * the PIT value as we know that there are PMTIMERs around
334 * running at double speed.
336 printk(KERN_INFO "TSC: Using PIT calibration value\n");
341 /* Only called from the Powernow K7 cpu freq driver */
342 int recalibrate_cpu_khz(void)
345 unsigned long cpu_khz_old = cpu_khz;
348 tsc_khz = calibrate_tsc();
350 cpu_data(0).loops_per_jiffy =
351 cpufreq_scale(cpu_data(0).loops_per_jiffy,
352 cpu_khz_old, cpu_khz);
361 EXPORT_SYMBOL(recalibrate_cpu_khz);
363 #endif /* CONFIG_X86_32 */
365 /* Accelerators for sched_clock()
366 * convert from cycles(64bits) => nanoseconds (64bits)
368 * ns = cycles / (freq / ns_per_sec)
369 * ns = cycles * (ns_per_sec / freq)
370 * ns = cycles * (10^9 / (cpu_khz * 10^3))
371 * ns = cycles * (10^6 / cpu_khz)
373 * Then we use scaling math (suggested by george@mvista.com) to get:
374 * ns = cycles * (10^6 * SC / cpu_khz) / SC
375 * ns = cycles * cyc2ns_scale / SC
377 * And since SC is a constant power of two, we can convert the div
380 * We can use khz divisor instead of mhz to keep a better precision, since
381 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
382 * (mathieu.desnoyers@polymtl.ca)
384 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
387 DEFINE_PER_CPU(unsigned long, cyc2ns);
389 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
391 unsigned long long tsc_now, ns_now;
392 unsigned long flags, *scale;
394 local_irq_save(flags);
395 sched_clock_idle_sleep_event();
397 scale = &per_cpu(cyc2ns, cpu);
400 ns_now = __cycles_2_ns(tsc_now);
403 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
405 sched_clock_idle_wakeup_event(0);
406 local_irq_restore(flags);
409 #ifdef CONFIG_CPU_FREQ
411 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
414 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
415 * not that important because current Opteron setups do not support
416 * scaling on SMP anyroads.
418 * Should fix up last_tsc too. Currently gettimeofday in the
419 * first tick after the change will be slightly wrong.
422 static unsigned int ref_freq;
423 static unsigned long loops_per_jiffy_ref;
424 static unsigned long tsc_khz_ref;
426 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
429 struct cpufreq_freqs *freq = data;
430 unsigned long *lpj, dummy;
432 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
436 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
438 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
440 lpj = &boot_cpu_data.loops_per_jiffy;
444 ref_freq = freq->old;
445 loops_per_jiffy_ref = *lpj;
446 tsc_khz_ref = tsc_khz;
448 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
449 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
450 (val == CPUFREQ_RESUMECHANGE)) {
451 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
453 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
454 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
455 mark_tsc_unstable("cpufreq changes");
458 set_cyc2ns_scale(tsc_khz, freq->cpu);
463 static struct notifier_block time_cpufreq_notifier_block = {
464 .notifier_call = time_cpufreq_notifier
467 static int __init cpufreq_tsc(void)
471 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
473 cpufreq_register_notifier(&time_cpufreq_notifier_block,
474 CPUFREQ_TRANSITION_NOTIFIER);
478 core_initcall(cpufreq_tsc);
480 #endif /* CONFIG_CPU_FREQ */
482 /* clocksource code */
484 static struct clocksource clocksource_tsc;
487 * We compare the TSC to the cycle_last value in the clocksource
488 * structure to avoid a nasty time-warp. This can be observed in a
489 * very small window right after one CPU updated cycle_last under
490 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
491 * is smaller than the cycle_last reference value due to a TSC which
492 * is slighty behind. This delta is nowhere else observable, but in
493 * that case it results in a forward time jump in the range of hours
494 * due to the unsigned delta calculation of the time keeping core
495 * code, which is necessary to support wrapping clocksources like pm
498 static cycle_t read_tsc(void)
500 cycle_t ret = (cycle_t)get_cycles();
502 return ret >= clocksource_tsc.cycle_last ?
503 ret : clocksource_tsc.cycle_last;
507 static cycle_t __vsyscall_fn vread_tsc(void)
509 cycle_t ret = (cycle_t)vget_cycles();
511 return ret >= __vsyscall_gtod_data.clock.cycle_last ?
512 ret : __vsyscall_gtod_data.clock.cycle_last;
516 static struct clocksource clocksource_tsc = {
520 .mask = CLOCKSOURCE_MASK(64),
522 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
523 CLOCK_SOURCE_MUST_VERIFY,
529 void mark_tsc_unstable(char *reason)
533 printk("Marking TSC unstable due to %s\n", reason);
534 /* Change only the rating, when not registered */
535 if (clocksource_tsc.mult)
536 clocksource_change_rating(&clocksource_tsc, 0);
538 clocksource_tsc.rating = 0;
542 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
544 static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
546 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
552 /* List of systems that have known TSC problems */
553 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
555 .callback = dmi_mark_tsc_unstable,
556 .ident = "IBM Thinkpad 380XD",
558 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
559 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
566 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
568 #ifdef CONFIG_MGEODE_LX
569 /* RTSC counts during suspend */
570 #define RTSC_SUSP 0x100
572 static void __init check_geode_tsc_reliable(void)
574 unsigned long res_low, res_high;
576 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
577 if (res_low & RTSC_SUSP)
578 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
581 static inline void check_geode_tsc_reliable(void) { }
585 * Make an educated guess if the TSC is trustworthy and synchronized
588 __cpuinit int unsynchronized_tsc(void)
590 if (!cpu_has_tsc || tsc_unstable)
594 if (apic_is_clustered_box())
598 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
601 * Intel systems are normally all synchronized.
602 * Exceptions must mark TSC as unstable:
604 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
605 /* assume multi socket systems are not synchronized: */
606 if (num_possible_cpus() > 1)
613 static void __init init_tsc_clocksource(void)
615 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
616 clocksource_tsc.shift);
617 /* lower the rating if we already know its unstable: */
618 if (check_tsc_unstable()) {
619 clocksource_tsc.rating = 0;
620 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
622 clocksource_register(&clocksource_tsc);
625 void __init tsc_init(void)
633 tsc_khz = calibrate_tsc();
637 mark_tsc_unstable("could not calculate TSC khz");
642 if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
643 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
644 cpu_khz = calibrate_cpu();
647 lpj = ((u64)tsc_khz * 1000);
651 printk("Detected %lu.%03lu MHz processor.\n",
652 (unsigned long)cpu_khz / 1000,
653 (unsigned long)cpu_khz % 1000);
656 * Secondary CPUs do not run through tsc_init(), so set up
657 * all the scale factors for all CPUs, assuming the same
658 * speed as the bootup CPU. (cpufreq notifiers will fix this
659 * up if their speed diverges)
661 for_each_possible_cpu(cpu)
662 set_cyc2ns_scale(cpu_khz, cpu);
664 if (tsc_disabled > 0)
667 /* now allow native_sched_clock() to use rdtsc */
671 /* Check and install the TSC clocksource */
672 dmi_check_system(bad_tsc_dmi_table);
674 if (unsynchronized_tsc())
675 mark_tsc_unstable("TSCs unsynchronized");
677 check_geode_tsc_reliable();
678 init_tsc_clocksource();