2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
58 #include <asm/pgtable.h>
59 #include <asm/tlbflush.h>
63 #include <linux/mc146818rtc.h>
65 #include <mach_apic.h>
66 #include <mach_wakecpu.h>
67 #include <smpboot_hooks.h>
70 * FIXME: For x86_64, those are defined in other files. But moving them here,
71 * would make the setup areas dependent on smp, which is a loss. When we
72 * integrate apic between arches, we can probably do a better job, but
73 * right now, they'll stay here -- glommer
76 /* which logical CPU number maps to which CPU (physical APIC ID) */
77 u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata =
78 { [0 ... NR_CPUS-1] = BAD_APICID };
79 void *x86_cpu_to_apicid_early_ptr;
80 DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID;
81 EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid);
83 u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
84 = { [0 ... NR_CPUS-1] = BAD_APICID };
85 void *x86_bios_cpu_apicid_early_ptr;
86 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
87 EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
88 u8 apicid_2_node[MAX_APICID];
91 /* State of each CPU */
92 DEFINE_PER_CPU(int, cpu_state) = { 0 };
94 /* Store all idle threads, this can be reused instead of creating
95 * a new thread. Also avoids complicated thread destroy functionality
98 #ifdef CONFIG_HOTPLUG_CPU
100 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
101 * removed after init for !CONFIG_HOTPLUG_CPU.
103 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
104 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
105 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
107 struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
108 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
109 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
112 /* Number of siblings per CPU package */
113 int smp_num_siblings = 1;
114 EXPORT_SYMBOL(smp_num_siblings);
116 /* Last level cache ID of each logical CPU */
117 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
119 /* bitmap of online cpus */
120 cpumask_t cpu_online_map __read_mostly;
121 EXPORT_SYMBOL(cpu_online_map);
123 cpumask_t cpu_callin_map;
124 cpumask_t cpu_callout_map;
125 cpumask_t cpu_possible_map;
126 EXPORT_SYMBOL(cpu_possible_map);
128 /* representing HT siblings of each logical CPU */
129 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
130 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
132 /* representing HT and core siblings of each logical CPU */
133 DEFINE_PER_CPU(cpumask_t, cpu_core_map);
134 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
136 /* Per CPU bogomips and other parameters */
137 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
138 EXPORT_PER_CPU_SYMBOL(cpu_info);
140 static atomic_t init_deasserted;
142 static int boot_cpu_logical_apicid;
144 /* ready for x86_64, no harm for x86, since it will overwrite after alloc */
145 unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE);
147 /* representing cpus for which sibling maps can be computed */
148 static cpumask_t cpu_sibling_setup_map;
150 /* Set if we find a B stepping CPU */
151 int __cpuinitdata smp_b_stepping;
153 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
155 /* which logical CPUs are on which nodes */
156 cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly =
157 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
158 EXPORT_SYMBOL(node_to_cpumask_map);
159 /* which node each logical CPU is on */
160 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
161 EXPORT_SYMBOL(cpu_to_node_map);
163 /* set up a mapping between cpu and node. */
164 static void map_cpu_to_node(int cpu, int node)
166 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
167 cpu_set(cpu, node_to_cpumask_map[node]);
168 cpu_to_node_map[cpu] = node;
171 /* undo a mapping between cpu and node. */
172 static void unmap_cpu_to_node(int cpu)
176 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
177 for (node = 0; node < MAX_NUMNODES; node++)
178 cpu_clear(cpu, node_to_cpumask_map[node]);
179 cpu_to_node_map[cpu] = 0;
181 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
182 #define map_cpu_to_node(cpu, node) ({})
183 #define unmap_cpu_to_node(cpu) ({})
187 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
188 { [0 ... NR_CPUS-1] = BAD_APICID };
190 void map_cpu_to_logical_apicid(void)
192 int cpu = smp_processor_id();
193 int apicid = logical_smp_processor_id();
194 int node = apicid_to_node(apicid);
196 if (!node_online(node))
197 node = first_online_node;
199 cpu_2_logical_apicid[cpu] = apicid;
200 map_cpu_to_node(cpu, node);
203 void unmap_cpu_to_logical_apicid(int cpu)
205 cpu_2_logical_apicid[cpu] = BAD_APICID;
206 unmap_cpu_to_node(cpu);
209 #define unmap_cpu_to_logical_apicid(cpu) do {} while (0)
210 #define map_cpu_to_logical_apicid() do {} while (0)
214 * Report back to the Boot Processor.
217 void __cpuinit smp_callin(void)
220 unsigned long timeout;
223 * If waken up by an INIT in an 82489DX configuration
224 * we may get here before an INIT-deassert IPI reaches
225 * our local APIC. We have to wait for the IPI or we'll
226 * lock up on an APIC access.
228 wait_for_init_deassert(&init_deasserted);
231 * (This works even if the APIC is not enabled.)
233 phys_id = GET_APIC_ID(apic_read(APIC_ID));
234 cpuid = smp_processor_id();
235 if (cpu_isset(cpuid, cpu_callin_map)) {
236 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
239 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
242 * STARTUP IPIs are fragile beasts as they might sometimes
243 * trigger some glue motherboard logic. Complete APIC bus
244 * silence for 1 second, this overestimates the time the
245 * boot CPU is spending to send the up to 2 STARTUP IPIs
246 * by a factor of two. This should be enough.
250 * Waiting 2s total for startup (udelay is not yet working)
252 timeout = jiffies + 2*HZ;
253 while (time_before(jiffies, timeout)) {
255 * Has the boot CPU finished it's STARTUP sequence?
257 if (cpu_isset(cpuid, cpu_callout_map))
262 if (!time_before(jiffies, timeout)) {
263 panic("%s: CPU%d started up but did not get a callout!\n",
268 * the boot CPU has finished the init stage and is spinning
269 * on callin_map until we finish. We are free to set up this
270 * CPU, first the APIC. (this is probably redundant on most
274 Dprintk("CALLIN, before setup_local_APIC().\n");
275 smp_callin_clear_local_apic();
277 end_local_APIC_setup();
278 map_cpu_to_logical_apicid();
283 * Need to enable IRQs because it can take longer and then
284 * the NMI watchdog might kill us.
289 Dprintk("Stack at about %p\n", &cpuid);
292 * Save our processor parameters
294 smp_store_cpu_info(cpuid);
297 * Allow the master to continue.
299 cpu_set(cpuid, cpu_callin_map);
303 * Activate a secondary processor.
305 void __cpuinit start_secondary(void *unused)
308 * Don't put *anything* before cpu_init(), SMP booting is too
309 * fragile that we want to limit the things done here to the
310 * most necessary things.
319 /* otherwise gcc will move up smp_processor_id before the cpu_init */
322 * Check TSC synchronization with the BP:
324 check_tsc_sync_target();
326 if (nmi_watchdog == NMI_IO_APIC) {
327 disable_8259A_irq(0);
328 enable_NMI_through_LVT0();
332 /* This must be done before setting cpu_online_map */
333 set_cpu_sibling_map(raw_smp_processor_id());
337 * We need to hold call_lock, so there is no inconsistency
338 * between the time smp_call_function() determines number of
339 * IPI recipients, and the time when the determination is made
340 * for which cpus receive the IPI. Holding this
341 * lock helps us to not include this cpu in a currently in progress
342 * smp_call_function().
344 lock_ipi_call_lock();
346 spin_lock(&vector_lock);
348 /* Setup the per cpu irq handling data structures */
349 __setup_vector_irq(smp_processor_id());
351 * Allow the master to continue.
353 spin_unlock(&vector_lock);
355 cpu_set(smp_processor_id(), cpu_online_map);
356 unlock_ipi_call_lock();
357 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
359 setup_secondary_clock();
367 * Everything has been set up for the secondary
368 * CPUs - they just need to reload everything
369 * from the task structure
370 * This function must not return.
372 void __devinit initialize_secondary(void)
375 * We don't actually need to load the full TSS,
376 * basically just the stack pointer and the ip.
383 :"m" (current->thread.sp), "m" (current->thread.ip));
387 static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
391 * Mask B, Pentium, but not Pentium MMX
393 if (c->x86_vendor == X86_VENDOR_INTEL &&
395 c->x86_mask >= 1 && c->x86_mask <= 4 &&
398 * Remember we have B step Pentia with bugs
403 * Certain Athlons might work (for various values of 'work') in SMP
404 * but they are not certified as MP capable.
406 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
408 if (num_possible_cpus() == 1)
411 /* Athlon 660/661 is valid. */
412 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
416 /* Duron 670 is valid */
417 if ((c->x86_model == 7) && (c->x86_mask == 0))
421 * Athlon 662, Duron 671, and Athlon >model 7 have capability
422 * bit. It's worth noting that the A5 stepping (662) of some
423 * Athlon XP's have the MP bit set.
424 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
427 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
428 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
433 /* If we get here, not a certified SMP capable AMD system. */
434 add_taint(TAINT_UNSAFE_SMP);
442 void smp_checks(void)
445 printk(KERN_WARNING "WARNING: SMP operation may be unreliable"
446 "with B stepping processors.\n");
449 * Don't taint if we are running SMP kernel on a single non-MP
452 if (tainted & TAINT_UNSAFE_SMP) {
453 if (num_online_cpus())
454 printk(KERN_INFO "WARNING: This combination of AMD"
455 "processors is not suitable for SMP.\n");
457 tainted &= ~TAINT_UNSAFE_SMP;
462 * The bootstrap kernel entry code has set these up. Save them for
466 void __cpuinit smp_store_cpu_info(int id)
468 struct cpuinfo_x86 *c = &cpu_data(id);
473 identify_secondary_cpu(c);
478 void __cpuinit set_cpu_sibling_map(int cpu)
481 struct cpuinfo_x86 *c = &cpu_data(cpu);
483 cpu_set(cpu, cpu_sibling_setup_map);
485 if (smp_num_siblings > 1) {
486 for_each_cpu_mask(i, cpu_sibling_setup_map) {
487 if (c->phys_proc_id == cpu_data(i).phys_proc_id &&
488 c->cpu_core_id == cpu_data(i).cpu_core_id) {
489 cpu_set(i, per_cpu(cpu_sibling_map, cpu));
490 cpu_set(cpu, per_cpu(cpu_sibling_map, i));
491 cpu_set(i, per_cpu(cpu_core_map, cpu));
492 cpu_set(cpu, per_cpu(cpu_core_map, i));
493 cpu_set(i, c->llc_shared_map);
494 cpu_set(cpu, cpu_data(i).llc_shared_map);
498 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
501 cpu_set(cpu, c->llc_shared_map);
503 if (current_cpu_data.x86_max_cores == 1) {
504 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
509 for_each_cpu_mask(i, cpu_sibling_setup_map) {
510 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
511 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
512 cpu_set(i, c->llc_shared_map);
513 cpu_set(cpu, cpu_data(i).llc_shared_map);
515 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
516 cpu_set(i, per_cpu(cpu_core_map, cpu));
517 cpu_set(cpu, per_cpu(cpu_core_map, i));
519 * Does this new cpu bringup a new core?
521 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
523 * for each core in package, increment
524 * the booted_cores for this new cpu
526 if (first_cpu(per_cpu(cpu_sibling_map, i)) == i)
529 * increment the core count for all
530 * the other cpus in this package
533 cpu_data(i).booted_cores++;
534 } else if (i != cpu && !c->booted_cores)
535 c->booted_cores = cpu_data(i).booted_cores;
540 /* maps the cpu to the sched domain representing multi-core */
541 cpumask_t cpu_coregroup_map(int cpu)
543 struct cpuinfo_x86 *c = &cpu_data(cpu);
545 * For perf, we return last level cache shared map.
546 * And for power savings, we return cpu_core_map
548 if (sched_mc_power_savings || sched_smt_power_savings)
549 return per_cpu(cpu_core_map, cpu);
551 return c->llc_shared_map;
555 * Currently trivial. Write the real->protected mode
556 * bootstrap into the page concerned. The caller
557 * has made sure it's suitably aligned.
560 unsigned long __cpuinit setup_trampoline(void)
562 memcpy(trampoline_base, trampoline_data,
563 trampoline_end - trampoline_data);
564 return virt_to_phys(trampoline_base);
569 * We are called very early to get the low memory for the
570 * SMP bootup trampoline page.
572 void __init smp_alloc_memory(void)
574 trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE);
576 * Has to be in very low memory so we can execute
579 if (__pa(trampoline_base) >= 0x9F000)
584 void impress_friends(void)
587 unsigned long bogosum = 0;
589 * Allow the user to impress friends.
591 Dprintk("Before bogomips.\n");
592 for_each_possible_cpu(cpu)
593 if (cpu_isset(cpu, cpu_callout_map))
594 bogosum += cpu_data(cpu).loops_per_jiffy;
596 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
599 (bogosum/(5000/HZ))%100);
601 Dprintk("Before bogocount - setting activated=1.\n");
604 static inline void __inquire_remote_apic(int apicid)
606 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
607 char *names[] = { "ID", "VERSION", "SPIV" };
611 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
613 for (i = 0; i < ARRAY_SIZE(regs); i++) {
614 printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
619 status = safe_apic_wait_icr_idle();
622 "a previous APIC delivery may have failed\n");
624 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
625 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
630 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
631 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
634 case APIC_ICR_RR_VALID:
635 status = apic_read(APIC_RRR);
636 printk(KERN_CONT "%08x\n", status);
639 printk(KERN_CONT "failed\n");
644 #ifdef WAKE_SECONDARY_VIA_NMI
646 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
647 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
648 * won't ... remember to clear down the APIC, etc later.
651 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
653 unsigned long send_status, accept_status = 0;
657 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
659 /* Boot on the stack */
660 /* Kick the second */
661 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
663 Dprintk("Waiting for send to finish...\n");
664 send_status = safe_apic_wait_icr_idle();
667 * Give the other CPU some time to accept the IPI.
671 * Due to the Pentium erratum 3AP.
673 maxlvt = lapic_get_maxlvt();
675 apic_read_around(APIC_SPIV);
676 apic_write(APIC_ESR, 0);
678 accept_status = (apic_read(APIC_ESR) & 0xEF);
679 Dprintk("NMI sent.\n");
682 printk(KERN_ERR "APIC never delivered???\n");
684 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
686 return (send_status | accept_status);
688 #endif /* WAKE_SECONDARY_VIA_NMI */
690 #ifdef WAKE_SECONDARY_VIA_INIT
692 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
694 unsigned long send_status, accept_status = 0;
695 int maxlvt, num_starts, j;
698 * Be paranoid about clearing APIC errors.
700 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
701 apic_read_around(APIC_SPIV);
702 apic_write(APIC_ESR, 0);
706 Dprintk("Asserting INIT.\n");
709 * Turn INIT on target chip
711 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
716 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
719 Dprintk("Waiting for send to finish...\n");
720 send_status = safe_apic_wait_icr_idle();
724 Dprintk("Deasserting INIT.\n");
727 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
730 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
732 Dprintk("Waiting for send to finish...\n");
733 send_status = safe_apic_wait_icr_idle();
736 atomic_set(&init_deasserted, 1);
739 * Should we send STARTUP IPIs ?
741 * Determine this based on the APIC version.
742 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
744 if (APIC_INTEGRATED(apic_version[phys_apicid]))
750 * Paravirt / VMI wants a startup IPI hook here to set up the
751 * target processor state.
753 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
755 (unsigned long)init_rsp);
757 (unsigned long)stack_start.sp);
761 * Run STARTUP IPI loop.
763 Dprintk("#startup loops: %d.\n", num_starts);
765 maxlvt = lapic_get_maxlvt();
767 for (j = 1; j <= num_starts; j++) {
768 Dprintk("Sending STARTUP #%d.\n", j);
769 apic_read_around(APIC_SPIV);
770 apic_write(APIC_ESR, 0);
772 Dprintk("After apic_write.\n");
779 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
781 /* Boot on the stack */
782 /* Kick the second */
783 apic_write_around(APIC_ICR, APIC_DM_STARTUP
784 | (start_eip >> 12));
787 * Give the other CPU some time to accept the IPI.
791 Dprintk("Startup point 1.\n");
793 Dprintk("Waiting for send to finish...\n");
794 send_status = safe_apic_wait_icr_idle();
797 * Give the other CPU some time to accept the IPI.
801 * Due to the Pentium erratum 3AP.
804 apic_read_around(APIC_SPIV);
805 apic_write(APIC_ESR, 0);
807 accept_status = (apic_read(APIC_ESR) & 0xEF);
808 if (send_status || accept_status)
811 Dprintk("After Startup.\n");
814 printk(KERN_ERR "APIC never delivered???\n");
816 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
818 return (send_status | accept_status);
820 #endif /* WAKE_SECONDARY_VIA_INIT */
823 struct work_struct work;
824 struct task_struct *idle;
825 struct completion done;
829 static void __cpuinit do_fork_idle(struct work_struct *work)
831 struct create_idle *c_idle =
832 container_of(work, struct create_idle, work);
834 c_idle->idle = fork_idle(c_idle->cpu);
835 complete(&c_idle->done);
838 static int __cpuinit do_boot_cpu(int apicid, int cpu)
840 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
841 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
842 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
845 unsigned long boot_error = 0;
847 unsigned long start_ip;
848 unsigned short nmi_high = 0, nmi_low = 0;
849 struct create_idle c_idle = {
851 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
853 INIT_WORK(&c_idle.work, do_fork_idle);
855 /* allocate memory for gdts of secondary cpus. Hotplug is considered */
856 if (!cpu_gdt_descr[cpu].address &&
857 !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) {
858 printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu);
862 /* Allocate node local memory for AP pdas */
863 if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) {
864 struct x8664_pda *newpda, *pda;
865 int node = cpu_to_node(cpu);
867 newpda = kmalloc_node(sizeof(struct x8664_pda), GFP_ATOMIC,
870 memcpy(newpda, pda, sizeof(struct x8664_pda));
871 cpu_pda(cpu) = newpda;
874 "Could not allocate node local PDA for CPU %d on node %d\n",
879 alternatives_smp_switch(1);
881 c_idle.idle = get_idle_for_cpu(cpu);
884 * We can't use kernel_thread since we must avoid to
885 * reschedule the child.
888 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
889 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
890 init_idle(c_idle.idle, cpu);
894 if (!keventd_up() || current_is_keventd())
895 c_idle.work.func(&c_idle.work);
897 schedule_work(&c_idle.work);
898 wait_for_completion(&c_idle.done);
901 if (IS_ERR(c_idle.idle)) {
902 printk("failed fork for CPU %d\n", cpu);
903 return PTR_ERR(c_idle.idle);
906 set_idle_for_cpu(cpu, c_idle.idle);
909 per_cpu(current_task, cpu) = c_idle.idle;
911 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
912 c_idle.idle->thread.ip = (unsigned long) start_secondary;
913 /* Stack for startup_32 can be just as for start_secondary onwards */
914 stack_start.sp = (void *) c_idle.idle->thread.sp;
917 cpu_pda(cpu)->pcurrent = c_idle.idle;
918 init_rsp = c_idle.idle->thread.sp;
919 load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread);
920 initial_code = (unsigned long)start_secondary;
921 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
924 /* start_ip had better be page-aligned! */
925 start_ip = setup_trampoline();
927 /* So we see what's up */
928 printk(KERN_INFO "Booting processor %d/%d ip %lx\n",
929 cpu, apicid, start_ip);
932 * This grunge runs the startup process for
933 * the targeted processor.
936 atomic_set(&init_deasserted, 0);
938 Dprintk("Setting warm reset code and vector.\n");
940 store_NMI_vector(&nmi_high, &nmi_low);
942 smpboot_setup_warm_reset_vector(start_ip);
944 * Be paranoid about clearing APIC errors.
946 apic_write(APIC_ESR, 0);
950 * Starting actual IPI sequence...
952 boot_error = wakeup_secondary_cpu(apicid, start_ip);
956 * allow APs to start initializing.
958 Dprintk("Before Callout %d.\n", cpu);
959 cpu_set(cpu, cpu_callout_map);
960 Dprintk("After Callout %d.\n", cpu);
963 * Wait 5s total for a response
965 for (timeout = 0; timeout < 50000; timeout++) {
966 if (cpu_isset(cpu, cpu_callin_map))
967 break; /* It has booted */
971 if (cpu_isset(cpu, cpu_callin_map)) {
972 /* number CPUs logically, starting from 1 (BSP is 0) */
974 printk(KERN_INFO "CPU%d: ", cpu);
975 print_cpu_info(&cpu_data(cpu));
976 Dprintk("CPU has booted.\n");
979 if (*((volatile unsigned char *)trampoline_base)
981 /* trampoline started but...? */
982 printk(KERN_ERR "Stuck ??\n");
984 /* trampoline code not run */
985 printk(KERN_ERR "Not responding.\n");
986 inquire_remote_apic(apicid);
991 /* Try to put things back the way they were before ... */
992 unmap_cpu_to_logical_apicid(cpu);
994 clear_node_cpumask(cpu); /* was set by numa_add_cpu */
996 cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */
997 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
998 cpu_clear(cpu, cpu_possible_map);
999 cpu_clear(cpu, cpu_present_map);
1000 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
1003 /* mark "stuck" area as not stuck */
1004 *((volatile unsigned long *)trampoline_base) = 0;
1009 int __cpuinit native_cpu_up(unsigned int cpu)
1011 int apicid = cpu_present_to_apicid(cpu);
1012 unsigned long flags;
1015 WARN_ON(irqs_disabled());
1017 Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1019 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
1020 !physid_isset(apicid, phys_cpu_present_map)) {
1021 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
1026 * Already booted CPU?
1028 if (cpu_isset(cpu, cpu_callin_map)) {
1029 Dprintk("do_boot_cpu %d Already started\n", cpu);
1034 * Save current MTRR state in case it was changed since early boot
1035 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1039 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1041 #ifdef CONFIG_X86_32
1042 /* init low mem mapping */
1043 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
1044 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
1048 err = do_boot_cpu(apicid, cpu);
1050 Dprintk("do_boot_cpu failed %d\n", err);
1055 * Check TSC synchronization with the AP (keep irqs disabled
1058 local_irq_save(flags);
1059 check_tsc_sync_source(cpu);
1060 local_irq_restore(flags);
1062 while (!cpu_isset(cpu, cpu_online_map)) {
1064 touch_nmi_watchdog();
1071 * Fall back to non SMP mode after errors.
1073 * RED-PEN audit/test this more. I bet there is more state messed up here.
1075 static __init void disable_smp(void)
1077 cpu_present_map = cpumask_of_cpu(0);
1078 cpu_possible_map = cpumask_of_cpu(0);
1079 #ifdef CONFIG_X86_32
1080 smpboot_clear_io_apic_irqs();
1082 if (smp_found_config)
1083 phys_cpu_present_map =
1084 physid_mask_of_physid(boot_cpu_physical_apicid);
1086 phys_cpu_present_map = physid_mask_of_physid(0);
1087 map_cpu_to_logical_apicid();
1088 cpu_set(0, per_cpu(cpu_sibling_map, 0));
1089 cpu_set(0, per_cpu(cpu_core_map, 0));
1093 * Various sanity checks.
1095 static int __init smp_sanity_check(unsigned max_cpus)
1097 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1098 printk(KERN_WARNING "weird, boot CPU (#%d) not listed"
1099 "by the BIOS.\n", hard_smp_processor_id());
1100 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1104 * If we couldn't find an SMP configuration at boot time,
1105 * get out of here now!
1107 if (!smp_found_config && !acpi_lapic) {
1108 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1110 if (APIC_init_uniprocessor())
1111 printk(KERN_NOTICE "Local APIC not detected."
1112 " Using dummy APIC emulation.\n");
1117 * Should not be necessary because the MP table should list the boot
1118 * CPU too, but we do it for the sake of robustness anyway.
1120 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1122 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1123 boot_cpu_physical_apicid);
1124 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1128 * If we couldn't find a local APIC, then get out of here now!
1130 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1132 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1133 boot_cpu_physical_apicid);
1134 printk(KERN_ERR "... forcing use of dummy APIC emulation."
1135 "(tell your hw vendor)\n");
1136 smpboot_clear_io_apic();
1140 verify_local_APIC();
1143 * If SMP should be disabled, then really disable it!
1146 printk(KERN_INFO "SMP mode deactivated,"
1147 "forcing use of dummy APIC emulation.\n");
1148 smpboot_clear_io_apic();
1149 #ifdef CONFIG_X86_32
1150 if (nmi_watchdog == NMI_LOCAL_APIC) {
1151 printk(KERN_INFO "activating minimal APIC for"
1152 "NMI watchdog use.\n");
1155 end_local_APIC_setup();
1164 static void __init smp_cpu_index_default(void)
1167 struct cpuinfo_x86 *c;
1169 for_each_cpu_mask(i, cpu_possible_map) {
1171 /* mark all to hotplug */
1172 c->cpu_index = NR_CPUS;
1177 * Prepare for SMP bootup. The MP table or ACPI has been read
1178 * earlier. Just do some sanity checking here and enable APIC mode.
1180 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1182 nmi_watchdog_default();
1183 smp_cpu_index_default();
1184 current_cpu_data = boot_cpu_data;
1185 cpu_callin_map = cpumask_of_cpu(0);
1188 * Setup boot CPU information
1190 smp_store_cpu_info(0); /* Final full version of the data */
1191 boot_cpu_logical_apicid = logical_smp_processor_id();
1192 current_thread_info()->cpu = 0; /* needed? */
1193 set_cpu_sibling_map(0);
1195 if (smp_sanity_check(max_cpus) < 0) {
1196 printk(KERN_INFO "SMP disabled\n");
1201 if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_physical_apicid) {
1202 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1203 GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_physical_apicid);
1204 /* Or can we switch back to PIC here? */
1207 #ifdef CONFIG_X86_32
1211 * Switch from PIC to APIC mode.
1215 #ifdef CONFIG_X86_64
1217 * Enable IO APIC before setting up error vector
1219 if (!skip_ioapic_setup && nr_ioapics)
1222 end_local_APIC_setup();
1224 map_cpu_to_logical_apicid();
1226 setup_portio_remap();
1228 smpboot_setup_io_apic();
1230 * Set up local APIC timer on boot CPU.
1233 printk(KERN_INFO "CPU%d: ", 0);
1234 print_cpu_info(&cpu_data(0));
1238 * Early setup to make printk work.
1240 void __init native_smp_prepare_boot_cpu(void)
1242 int me = smp_processor_id();
1243 #ifdef CONFIG_X86_32
1245 switch_to_new_gdt();
1247 /* already set me in cpu_online_map in boot_cpu_init() */
1248 cpu_set(me, cpu_callout_map);
1249 per_cpu(cpu_state, me) = CPU_ONLINE;
1252 void __init native_smp_cpus_done(unsigned int max_cpus)
1255 * Cleanup possible dangling ends...
1257 smpboot_restore_warm_reset_vector();
1259 Dprintk("Boot done.\n");
1263 #ifdef CONFIG_X86_IO_APIC
1264 setup_ioapic_dest();
1266 check_nmi_watchdog();
1267 #ifdef CONFIG_X86_32
1272 #ifdef CONFIG_HOTPLUG_CPU
1274 # ifdef CONFIG_X86_32
1275 void cpu_exit_clear(void)
1277 int cpu = raw_smp_processor_id();
1284 cpu_clear(cpu, cpu_callout_map);
1285 cpu_clear(cpu, cpu_callin_map);
1287 unmap_cpu_to_logical_apicid(cpu);
1289 # endif /* CONFIG_X86_32 */
1291 void remove_siblinginfo(int cpu)
1294 struct cpuinfo_x86 *c = &cpu_data(cpu);
1296 for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) {
1297 cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
1299 * last thread sibling in this cpu core going down
1301 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
1302 cpu_data(sibling).booted_cores--;
1305 for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
1306 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
1307 cpus_clear(per_cpu(cpu_sibling_map, cpu));
1308 cpus_clear(per_cpu(cpu_core_map, cpu));
1309 c->phys_proc_id = 0;
1311 cpu_clear(cpu, cpu_sibling_setup_map);
1314 int additional_cpus __initdata = -1;
1316 static __init int setup_additional_cpus(char *s)
1318 return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL;
1320 early_param("additional_cpus", setup_additional_cpus);
1323 * cpu_possible_map should be static, it cannot change as cpu's
1324 * are onlined, or offlined. The reason is per-cpu data-structures
1325 * are allocated by some modules at init time, and dont expect to
1326 * do this dynamically on cpu arrival/departure.
1327 * cpu_present_map on the other hand can change dynamically.
1328 * In case when cpu_hotplug is not compiled, then we resort to current
1329 * behaviour, which is cpu_possible == cpu_present.
1332 * Three ways to find out the number of additional hotplug CPUs:
1333 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1334 * - The user can overwrite it with additional_cpus=NUM
1335 * - Otherwise don't reserve additional CPUs.
1336 * We do this because additional CPUs waste a lot of memory.
1339 __init void prefill_possible_map(void)
1344 if (additional_cpus == -1) {
1345 if (disabled_cpus > 0)
1346 additional_cpus = disabled_cpus;
1348 additional_cpus = 0;
1350 possible = num_processors + additional_cpus;
1351 if (possible > NR_CPUS)
1354 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1355 possible, max_t(int, possible - num_processors, 0));
1357 for (i = 0; i < possible; i++)
1358 cpu_set(i, cpu_possible_map);
1361 static void __ref remove_cpu_from_maps(int cpu)
1363 cpu_clear(cpu, cpu_online_map);
1364 #ifdef CONFIG_X86_64
1365 cpu_clear(cpu, cpu_callout_map);
1366 cpu_clear(cpu, cpu_callin_map);
1367 /* was set by cpu_init() */
1368 clear_bit(cpu, (unsigned long *)&cpu_initialized);
1369 clear_node_cpumask(cpu);
1373 int __cpu_disable(void)
1375 int cpu = smp_processor_id();
1378 * Perhaps use cpufreq to drop frequency, but that could go
1379 * into generic code.
1381 * We won't take down the boot processor on i386 due to some
1382 * interrupts only being able to be serviced by the BSP.
1383 * Especially so if we're not using an IOAPIC -zwane
1388 if (nmi_watchdog == NMI_LOCAL_APIC)
1389 stop_apic_nmi_watchdog(NULL);
1394 * Allow any queued timer interrupts to get serviced
1395 * This is only a temporary solution until we cleanup
1396 * fixup_irqs as we do for IA64.
1401 local_irq_disable();
1402 remove_siblinginfo(cpu);
1404 /* It's now safe to remove this processor from the online map */
1405 remove_cpu_from_maps(cpu);
1406 fixup_irqs(cpu_online_map);
1410 void __cpu_die(unsigned int cpu)
1412 /* We don't do anything here: idle task is faking death itself. */
1415 for (i = 0; i < 10; i++) {
1416 /* They ack this in play_dead by setting CPU_DEAD */
1417 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1418 printk(KERN_INFO "CPU %d is now offline\n", cpu);
1419 if (1 == num_online_cpus())
1420 alternatives_smp_switch(0);
1425 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1427 #else /* ... !CONFIG_HOTPLUG_CPU */
1428 int __cpu_disable(void)
1433 void __cpu_die(unsigned int cpu)
1435 /* We said "no" in __cpu_disable */
1441 * If the BIOS enumerates physical processors before logical,
1442 * maxcpus=N at enumeration-time can be used to disable HT.
1444 static int __init parse_maxcpus(char *arg)
1446 extern unsigned int maxcpus;
1448 maxcpus = simple_strtoul(arg, NULL, 0);
1451 early_param("maxcpus", parse_maxcpus);