1 #include <linux/dma-mapping.h>
2 #include <linux/dmar.h>
3 #include <linux/bootmem.h>
10 #include <asm/calgary.h>
11 #include <asm/amd_iommu.h>
13 static int forbid_dac __read_mostly;
15 struct dma_mapping_ops *dma_ops;
16 EXPORT_SYMBOL(dma_ops);
18 static int iommu_sac_force __read_mostly;
20 #ifdef CONFIG_IOMMU_DEBUG
21 int panic_on_overflow __read_mostly = 1;
22 int force_iommu __read_mostly = 1;
24 int panic_on_overflow __read_mostly = 0;
25 int force_iommu __read_mostly = 0;
28 int iommu_merge __read_mostly = 0;
30 int no_iommu __read_mostly;
31 /* Set this to 1 if there is a HW IOMMU in the system */
32 int iommu_detected __read_mostly = 0;
34 dma_addr_t bad_dma_address __read_mostly = 0;
35 EXPORT_SYMBOL(bad_dma_address);
37 /* Dummy device used for NULL arguments (normally ISA). Better would
38 be probably a smaller DMA mask, but this is bug-to-bug compatible
40 struct device x86_dma_fallback_dev = {
41 .bus_id = "fallback device",
42 .coherent_dma_mask = DMA_32BIT_MASK,
43 .dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
45 EXPORT_SYMBOL(x86_dma_fallback_dev);
47 int dma_set_mask(struct device *dev, u64 mask)
49 if (!dev->dma_mask || !dma_supported(dev, mask))
52 *dev->dma_mask = mask;
56 EXPORT_SYMBOL(dma_set_mask);
59 static __initdata void *dma32_bootmem_ptr;
60 static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
62 static int __init parse_dma32_size_opt(char *p)
66 dma32_bootmem_size = memparse(p, &p);
69 early_param("dma32_size", parse_dma32_size_opt);
71 void __init dma32_reserve_bootmem(void)
73 unsigned long size, align;
74 if (max_pfn <= MAX_DMA32_PFN)
78 * check aperture_64.c allocate_aperture() for reason about
82 size = roundup(dma32_bootmem_size, align);
83 dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
85 if (dma32_bootmem_ptr)
86 dma32_bootmem_size = size;
88 dma32_bootmem_size = 0;
90 static void __init dma32_free_bootmem(void)
93 if (max_pfn <= MAX_DMA32_PFN)
96 if (!dma32_bootmem_ptr)
99 free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);
101 dma32_bootmem_ptr = NULL;
102 dma32_bootmem_size = 0;
105 void __init pci_iommu_alloc(void)
107 /* free the range so iommu could get some range less than 4G */
108 dma32_free_bootmem();
110 * The order of these functions is important for
111 * fall-back/fail-over reasons
113 gart_iommu_hole_init();
117 detect_intel_iommu();
124 unsigned long iommu_nr_pages(unsigned long addr, unsigned long len)
126 unsigned long size = roundup((addr & ~PAGE_MASK) + len, PAGE_SIZE);
128 return size >> PAGE_SHIFT;
130 EXPORT_SYMBOL(iommu_nr_pages);
133 void *dma_generic_alloc_coherent(struct device *dev, size_t size,
134 dma_addr_t *dma_addr, gfp_t flag)
136 unsigned long dma_mask;
140 dma_mask = dma_alloc_coherent_mask(dev, flag);
144 page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
148 addr = page_to_phys(page);
149 if (!is_buffer_dma_capable(dma_mask, addr, size)) {
150 __free_pages(page, get_order(size));
152 if (dma_mask < DMA_32BIT_MASK && !(flag & GFP_DMA)) {
153 flag = (flag & ~GFP_DMA32) | GFP_DMA;
161 return page_address(page);
165 * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
168 static __init int iommu_setup(char *p)
176 if (!strncmp(p, "off", 3))
178 /* gart_parse_options has more force support */
179 if (!strncmp(p, "force", 5))
181 if (!strncmp(p, "noforce", 7)) {
186 if (!strncmp(p, "biomerge", 8)) {
190 if (!strncmp(p, "panic", 5))
191 panic_on_overflow = 1;
192 if (!strncmp(p, "nopanic", 7))
193 panic_on_overflow = 0;
194 if (!strncmp(p, "merge", 5)) {
198 if (!strncmp(p, "nomerge", 7))
200 if (!strncmp(p, "forcesac", 8))
202 if (!strncmp(p, "allowdac", 8))
204 if (!strncmp(p, "nodac", 5))
206 if (!strncmp(p, "usedac", 6)) {
210 #ifdef CONFIG_SWIOTLB
211 if (!strncmp(p, "soft", 4))
215 gart_parse_options(p);
217 #ifdef CONFIG_CALGARY_IOMMU
218 if (!strncmp(p, "calgary", 7))
220 #endif /* CONFIG_CALGARY_IOMMU */
222 p += strcspn(p, ",");
228 early_param("iommu", iommu_setup);
230 int dma_supported(struct device *dev, u64 mask)
232 struct dma_mapping_ops *ops = get_dma_ops(dev);
235 if (mask > 0xffffffff && forbid_dac > 0) {
236 dev_info(dev, "PCI: Disallowing DAC for device\n");
241 if (ops->dma_supported)
242 return ops->dma_supported(dev, mask);
244 /* Copied from i386. Doesn't make much sense, because it will
245 only work for pci_alloc_coherent.
246 The caller just has to use GFP_DMA in this case. */
247 if (mask < DMA_24BIT_MASK)
250 /* Tell the device to use SAC when IOMMU force is on. This
251 allows the driver to use cheaper accesses in some cases.
253 Problem with this is that if we overflow the IOMMU area and
254 return DAC as fallback address the device may not handle it
257 As a special case some controllers have a 39bit address
258 mode that is as efficient as 32bit (aic79xx). Don't force
259 SAC for these. Assume all masks <= 40 bits are of this
260 type. Normally this doesn't make any difference, but gives
261 more gentle handling of IOMMU overflow. */
262 if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
263 dev_info(dev, "Force SAC with mask %Lx\n", mask);
269 EXPORT_SYMBOL(dma_supported);
271 static int __init pci_iommu_init(void)
273 calgary_iommu_init();
285 void pci_iommu_shutdown(void)
287 gart_iommu_shutdown();
289 /* Must execute after PCI subsystem */
290 fs_initcall(pci_iommu_init);
293 /* Many VIA bridges seem to corrupt data for DAC. Disable it here */
295 static __devinit void via_no_dac(struct pci_dev *dev)
297 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
299 "PCI: VIA PCI bridge detected. Disabling DAC.\n");
303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);