arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         unsigned long size, len = 0;
  53         struct page *page;
  54         void *map;
  55         int ret;
  56
  57         do {
  58                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  59                 if (!ret)
  60                         break;
  61
  62                 offset = addr & (PAGE_SIZE - 1);
  63                 size = min(PAGE_SIZE - offset, n - len);
  64
  65                 map = kmap_atomic(page);
  66                 memcpy(to, map+offset, size);
  67                 kunmap_atomic(map);
  68                 put_page(page);
  69
  70                 len  += size;
  71                 to   += size;
  72                 addr += size;
  73
  74         } while (len < n);
  75
  76         return len;
  77 }
  78
  79 struct event_constraint {
  80         union {
  81                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  82                 u64             idxmsk64;
  83         };
  84         u64     code;
  85         u64     cmask;
  86         int     weight;
  87 };
  88
  89 struct amd_nb {
  90         int nb_id;  /* NorthBridge id */
  91         int refcnt; /* reference count */
  92         struct perf_event *owners[X86_PMC_IDX_MAX];
  93         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  94 };
  95
  96 #define MAX_LBR_ENTRIES         16
  97
  98 struct cpu_hw_events {
  99         /*
 100          * Generic x86 PMC bits
 101          */
 102         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 103         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 104         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     n_txn;
 110         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 111         u64                     tags[X86_PMC_IDX_MAX];
 112         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 113
 114         unsigned int            group_flag;
 115
 116         /*
 117          * Intel DebugStore bits
 118          */
 119         struct debug_store      *ds;
 120         u64                     pebs_enabled;
 121
 122         /*
 123          * Intel LBR bits
 124          */
 125         int                             lbr_users;
 126         void                            *lbr_context;
 127         struct perf_branch_stack        lbr_stack;
 128         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 129
 130         /*
 131          * AMD specific bits
 132          */
 133         struct amd_nb           *amd_nb;
 134 };
 135
 136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 137         { .idxmsk64 = (n) },            \
 138         .code = (c),                    \
 139         .cmask = (m),                   \
 140         .weight = (w),                  \
 141 }
 142
 143 #define EVENT_CONSTRAINT(c, n, m)       \
 144         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 145
 146 /*
 147  * Constraint on the Event code.
 148  */
 149 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 150         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 151
 152 /*
 153  * Constraint on the Event code + UMask + fixed-mask
 154  *
 155  * filter mask to validate fixed counter events.
 156  * the following filters disqualify for fixed counters:
 157  *  - inv
 158  *  - edge
 159  *  - cnt-mask
 160  *  The other filters are supported by fixed counters.
 161  *  The any-thread option is supported starting with v3.
 162  */
 163 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 164         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 165
 166 /*
 167  * Constraint on the Event code + UMask
 168  */
 169 #define INTEL_UEVENT_CONSTRAINT(c, n)   \
 170         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 171 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 172         INTEL_UEVENT_CONSTRAINT(c, n)
 173
 174 #define EVENT_CONSTRAINT_END            \
 175         EVENT_CONSTRAINT(0, 0, 0)
 176
 177 #define for_each_event_constraint(e, c) \
 178         for ((e) = (c); (e)->weight; (e)++)
 179
 180 union perf_capabilities {
 181         struct {
 182                 u64     lbr_format    : 6;
 183                 u64     pebs_trap     : 1;
 184                 u64     pebs_arch_reg : 1;
 185                 u64     pebs_format   : 4;
 186                 u64     smm_freeze    : 1;
 187         };
 188         u64     capabilities;
 189 };
 190
 191 /*
 192  * struct x86_pmu - generic x86 pmu
 193  */
 194 struct x86_pmu {
 195         /*
 196          * Generic x86 PMC bits
 197          */
 198         const char      *name;
 199         int             version;
 200         int             (*handle_irq)(struct pt_regs *);
 201         void            (*disable_all)(void);
 202         void            (*enable_all)(int added);
 203         void            (*enable)(struct perf_event *);
 204         void            (*disable)(struct perf_event *);
 205         int             (*hw_config)(struct perf_event *event);
 206         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 207         unsigned        eventsel;
 208         unsigned        perfctr;
 209         u64             (*event_map)(int);
 210         int             max_events;
 211         int             num_counters;
 212         int             num_counters_fixed;
 213         int             cntval_bits;
 214         u64             cntval_mask;
 215         int             apic;
 216         u64             max_period;
 217         struct event_constraint *
 218                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 219                                                  struct perf_event *event);
 220
 221         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 222                                                  struct perf_event *event);
 223         struct event_constraint *event_constraints;
 224         void            (*quirks)(void);
 225         int             perfctr_second_write;
 226
 227         int             (*cpu_prepare)(int cpu);
 228         void            (*cpu_starting)(int cpu);
 229         void            (*cpu_dying)(int cpu);
 230         void            (*cpu_dead)(int cpu);
 231
 232         /*
 233          * Intel Arch Perfmon v2+
 234          */
 235         u64                     intel_ctrl;
 236         union perf_capabilities intel_cap;
 237
 238         /*
 239          * Intel DebugStore bits
 240          */
 241         int             bts, pebs;
 242         int             bts_active, pebs_active;
 243         int             pebs_record_size;
 244         void            (*drain_pebs)(struct pt_regs *regs);
 245         struct event_constraint *pebs_constraints;
 246
 247         /*
 248          * Intel LBR
 249          */
 250         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 251         int             lbr_nr;                    /* hardware stack size */
 252 };
 253
 254 static struct x86_pmu x86_pmu __read_mostly;
 255
 256 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 257         .enabled = 1,
 258 };
 259
 260 static int x86_perf_event_set_period(struct perf_event *event);
 261
 262 /*
 263  * Generalized hw caching related hw_event table, filled
 264  * in on a per model basis. A value of 0 means
 265  * 'not supported', -1 means 'hw_event makes no sense on
 266  * this CPU', any other value means the raw hw_event
 267  * ID.
 268  */
 269
 270 #define C(x) PERF_COUNT_HW_CACHE_##x
 271
 272 static u64 __read_mostly hw_cache_event_ids
 273                                 [PERF_COUNT_HW_CACHE_MAX]
 274                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 275                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 276
 277 /*
 278  * Propagate event elapsed time into the generic event.
 279  * Can only be executed on the CPU where the event is active.
 280  * Returns the delta events processed.
 281  */
 282 static u64
 283 x86_perf_event_update(struct perf_event *event)
 284 {
 285         struct hw_perf_event *hwc = &event->hw;
 286         int shift = 64 - x86_pmu.cntval_bits;
 287         u64 prev_raw_count, new_raw_count;
 288         int idx = hwc->idx;
 289         s64 delta;
 290
 291         if (idx == X86_PMC_IDX_FIXED_BTS)
 292                 return 0;
 293
 294         /*
 295          * Careful: an NMI might modify the previous event value.
 296          *
 297          * Our tactic to handle this is to first atomically read and
 298          * exchange a new raw count - then add that new-prev delta
 299          * count to the generic event atomically:
 300          */
 301 again:
 302         prev_raw_count = local64_read(&hwc->prev_count);
 303         rdmsrl(hwc->event_base, new_raw_count);
 304
 305         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 306                                         new_raw_count) != prev_raw_count)
 307                 goto again;
 308
 309         /*
 310          * Now we have the new raw value and have updated the prev
 311          * timestamp already. We can now calculate the elapsed delta
 312          * (event-)time and add that to the generic event.
 313          *
 314          * Careful, not all hw sign-extends above the physical width
 315          * of the count.
 316          */
 317         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 318         delta >>= shift;
 319
 320         local64_add(delta, &event->count);
 321         local64_sub(delta, &hwc->period_left);
 322
 323         return new_raw_count;
 324 }
 325
 326 /* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */
 327 static inline int x86_pmu_addr_offset(int index)
 328 {
 329         if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
 330                 return index << 1;
 331         return index;
 332 }
 333
 334 static inline unsigned int x86_pmu_config_addr(int index)
 335 {
 336         return x86_pmu.eventsel + x86_pmu_addr_offset(index);
 337 }
 338
 339 static inline unsigned int x86_pmu_event_addr(int index)
 340 {
 341         return x86_pmu.perfctr + x86_pmu_addr_offset(index);
 342 }
 343
 344 static atomic_t active_events;
 345 static DEFINE_MUTEX(pmc_reserve_mutex);
 346
 347 #ifdef CONFIG_X86_LOCAL_APIC
 348
 349 static bool reserve_pmc_hardware(void)
 350 {
 351         int i;
 352
 353         for (i = 0; i < x86_pmu.num_counters; i++) {
 354                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 355                         goto perfctr_fail;
 356         }
 357
 358         for (i = 0; i < x86_pmu.num_counters; i++) {
 359                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 360                         goto eventsel_fail;
 361         }
 362
 363         return true;
 364
 365 eventsel_fail:
 366         for (i--; i >= 0; i--)
 367                 release_evntsel_nmi(x86_pmu_config_addr(i));
 368
 369         i = x86_pmu.num_counters;
 370
 371 perfctr_fail:
 372         for (i--; i >= 0; i--)
 373                 release_perfctr_nmi(x86_pmu_event_addr(i));
 374
 375         return false;
 376 }
 377
 378 static void release_pmc_hardware(void)
 379 {
 380         int i;
 381
 382         for (i = 0; i < x86_pmu.num_counters; i++) {
 383                 release_perfctr_nmi(x86_pmu_event_addr(i));
 384                 release_evntsel_nmi(x86_pmu_config_addr(i));
 385         }
 386 }
 387
 388 #else
 389
 390 static bool reserve_pmc_hardware(void) { return true; }
 391 static void release_pmc_hardware(void) {}
 392
 393 #endif
 394
 395 static bool check_hw_exists(void)
 396 {
 397         u64 val, val_new = 0;
 398         int i, reg, ret = 0;
 399
 400         /*
 401          * Check to see if the BIOS enabled any of the counters, if so
 402          * complain and bail.
 403          */
 404         for (i = 0; i < x86_pmu.num_counters; i++) {
 405                 reg = x86_pmu_config_addr(i);
 406                 ret = rdmsrl_safe(reg, &val);
 407                 if (ret)
 408                         goto msr_fail;
 409                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 410                         goto bios_fail;
 411         }
 412
 413         if (x86_pmu.num_counters_fixed) {
 414                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 415                 ret = rdmsrl_safe(reg, &val);
 416                 if (ret)
 417                         goto msr_fail;
 418                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 419                         if (val & (0x03 << i*4))
 420                                 goto bios_fail;
 421                 }
 422         }
 423
 424         /*
 425          * Now write a value and read it back to see if it matches,
 426          * this is needed to detect certain hardware emulators (qemu/kvm)
 427          * that don't trap on the MSR access and always return 0s.
 428          */
 429         val = 0xabcdUL;
 430         ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
 431         ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
 432         if (ret || val != val_new)
 433                 goto msr_fail;
 434
 435         return true;
 436
 437 bios_fail:
 438         printk(KERN_CONT "Broken BIOS detected, using software events only.\n");
 439         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
 440         return false;
 441
 442 msr_fail:
 443         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 444         return false;
 445 }
 446
 447 static void reserve_ds_buffers(void);
 448 static void release_ds_buffers(void);
 449
 450 static void hw_perf_event_destroy(struct perf_event *event)
 451 {
 452         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 453                 release_pmc_hardware();
 454                 release_ds_buffers();
 455                 mutex_unlock(&pmc_reserve_mutex);
 456         }
 457 }
 458
 459 static inline int x86_pmu_initialized(void)
 460 {
 461         return x86_pmu.handle_irq != NULL;
 462 }
 463
 464 static inline int
 465 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 466 {
 467         unsigned int cache_type, cache_op, cache_result;
 468         u64 config, val;
 469
 470         config = attr->config;
 471
 472         cache_type = (config >>  0) & 0xff;
 473         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 474                 return -EINVAL;
 475
 476         cache_op = (config >>  8) & 0xff;
 477         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 478                 return -EINVAL;
 479
 480         cache_result = (config >> 16) & 0xff;
 481         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 482                 return -EINVAL;
 483
 484         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 485
 486         if (val == 0)
 487                 return -ENOENT;
 488
 489         if (val == -1)
 490                 return -EINVAL;
 491
 492         hwc->config |= val;
 493
 494         return 0;
 495 }
 496
 497 static int x86_setup_perfctr(struct perf_event *event)
 498 {
 499         struct perf_event_attr *attr = &event->attr;
 500         struct hw_perf_event *hwc = &event->hw;
 501         u64 config;
 502
 503         if (!is_sampling_event(event)) {
 504                 hwc->sample_period = x86_pmu.max_period;
 505                 hwc->last_period = hwc->sample_period;
 506                 local64_set(&hwc->period_left, hwc->sample_period);
 507         } else {
 508                 /*
 509                  * If we have a PMU initialized but no APIC
 510                  * interrupts, we cannot sample hardware
 511                  * events (user-space has to fall back and
 512                  * sample via a hrtimer based software event):
 513                  */
 514                 if (!x86_pmu.apic)
 515                         return -EOPNOTSUPP;
 516         }
 517
 518         if (attr->type == PERF_TYPE_RAW)
 519                 return 0;
 520
 521         if (attr->type == PERF_TYPE_HW_CACHE)
 522                 return set_ext_hw_attr(hwc, attr);
 523
 524         if (attr->config >= x86_pmu.max_events)
 525                 return -EINVAL;
 526
 527         /*
 528          * The generic map:
 529          */
 530         config = x86_pmu.event_map(attr->config);
 531
 532         if (config == 0)
 533                 return -ENOENT;
 534
 535         if (config == -1LL)
 536                 return -EINVAL;
 537
 538         /*
 539          * Branch tracing:
 540          */
 541         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 542             (hwc->sample_period == 1)) {
 543                 /* BTS is not supported by this architecture. */
 544                 if (!x86_pmu.bts_active)
 545                         return -EOPNOTSUPP;
 546
 547                 /* BTS is currently only allowed for user-mode. */
 548                 if (!attr->exclude_kernel)
 549                         return -EOPNOTSUPP;
 550         }
 551
 552         hwc->config |= config;
 553
 554         return 0;
 555 }
 556
 557 static int x86_pmu_hw_config(struct perf_event *event)
 558 {
 559         if (event->attr.precise_ip) {
 560                 int precise = 0;
 561
 562                 /* Support for constant skid */
 563                 if (x86_pmu.pebs_active) {
 564                         precise++;
 565
 566                         /* Support for IP fixup */
 567                         if (x86_pmu.lbr_nr)
 568                                 precise++;
 569                 }
 570
 571                 if (event->attr.precise_ip > precise)
 572                         return -EOPNOTSUPP;
 573         }
 574
 575         /*
 576          * Generate PMC IRQs:
 577          * (keep 'enabled' bit clear for now)
 578          */
 579         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 580
 581         /*
 582          * Count user and OS events unless requested not to
 583          */
 584         if (!event->attr.exclude_user)
 585                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 586         if (!event->attr.exclude_kernel)
 587                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 588
 589         if (event->attr.type == PERF_TYPE_RAW)
 590                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 591
 592         return x86_setup_perfctr(event);
 593 }
 594
 595 /*
 596  * Setup the hardware configuration for a given attr_type
 597  */
 598 static int __x86_pmu_event_init(struct perf_event *event)
 599 {
 600         int err;
 601
 602         if (!x86_pmu_initialized())
 603                 return -ENODEV;
 604
 605         err = 0;
 606         if (!atomic_inc_not_zero(&active_events)) {
 607                 mutex_lock(&pmc_reserve_mutex);
 608                 if (atomic_read(&active_events) == 0) {
 609                         if (!reserve_pmc_hardware())
 610                                 err = -EBUSY;
 611                         else
 612                                 reserve_ds_buffers();
 613                 }
 614                 if (!err)
 615                         atomic_inc(&active_events);
 616                 mutex_unlock(&pmc_reserve_mutex);
 617         }
 618         if (err)
 619                 return err;
 620
 621         event->destroy = hw_perf_event_destroy;
 622
 623         event->hw.idx = -1;
 624         event->hw.last_cpu = -1;
 625         event->hw.last_tag = ~0ULL;
 626
 627         return x86_pmu.hw_config(event);
 628 }
 629
 630 static void x86_pmu_disable_all(void)
 631 {
 632         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 633         int idx;
 634
 635         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 636                 u64 val;
 637
 638                 if (!test_bit(idx, cpuc->active_mask))
 639                         continue;
 640                 rdmsrl(x86_pmu_config_addr(idx), val);
 641                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 642                         continue;
 643                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 644                 wrmsrl(x86_pmu_config_addr(idx), val);
 645         }
 646 }
 647
 648 static void x86_pmu_disable(struct pmu *pmu)
 649 {
 650         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 651
 652         if (!x86_pmu_initialized())
 653                 return;
 654
 655         if (!cpuc->enabled)
 656                 return;
 657
 658         cpuc->n_added = 0;
 659         cpuc->enabled = 0;
 660         barrier();
 661
 662         x86_pmu.disable_all();
 663 }
 664
 665 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 666                                           u64 enable_mask)
 667 {
 668         wrmsrl(hwc->config_base, hwc->config | enable_mask);
 669 }
 670
 671 static void x86_pmu_enable_all(int added)
 672 {
 673         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 674         int idx;
 675
 676         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 677                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 678
 679                 if (!test_bit(idx, cpuc->active_mask))
 680                         continue;
 681
 682                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 683         }
 684 }
 685
 686 static struct pmu pmu;
 687
 688 static inline int is_x86_event(struct perf_event *event)
 689 {
 690         return event->pmu == &pmu;
 691 }
 692
 693 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 694 {
 695         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 696         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 697         int i, j, w, wmax, num = 0;
 698         struct hw_perf_event *hwc;
 699
 700         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 701
 702         for (i = 0; i < n; i++) {
 703                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 704                 constraints[i] = c;
 705         }
 706
 707         /*
 708          * fastpath, try to reuse previous register
 709          */
 710         for (i = 0; i < n; i++) {
 711                 hwc = &cpuc->event_list[i]->hw;
 712                 c = constraints[i];
 713
 714                 /* never assigned */
 715                 if (hwc->idx == -1)
 716                         break;
 717
 718                 /* constraint still honored */
 719                 if (!test_bit(hwc->idx, c->idxmsk))
 720                         break;
 721
 722                 /* not already used */
 723                 if (test_bit(hwc->idx, used_mask))
 724                         break;
 725
 726                 __set_bit(hwc->idx, used_mask);
 727                 if (assign)
 728                         assign[i] = hwc->idx;
 729         }
 730         if (i == n)
 731                 goto done;
 732
 733         /*
 734          * begin slow path
 735          */
 736
 737         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 738
 739         /*
 740          * weight = number of possible counters
 741          *
 742          * 1    = most constrained, only works on one counter
 743          * wmax = least constrained, works on any counter
 744          *
 745          * assign events to counters starting with most
 746          * constrained events.
 747          */
 748         wmax = x86_pmu.num_counters;
 749
 750         /*
 751          * when fixed event counters are present,
 752          * wmax is incremented by 1 to account
 753          * for one more choice
 754          */
 755         if (x86_pmu.num_counters_fixed)
 756                 wmax++;
 757
 758         for (w = 1, num = n; num && w <= wmax; w++) {
 759                 /* for each event */
 760                 for (i = 0; num && i < n; i++) {
 761                         c = constraints[i];
 762                         hwc = &cpuc->event_list[i]->hw;
 763
 764                         if (c->weight != w)
 765                                 continue;
 766
 767                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 768                                 if (!test_bit(j, used_mask))
 769                                         break;
 770                         }
 771
 772                         if (j == X86_PMC_IDX_MAX)
 773                                 break;
 774
 775                         __set_bit(j, used_mask);
 776
 777                         if (assign)
 778                                 assign[i] = j;
 779                         num--;
 780                 }
 781         }
 782 done:
 783         /*
 784          * scheduling failed or is just a simulation,
 785          * free resources if necessary
 786          */
 787         if (!assign || num) {
 788                 for (i = 0; i < n; i++) {
 789                         if (x86_pmu.put_event_constraints)
 790                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 791                 }
 792         }
 793         return num ? -ENOSPC : 0;
 794 }
 795
 796 /*
 797  * dogrp: true if must collect siblings events (group)
 798  * returns total number of events and error code
 799  */
 800 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 801 {
 802         struct perf_event *event;
 803         int n, max_count;
 804
 805         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 806
 807         /* current number of events already accepted */
 808         n = cpuc->n_events;
 809
 810         if (is_x86_event(leader)) {
 811                 if (n >= max_count)
 812                         return -ENOSPC;
 813                 cpuc->event_list[n] = leader;
 814                 n++;
 815         }
 816         if (!dogrp)
 817                 return n;
 818
 819         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 820                 if (!is_x86_event(event) ||
 821                     event->state <= PERF_EVENT_STATE_OFF)
 822                         continue;
 823
 824                 if (n >= max_count)
 825                         return -ENOSPC;
 826
 827                 cpuc->event_list[n] = event;
 828                 n++;
 829         }
 830         return n;
 831 }
 832
 833 static inline void x86_assign_hw_event(struct perf_event *event,
 834                                 struct cpu_hw_events *cpuc, int i)
 835 {
 836         struct hw_perf_event *hwc = &event->hw;
 837
 838         hwc->idx = cpuc->assign[i];
 839         hwc->last_cpu = smp_processor_id();
 840         hwc->last_tag = ++cpuc->tags[i];
 841
 842         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 843                 hwc->config_base = 0;
 844                 hwc->event_base = 0;
 845         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 846                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 847                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0;
 848         } else {
 849                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 850                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 851         }
 852 }
 853
 854 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 855                                         struct cpu_hw_events *cpuc,
 856                                         int i)
 857 {
 858         return hwc->idx == cpuc->assign[i] &&
 859                 hwc->last_cpu == smp_processor_id() &&
 860                 hwc->last_tag == cpuc->tags[i];
 861 }
 862
 863 static void x86_pmu_start(struct perf_event *event, int flags);
 864 static void x86_pmu_stop(struct perf_event *event, int flags);
 865
 866 static void x86_pmu_enable(struct pmu *pmu)
 867 {
 868         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 869         struct perf_event *event;
 870         struct hw_perf_event *hwc;
 871         int i, added = cpuc->n_added;
 872
 873         if (!x86_pmu_initialized())
 874                 return;
 875
 876         if (cpuc->enabled)
 877                 return;
 878
 879         if (cpuc->n_added) {
 880                 int n_running = cpuc->n_events - cpuc->n_added;
 881                 /*
 882                  * apply assignment obtained either from
 883                  * hw_perf_group_sched_in() or x86_pmu_enable()
 884                  *
 885                  * step1: save events moving to new counters
 886                  * step2: reprogram moved events into new counters
 887                  */
 888                 for (i = 0; i < n_running; i++) {
 889                         event = cpuc->event_list[i];
 890                         hwc = &event->hw;
 891
 892                         /*
 893                          * we can avoid reprogramming counter if:
 894                          * - assigned same counter as last time
 895                          * - running on same CPU as last time
 896                          * - no other event has used the counter since
 897                          */
 898                         if (hwc->idx == -1 ||
 899                             match_prev_assignment(hwc, cpuc, i))
 900                                 continue;
 901
 902                         /*
 903                          * Ensure we don't accidentally enable a stopped
 904                          * counter simply because we rescheduled.
 905                          */
 906                         if (hwc->state & PERF_HES_STOPPED)
 907                                 hwc->state |= PERF_HES_ARCH;
 908
 909                         x86_pmu_stop(event, PERF_EF_UPDATE);
 910                 }
 911
 912                 for (i = 0; i < cpuc->n_events; i++) {
 913                         event = cpuc->event_list[i];
 914                         hwc = &event->hw;
 915
 916                         if (!match_prev_assignment(hwc, cpuc, i))
 917                                 x86_assign_hw_event(event, cpuc, i);
 918                         else if (i < n_running)
 919                                 continue;
 920
 921                         if (hwc->state & PERF_HES_ARCH)
 922                                 continue;
 923
 924                         x86_pmu_start(event, PERF_EF_RELOAD);
 925                 }
 926                 cpuc->n_added = 0;
 927                 perf_events_lapic_init();
 928         }
 929
 930         cpuc->enabled = 1;
 931         barrier();
 932
 933         x86_pmu.enable_all(added);
 934 }
 935
 936 static inline void x86_pmu_disable_event(struct perf_event *event)
 937 {
 938         struct hw_perf_event *hwc = &event->hw;
 939
 940         wrmsrl(hwc->config_base, hwc->config);
 941 }
 942
 943 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 944
 945 /*
 946  * Set the next IRQ period, based on the hwc->period_left value.
 947  * To be called with the event disabled in hw:
 948  */
 949 static int
 950 x86_perf_event_set_period(struct perf_event *event)
 951 {
 952         struct hw_perf_event *hwc = &event->hw;
 953         s64 left = local64_read(&hwc->period_left);
 954         s64 period = hwc->sample_period;
 955         int ret = 0, idx = hwc->idx;
 956
 957         if (idx == X86_PMC_IDX_FIXED_BTS)
 958                 return 0;
 959
 960         /*
 961          * If we are way outside a reasonable range then just skip forward:
 962          */
 963         if (unlikely(left <= -period)) {
 964                 left = period;
 965                 local64_set(&hwc->period_left, left);
 966                 hwc->last_period = period;
 967                 ret = 1;
 968         }
 969
 970         if (unlikely(left <= 0)) {
 971                 left += period;
 972                 local64_set(&hwc->period_left, left);
 973                 hwc->last_period = period;
 974                 ret = 1;
 975         }
 976         /*
 977          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 978          */
 979         if (unlikely(left < 2))
 980                 left = 2;
 981
 982         if (left > x86_pmu.max_period)
 983                 left = x86_pmu.max_period;
 984
 985         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 986
 987         /*
 988          * The hw event starts counting from this event offset,
 989          * mark it to be able to extra future deltas:
 990          */
 991         local64_set(&hwc->prev_count, (u64)-left);
 992
 993         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
 994
 995         /*
 996          * Due to erratum on certan cpu we need
 997          * a second write to be sure the register
 998          * is updated properly
 999          */
1000         if (x86_pmu.perfctr_second_write) {
1001                 wrmsrl(hwc->event_base,
1002                         (u64)(-left) & x86_pmu.cntval_mask);
1003         }
1004
1005         perf_event_update_userpage(event);
1006
1007         return ret;
1008 }
1009
1010 static void x86_pmu_enable_event(struct perf_event *event)
1011 {
1012         if (__this_cpu_read(cpu_hw_events.enabled))
1013                 __x86_pmu_enable_event(&event->hw,
1014                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1015 }
1016
1017 /*
1018  * Add a single event to the PMU.
1019  *
1020  * The event is added to the group of enabled events
1021  * but only if it can be scehduled with existing events.
1022  */
1023 static int x86_pmu_add(struct perf_event *event, int flags)
1024 {
1025         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1026         struct hw_perf_event *hwc;
1027         int assign[X86_PMC_IDX_MAX];
1028         int n, n0, ret;
1029
1030         hwc = &event->hw;
1031
1032         perf_pmu_disable(event->pmu);
1033         n0 = cpuc->n_events;
1034         ret = n = collect_events(cpuc, event, false);
1035         if (ret < 0)
1036                 goto out;
1037
1038         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1039         if (!(flags & PERF_EF_START))
1040                 hwc->state |= PERF_HES_ARCH;
1041
1042         /*
1043          * If group events scheduling transaction was started,
1044          * skip the schedulability test here, it will be peformed
1045          * at commit time (->commit_txn) as a whole
1046          */
1047         if (cpuc->group_flag & PERF_EVENT_TXN)
1048                 goto done_collect;
1049
1050         ret = x86_pmu.schedule_events(cpuc, n, assign);
1051         if (ret)
1052                 goto out;
1053         /*
1054          * copy new assignment, now we know it is possible
1055          * will be used by hw_perf_enable()
1056          */
1057         memcpy(cpuc->assign, assign, n*sizeof(int));
1058
1059 done_collect:
1060         cpuc->n_events = n;
1061         cpuc->n_added += n - n0;
1062         cpuc->n_txn += n - n0;
1063
1064         ret = 0;
1065 out:
1066         perf_pmu_enable(event->pmu);
1067         return ret;
1068 }
1069
1070 static void x86_pmu_start(struct perf_event *event, int flags)
1071 {
1072         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1073         int idx = event->hw.idx;
1074
1075         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1076                 return;
1077
1078         if (WARN_ON_ONCE(idx == -1))
1079                 return;
1080
1081         if (flags & PERF_EF_RELOAD) {
1082                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1083                 x86_perf_event_set_period(event);
1084         }
1085
1086         event->hw.state = 0;
1087
1088         cpuc->events[idx] = event;
1089         __set_bit(idx, cpuc->active_mask);
1090         __set_bit(idx, cpuc->running);
1091         x86_pmu.enable(event);
1092         perf_event_update_userpage(event);
1093 }
1094
1095 void perf_event_print_debug(void)
1096 {
1097         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1098         u64 pebs;
1099         struct cpu_hw_events *cpuc;
1100         unsigned long flags;
1101         int cpu, idx;
1102
1103         if (!x86_pmu.num_counters)
1104                 return;
1105
1106         local_irq_save(flags);
1107
1108         cpu = smp_processor_id();
1109         cpuc = &per_cpu(cpu_hw_events, cpu);
1110
1111         if (x86_pmu.version >= 2) {
1112                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1113                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1114                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1115                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1116                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1117
1118                 pr_info("\n");
1119                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1120                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1121                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1122                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1123                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1124         }
1125         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1126
1127         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1128                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1129                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1130
1131                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1132
1133                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1134                         cpu, idx, pmc_ctrl);
1135                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1136                         cpu, idx, pmc_count);
1137                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1138                         cpu, idx, prev_left);
1139         }
1140         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1141                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1142
1143                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1144                         cpu, idx, pmc_count);
1145         }
1146         local_irq_restore(flags);
1147 }
1148
1149 static void x86_pmu_stop(struct perf_event *event, int flags)
1150 {
1151         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1152         struct hw_perf_event *hwc = &event->hw;
1153
1154         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1155                 x86_pmu.disable(event);
1156                 cpuc->events[hwc->idx] = NULL;
1157                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1158                 hwc->state |= PERF_HES_STOPPED;
1159         }
1160
1161         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1162                 /*
1163                  * Drain the remaining delta count out of a event
1164                  * that we are disabling:
1165                  */
1166                 x86_perf_event_update(event);
1167                 hwc->state |= PERF_HES_UPTODATE;
1168         }
1169 }
1170
1171 static void x86_pmu_del(struct perf_event *event, int flags)
1172 {
1173         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1174         int i;
1175
1176         /*
1177          * If we're called during a txn, we don't need to do anything.
1178          * The events never got scheduled and ->cancel_txn will truncate
1179          * the event_list.
1180          */
1181         if (cpuc->group_flag & PERF_EVENT_TXN)
1182                 return;
1183
1184         x86_pmu_stop(event, PERF_EF_UPDATE);
1185
1186         for (i = 0; i < cpuc->n_events; i++) {
1187                 if (event == cpuc->event_list[i]) {
1188
1189                         if (x86_pmu.put_event_constraints)
1190                                 x86_pmu.put_event_constraints(cpuc, event);
1191
1192                         while (++i < cpuc->n_events)
1193                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1194
1195                         --cpuc->n_events;
1196                         break;
1197                 }
1198         }
1199         perf_event_update_userpage(event);
1200 }
1201
1202 static int x86_pmu_handle_irq(struct pt_regs *regs)
1203 {
1204         struct perf_sample_data data;
1205         struct cpu_hw_events *cpuc;
1206         struct perf_event *event;
1207         int idx, handled = 0;
1208         u64 val;
1209
1210         perf_sample_data_init(&data, 0);
1211
1212         cpuc = &__get_cpu_var(cpu_hw_events);
1213
1214         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1215                 if (!test_bit(idx, cpuc->active_mask)) {
1216                         /*
1217                          * Though we deactivated the counter some cpus
1218                          * might still deliver spurious interrupts still
1219                          * in flight. Catch them:
1220                          */
1221                         if (__test_and_clear_bit(idx, cpuc->running))
1222                                 handled++;
1223                         continue;
1224                 }
1225
1226                 event = cpuc->events[idx];
1227
1228                 val = x86_perf_event_update(event);
1229                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1230                         continue;
1231
1232                 /*
1233                  * event overflow
1234                  */
1235                 handled++;
1236                 data.period     = event->hw.last_period;
1237
1238                 if (!x86_perf_event_set_period(event))
1239                         continue;
1240
1241                 if (perf_event_overflow(event, 1, &data, regs))
1242                         x86_pmu_stop(event, 0);
1243         }
1244
1245         if (handled)
1246                 inc_irq_stat(apic_perf_irqs);
1247
1248         return handled;
1249 }
1250
1251 void perf_events_lapic_init(void)
1252 {
1253         if (!x86_pmu.apic || !x86_pmu_initialized())
1254                 return;
1255
1256         /*
1257          * Always use NMI for PMU
1258          */
1259         apic_write(APIC_LVTPC, APIC_DM_NMI);
1260 }
1261
1262 struct pmu_nmi_state {
1263         unsigned int    marked;
1264         int             handled;
1265 };
1266
1267 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1268
1269 static int __kprobes
1270 perf_event_nmi_handler(struct notifier_block *self,
1271                          unsigned long cmd, void *__args)
1272 {
1273         struct die_args *args = __args;
1274         unsigned int this_nmi;
1275         int handled;
1276
1277         if (!atomic_read(&active_events))
1278                 return NOTIFY_DONE;
1279
1280         switch (cmd) {
1281         case DIE_NMI:
1282                 break;
1283         case DIE_NMIUNKNOWN:
1284                 this_nmi = percpu_read(irq_stat.__nmi_count);
1285                 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1286                         /* let the kernel handle the unknown nmi */
1287                         return NOTIFY_DONE;
1288                 /*
1289                  * This one is a PMU back-to-back nmi. Two events
1290                  * trigger 'simultaneously' raising two back-to-back
1291                  * NMIs. If the first NMI handles both, the latter
1292                  * will be empty and daze the CPU. So, we drop it to
1293                  * avoid false-positive 'unknown nmi' messages.
1294                  */
1295                 return NOTIFY_STOP;
1296         default:
1297                 return NOTIFY_DONE;
1298         }
1299
1300         apic_write(APIC_LVTPC, APIC_DM_NMI);
1301
1302         handled = x86_pmu.handle_irq(args->regs);
1303         if (!handled)
1304                 return NOTIFY_DONE;
1305
1306         this_nmi = percpu_read(irq_stat.__nmi_count);
1307         if ((handled > 1) ||
1308                 /* the next nmi could be a back-to-back nmi */
1309             ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1310              (__this_cpu_read(pmu_nmi.handled) > 1))) {
1311                 /*
1312                  * We could have two subsequent back-to-back nmis: The
1313                  * first handles more than one counter, the 2nd
1314                  * handles only one counter and the 3rd handles no
1315                  * counter.
1316                  *
1317                  * This is the 2nd nmi because the previous was
1318                  * handling more than one counter. We will mark the
1319                  * next (3rd) and then drop it if unhandled.
1320                  */
1321                 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1322                 __this_cpu_write(pmu_nmi.handled, handled);
1323         }
1324
1325         return NOTIFY_STOP;
1326 }
1327
1328 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1329         .notifier_call          = perf_event_nmi_handler,
1330         .next                   = NULL,
1331         .priority               = NMI_LOCAL_LOW_PRIOR,
1332 };
1333
1334 static struct event_constraint unconstrained;
1335 static struct event_constraint emptyconstraint;
1336
1337 static struct event_constraint *
1338 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1339 {
1340         struct event_constraint *c;
1341
1342         if (x86_pmu.event_constraints) {
1343                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1344                         if ((event->hw.config & c->cmask) == c->code)
1345                                 return c;
1346                 }
1347         }
1348
1349         return &unconstrained;
1350 }
1351
1352 #include "perf_event_amd.c"
1353 #include "perf_event_p6.c"
1354 #include "perf_event_p4.c"
1355 #include "perf_event_intel_lbr.c"
1356 #include "perf_event_intel_ds.c"
1357 #include "perf_event_intel.c"
1358
1359 static int __cpuinit
1360 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1361 {
1362         unsigned int cpu = (long)hcpu;
1363         int ret = NOTIFY_OK;
1364
1365         switch (action & ~CPU_TASKS_FROZEN) {
1366         case CPU_UP_PREPARE:
1367                 if (x86_pmu.cpu_prepare)
1368                         ret = x86_pmu.cpu_prepare(cpu);
1369                 break;
1370
1371         case CPU_STARTING:
1372                 if (x86_pmu.cpu_starting)
1373                         x86_pmu.cpu_starting(cpu);
1374                 break;
1375
1376         case CPU_DYING:
1377                 if (x86_pmu.cpu_dying)
1378                         x86_pmu.cpu_dying(cpu);
1379                 break;
1380
1381         case CPU_UP_CANCELED:
1382         case CPU_DEAD:
1383                 if (x86_pmu.cpu_dead)
1384                         x86_pmu.cpu_dead(cpu);
1385                 break;
1386
1387         default:
1388                 break;
1389         }
1390
1391         return ret;
1392 }
1393
1394 static void __init pmu_check_apic(void)
1395 {
1396         if (cpu_has_apic)
1397                 return;
1398
1399         x86_pmu.apic = 0;
1400         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1401         pr_info("no hardware sampling interrupt available.\n");
1402 }
1403
1404 static int __init init_hw_perf_events(void)
1405 {
1406         struct event_constraint *c;
1407         int err;
1408
1409         pr_info("Performance Events: ");
1410
1411         switch (boot_cpu_data.x86_vendor) {
1412         case X86_VENDOR_INTEL:
1413                 err = intel_pmu_init();
1414                 break;
1415         case X86_VENDOR_AMD:
1416                 err = amd_pmu_init();
1417                 break;
1418         default:
1419                 return 0;
1420         }
1421         if (err != 0) {
1422                 pr_cont("no PMU driver, software events only.\n");
1423                 return 0;
1424         }
1425
1426         pmu_check_apic();
1427
1428         /* sanity check that the hardware exists or is emulated */
1429         if (!check_hw_exists())
1430                 return 0;
1431
1432         pr_cont("%s PMU driver.\n", x86_pmu.name);
1433
1434         if (x86_pmu.quirks)
1435                 x86_pmu.quirks();
1436
1437         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1438                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1439                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1440                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1441         }
1442         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1443
1444         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1445                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1446                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1447                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1448         }
1449
1450         x86_pmu.intel_ctrl |=
1451                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1452
1453         perf_events_lapic_init();
1454         register_die_notifier(&perf_event_nmi_notifier);
1455
1456         unconstrained = (struct event_constraint)
1457                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1458                                    0, x86_pmu.num_counters);
1459
1460         if (x86_pmu.event_constraints) {
1461                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1462                         if (c->cmask != X86_RAW_EVENT_MASK)
1463                                 continue;
1464
1465                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1466                         c->weight += x86_pmu.num_counters;
1467                 }
1468         }
1469
1470         pr_info("... version:                %d\n",     x86_pmu.version);
1471         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1472         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1473         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1474         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1475         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1476         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1477
1478         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1479         perf_cpu_notifier(x86_pmu_notifier);
1480
1481         return 0;
1482 }
1483 early_initcall(init_hw_perf_events);
1484
1485 static inline void x86_pmu_read(struct perf_event *event)
1486 {
1487         x86_perf_event_update(event);
1488 }
1489
1490 /*
1491  * Start group events scheduling transaction
1492  * Set the flag to make pmu::enable() not perform the
1493  * schedulability test, it will be performed at commit time
1494  */
1495 static void x86_pmu_start_txn(struct pmu *pmu)
1496 {
1497         perf_pmu_disable(pmu);
1498         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1499         __this_cpu_write(cpu_hw_events.n_txn, 0);
1500 }
1501
1502 /*
1503  * Stop group events scheduling transaction
1504  * Clear the flag and pmu::enable() will perform the
1505  * schedulability test.
1506  */
1507 static void x86_pmu_cancel_txn(struct pmu *pmu)
1508 {
1509         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1510         /*
1511          * Truncate the collected events.
1512          */
1513         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1514         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1515         perf_pmu_enable(pmu);
1516 }
1517
1518 /*
1519  * Commit group events scheduling transaction
1520  * Perform the group schedulability test as a whole
1521  * Return 0 if success
1522  */
1523 static int x86_pmu_commit_txn(struct pmu *pmu)
1524 {
1525         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1526         int assign[X86_PMC_IDX_MAX];
1527         int n, ret;
1528
1529         n = cpuc->n_events;
1530
1531         if (!x86_pmu_initialized())
1532                 return -EAGAIN;
1533
1534         ret = x86_pmu.schedule_events(cpuc, n, assign);
1535         if (ret)
1536                 return ret;
1537
1538         /*
1539          * copy new assignment, now we know it is possible
1540          * will be used by hw_perf_enable()
1541          */
1542         memcpy(cpuc->assign, assign, n*sizeof(int));
1543
1544         cpuc->group_flag &= ~PERF_EVENT_TXN;
1545         perf_pmu_enable(pmu);
1546         return 0;
1547 }
1548
1549 /*
1550  * validate that we can schedule this event
1551  */
1552 static int validate_event(struct perf_event *event)
1553 {
1554         struct cpu_hw_events *fake_cpuc;
1555         struct event_constraint *c;
1556         int ret = 0;
1557
1558         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1559         if (!fake_cpuc)
1560                 return -ENOMEM;
1561
1562         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1563
1564         if (!c || !c->weight)
1565                 ret = -ENOSPC;
1566
1567         if (x86_pmu.put_event_constraints)
1568                 x86_pmu.put_event_constraints(fake_cpuc, event);
1569
1570         kfree(fake_cpuc);
1571
1572         return ret;
1573 }
1574
1575 /*
1576  * validate a single event group
1577  *
1578  * validation include:
1579  *      - check events are compatible which each other
1580  *      - events do not compete for the same counter
1581  *      - number of events <= number of counters
1582  *
1583  * validation ensures the group can be loaded onto the
1584  * PMU if it was the only group available.
1585  */
1586 static int validate_group(struct perf_event *event)
1587 {
1588         struct perf_event *leader = event->group_leader;
1589         struct cpu_hw_events *fake_cpuc;
1590         int ret, n;
1591
1592         ret = -ENOMEM;
1593         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1594         if (!fake_cpuc)
1595                 goto out;
1596
1597         /*
1598          * the event is not yet connected with its
1599          * siblings therefore we must first collect
1600          * existing siblings, then add the new event
1601          * before we can simulate the scheduling
1602          */
1603         ret = -ENOSPC;
1604         n = collect_events(fake_cpuc, leader, true);
1605         if (n < 0)
1606                 goto out_free;
1607
1608         fake_cpuc->n_events = n;
1609         n = collect_events(fake_cpuc, event, false);
1610         if (n < 0)
1611                 goto out_free;
1612
1613         fake_cpuc->n_events = n;
1614
1615         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1616
1617 out_free:
1618         kfree(fake_cpuc);
1619 out:
1620         return ret;
1621 }
1622
1623 static int x86_pmu_event_init(struct perf_event *event)
1624 {
1625         struct pmu *tmp;
1626         int err;
1627
1628         switch (event->attr.type) {
1629         case PERF_TYPE_RAW:
1630         case PERF_TYPE_HARDWARE:
1631         case PERF_TYPE_HW_CACHE:
1632                 break;
1633
1634         default:
1635                 return -ENOENT;
1636         }
1637
1638         err = __x86_pmu_event_init(event);
1639         if (!err) {
1640                 /*
1641                  * we temporarily connect event to its pmu
1642                  * such that validate_group() can classify
1643                  * it as an x86 event using is_x86_event()
1644                  */
1645                 tmp = event->pmu;
1646                 event->pmu = &pmu;
1647
1648                 if (event->group_leader != event)
1649                         err = validate_group(event);
1650                 else
1651                         err = validate_event(event);
1652
1653                 event->pmu = tmp;
1654         }
1655         if (err) {
1656                 if (event->destroy)
1657                         event->destroy(event);
1658         }
1659
1660         return err;
1661 }
1662
1663 static struct pmu pmu = {
1664         .pmu_enable     = x86_pmu_enable,
1665         .pmu_disable    = x86_pmu_disable,
1666
1667         .event_init     = x86_pmu_event_init,
1668
1669         .add            = x86_pmu_add,
1670         .del            = x86_pmu_del,
1671         .start          = x86_pmu_start,
1672         .stop           = x86_pmu_stop,
1673         .read           = x86_pmu_read,
1674
1675         .start_txn      = x86_pmu_start_txn,
1676         .cancel_txn     = x86_pmu_cancel_txn,
1677         .commit_txn     = x86_pmu_commit_txn,
1678 };
1679
1680 /*
1681  * callchain support
1682  */
1683
1684 static void
1685 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1686 {
1687         /* Ignore warnings */
1688 }
1689
1690 static void backtrace_warning(void *data, char *msg)
1691 {
1692         /* Ignore warnings */
1693 }
1694
1695 static int backtrace_stack(void *data, char *name)
1696 {
1697         return 0;
1698 }
1699
1700 static void backtrace_address(void *data, unsigned long addr, int reliable)
1701 {
1702         struct perf_callchain_entry *entry = data;
1703
1704         perf_callchain_store(entry, addr);
1705 }
1706
1707 static const struct stacktrace_ops backtrace_ops = {
1708         .warning                = backtrace_warning,
1709         .warning_symbol         = backtrace_warning_symbol,
1710         .stack                  = backtrace_stack,
1711         .address                = backtrace_address,
1712         .walk_stack             = print_context_stack_bp,
1713 };
1714
1715 void
1716 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1717 {
1718         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1719                 /* TODO: We don't support guest os callchain now */
1720                 return;
1721         }
1722
1723         perf_callchain_store(entry, regs->ip);
1724
1725         dump_trace(NULL, regs, NULL, &backtrace_ops, entry);
1726 }
1727
1728 #ifdef CONFIG_COMPAT
1729 static inline int
1730 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1731 {
1732         /* 32-bit process in 64-bit kernel. */
1733         struct stack_frame_ia32 frame;
1734         const void __user *fp;
1735
1736         if (!test_thread_flag(TIF_IA32))
1737                 return 0;
1738
1739         fp = compat_ptr(regs->bp);
1740         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1741                 unsigned long bytes;
1742                 frame.next_frame     = 0;
1743                 frame.return_address = 0;
1744
1745                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1746                 if (bytes != sizeof(frame))
1747                         break;
1748
1749                 if (fp < compat_ptr(regs->sp))
1750                         break;
1751
1752                 perf_callchain_store(entry, frame.return_address);
1753                 fp = compat_ptr(frame.next_frame);
1754         }
1755         return 1;
1756 }
1757 #else
1758 static inline int
1759 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1760 {
1761     return 0;
1762 }
1763 #endif
1764
1765 void
1766 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1767 {
1768         struct stack_frame frame;
1769         const void __user *fp;
1770
1771         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1772                 /* TODO: We don't support guest os callchain now */
1773                 return;
1774         }
1775
1776         fp = (void __user *)regs->bp;
1777
1778         perf_callchain_store(entry, regs->ip);
1779
1780         if (perf_callchain_user32(regs, entry))
1781                 return;
1782
1783         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1784                 unsigned long bytes;
1785                 frame.next_frame             = NULL;
1786                 frame.return_address = 0;
1787
1788                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1789                 if (bytes != sizeof(frame))
1790                         break;
1791
1792                 if ((unsigned long)fp < regs->sp)
1793                         break;
1794
1795                 perf_callchain_store(entry, frame.return_address);
1796                 fp = frame.next_frame;
1797         }
1798 }
1799
1800 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1801 {
1802         unsigned long ip;
1803
1804         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1805                 ip = perf_guest_cbs->get_guest_ip();
1806         else
1807                 ip = instruction_pointer(regs);
1808
1809         return ip;
1810 }
1811
1812 unsigned long perf_misc_flags(struct pt_regs *regs)
1813 {
1814         int misc = 0;
1815
1816         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1817                 if (perf_guest_cbs->is_user_mode())
1818                         misc |= PERF_RECORD_MISC_GUEST_USER;
1819                 else
1820                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1821         } else {
1822                 if (user_mode(regs))
1823                         misc |= PERF_RECORD_MISC_USER;
1824                 else
1825                         misc |= PERF_RECORD_MISC_KERNEL;
1826         }
1827
1828         if (regs->flags & PERF_EFLAGS_EXACT)
1829                 misc |= PERF_RECORD_MISC_EXACT_IP;
1830
1831         return misc;
1832 }