1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/archrandom.h>
19 #include <asm/hypervisor.h>
20 #include <asm/processor.h>
21 #include <asm/sections.h>
22 #include <linux/topology.h>
23 #include <linux/cpumask.h>
24 #include <asm/pgtable.h>
25 #include <linux/atomic.h>
26 #include <asm/proto.h>
27 #include <asm/setup.h>
32 #include <linux/numa.h>
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/uv/uv.h>
45 /* all of these masks are initialized in setup_cpu_local_masks() */
46 cpumask_var_t cpu_initialized_mask;
47 cpumask_var_t cpu_callout_mask;
48 cpumask_var_t cpu_callin_mask;
50 /* representing cpus for which sibling maps can be computed */
51 cpumask_var_t cpu_sibling_setup_mask;
53 /* correctly size the local cpu masks */
54 void __init setup_cpu_local_masks(void)
56 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
57 alloc_bootmem_cpumask_var(&cpu_callin_mask);
58 alloc_bootmem_cpumask_var(&cpu_callout_mask);
59 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
62 static void __cpuinit default_init(struct cpuinfo_x86 *c)
65 cpu_detect_cache_sizes(c);
67 /* Not much we can do here... */
68 /* Check if at least it has cpuid */
69 if (c->cpuid_level == -1) {
70 /* No cpuid. It must be an ancient CPU */
72 strcpy(c->x86_model_id, "486");
74 strcpy(c->x86_model_id, "386");
79 static const struct cpu_dev __cpuinitconst default_cpu = {
80 .c_init = default_init,
81 .c_vendor = "Unknown",
82 .c_x86_vendor = X86_VENDOR_UNKNOWN,
85 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
87 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
90 * We need valid kernel segments for data and code in long mode too
91 * IRET will check the segment types kkeil 2000/10/28
92 * Also sysret mandates a special GDT layout
94 * TLS descriptors are currently at a different place compared to i386.
95 * Hopefully nobody expects them at a fixed place (Wine?)
97 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
98 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
99 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
100 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
101 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
102 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
104 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
105 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
107 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
109 * Segments used for calling PnP BIOS have byte granularity.
110 * They code segments and data segments have fixed 64k limits,
111 * the transfer segment sizes are set at run time.
114 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
116 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
118 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
120 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
122 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
124 * The APM segments have byte granularity and their bases
125 * are set at run time. All have 64k limits.
128 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
130 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
132 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
134 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
135 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
136 GDT_STACK_CANARY_INIT
139 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
141 static int __init x86_xsave_setup(char *s)
145 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
146 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
149 __setup("noxsave", x86_xsave_setup);
151 static int __init x86_xsaveopt_setup(char *s)
153 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
156 __setup("noxsaveopt", x86_xsaveopt_setup);
159 static int __init x86_pcid_setup(char *s)
161 /* require an exact match without trailing characters */
165 /* do not emit a message if the feature is not present */
166 if (!boot_cpu_has(X86_FEATURE_PCID))
169 setup_clear_cpu_cap(X86_FEATURE_PCID);
170 pr_info("nopcid: PCID feature disabled\n");
173 __setup("nopcid", x86_pcid_setup);
176 static int __init x86_noinvpcid_setup(char *s)
178 /* noinvpcid doesn't accept parameters */
182 /* do not emit a message if the feature is not present */
183 if (!boot_cpu_has(X86_FEATURE_INVPCID))
186 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
187 pr_info("noinvpcid: INVPCID feature disabled\n");
190 early_param("noinvpcid", x86_noinvpcid_setup);
193 static int cachesize_override __cpuinitdata = -1;
194 static int disable_x86_serial_nr __cpuinitdata = 1;
196 static int __init cachesize_setup(char *str)
198 get_option(&str, &cachesize_override);
201 __setup("cachesize=", cachesize_setup);
203 static int __init x86_fxsr_setup(char *s)
205 setup_clear_cpu_cap(X86_FEATURE_FXSR);
206 setup_clear_cpu_cap(X86_FEATURE_XMM);
209 __setup("nofxsr", x86_fxsr_setup);
211 static int __init x86_sep_setup(char *s)
213 setup_clear_cpu_cap(X86_FEATURE_SEP);
216 __setup("nosep", x86_sep_setup);
218 /* Standard macro to see if a specific flag is changeable */
219 static inline int flag_is_changeable_p(u32 flag)
224 * Cyrix and IDT cpus allow disabling of CPUID
225 * so the code below may return different results
226 * when it is executed before and after enabling
227 * the CPUID. Add "volatile" to not allow gcc to
228 * optimize the subsequent calls to this function.
230 asm volatile ("pushfl \n\t"
241 : "=&r" (f1), "=&r" (f2)
244 return ((f1^f2) & flag) != 0;
247 /* Probe for the CPUID instruction */
248 static int __cpuinit have_cpuid_p(void)
250 return flag_is_changeable_p(X86_EFLAGS_ID);
253 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
255 unsigned long lo, hi;
257 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
260 /* Disable processor serial number: */
262 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
264 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
266 printk(KERN_NOTICE "CPU serial number disabled.\n");
267 clear_cpu_cap(c, X86_FEATURE_PN);
269 /* Disabling the serial number may affect the cpuid level */
270 c->cpuid_level = cpuid_eax(0);
273 static int __init x86_serial_nr_setup(char *s)
275 disable_x86_serial_nr = 0;
278 __setup("serialnumber", x86_serial_nr_setup);
280 static inline int flag_is_changeable_p(u32 flag)
284 /* Probe for the CPUID instruction */
285 static inline int have_cpuid_p(void)
289 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
294 static int disable_smep __cpuinitdata;
295 static __init int setup_disable_smep(char *arg)
300 __setup("nosmep", setup_disable_smep);
302 static __cpuinit void setup_smep(struct cpuinfo_x86 *c)
304 if (cpu_has(c, X86_FEATURE_SMEP)) {
305 if (unlikely(disable_smep)) {
306 setup_clear_cpu_cap(X86_FEATURE_SMEP);
307 clear_in_cr4(X86_CR4_SMEP);
309 set_in_cr4(X86_CR4_SMEP);
314 * Some CPU features depend on higher CPUID levels, which may not always
315 * be available due to CPUID level capping or broken virtualization
316 * software. Add those features to this table to auto-disable them.
318 struct cpuid_dependent_feature {
323 static const struct cpuid_dependent_feature __cpuinitconst
324 cpuid_dependent_features[] = {
325 { X86_FEATURE_MWAIT, 0x00000005 },
326 { X86_FEATURE_DCA, 0x00000009 },
327 { X86_FEATURE_XSAVE, 0x0000000d },
331 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
333 const struct cpuid_dependent_feature *df;
335 for (df = cpuid_dependent_features; df->feature; df++) {
337 if (!cpu_has(c, df->feature))
340 * Note: cpuid_level is set to -1 if unavailable, but
341 * extended_extended_level is set to 0 if unavailable
342 * and the legitimate extended levels are all negative
343 * when signed; hence the weird messing around with
346 if (!((s32)df->level < 0 ?
347 (u32)df->level > (u32)c->extended_cpuid_level :
348 (s32)df->level > (s32)c->cpuid_level))
351 clear_cpu_cap(c, df->feature);
356 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
357 x86_cap_flags[df->feature], df->level);
362 * Naming convention should be: <Name> [(<Codename>)]
363 * This table only is used unless init_<vendor>() below doesn't set it;
364 * in particular, if CPUID levels 0x80000002..4 are supported, this
368 /* Look up CPU names by table lookup. */
369 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
371 const struct cpu_model_info *info;
373 if (c->x86_model >= 16)
374 return NULL; /* Range check */
379 info = this_cpu->c_models;
381 while (info && info->family) {
382 if (info->family == c->x86)
383 return info->model_names[c->x86_model];
386 return NULL; /* Not found */
389 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
390 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
392 void load_percpu_segment(int cpu)
395 loadsegment(fs, __KERNEL_PERCPU);
398 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
400 load_stack_canary_segment();
404 * Current gdt points %fs at the "master" per-cpu area: after this,
405 * it's on the real one.
407 void switch_to_new_gdt(int cpu)
409 struct desc_ptr gdt_descr;
411 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
412 gdt_descr.size = GDT_SIZE - 1;
413 load_gdt(&gdt_descr);
414 /* Reload the per-cpu base */
416 load_percpu_segment(cpu);
419 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
421 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
426 if (c->extended_cpuid_level < 0x80000004)
429 v = (unsigned int *)c->x86_model_id;
430 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
431 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
432 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
433 c->x86_model_id[48] = 0;
436 * Intel chips right-justify this string for some dumb reason;
437 * undo that brain damage:
439 p = q = &c->x86_model_id[0];
445 while (q <= &c->x86_model_id[48])
446 *q++ = '\0'; /* Zero-pad the rest */
450 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
452 unsigned int n, dummy, ebx, ecx, edx, l2size;
454 n = c->extended_cpuid_level;
456 if (n >= 0x80000005) {
457 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
458 c->x86_cache_size = (ecx>>24) + (edx>>24);
460 /* On K8 L1 TLB is inclusive, so don't count it */
465 if (n < 0x80000006) /* Some chips just has a large L1. */
468 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
472 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
474 /* do processor-specific cache resizing */
475 if (this_cpu->c_size_cache)
476 l2size = this_cpu->c_size_cache(c, l2size);
478 /* Allow user to override all this if necessary. */
479 if (cachesize_override != -1)
480 l2size = cachesize_override;
483 return; /* Again, no L2 cache is possible */
486 c->x86_cache_size = l2size;
489 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
492 u32 eax, ebx, ecx, edx;
493 int index_msb, core_bits;
496 if (!cpu_has(c, X86_FEATURE_HT))
499 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
502 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
505 cpuid(1, &eax, &ebx, &ecx, &edx);
507 smp_num_siblings = (ebx & 0xff0000) >> 16;
509 if (smp_num_siblings == 1) {
510 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
514 if (smp_num_siblings <= 1)
517 index_msb = get_count_order(smp_num_siblings);
518 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
520 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
522 index_msb = get_count_order(smp_num_siblings);
524 core_bits = get_count_order(c->x86_max_cores);
526 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
527 ((1 << core_bits) - 1);
530 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
531 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
533 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
540 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
542 char *v = c->x86_vendor_id;
545 for (i = 0; i < X86_VENDOR_NUM; i++) {
549 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
550 (cpu_devs[i]->c_ident[1] &&
551 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
553 this_cpu = cpu_devs[i];
554 c->x86_vendor = this_cpu->c_x86_vendor;
560 "CPU: vendor_id '%s' unknown, using generic init.\n" \
561 "CPU: Your system may be unstable.\n", v);
563 c->x86_vendor = X86_VENDOR_UNKNOWN;
564 this_cpu = &default_cpu;
567 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
569 /* Get vendor name */
570 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
571 (unsigned int *)&c->x86_vendor_id[0],
572 (unsigned int *)&c->x86_vendor_id[8],
573 (unsigned int *)&c->x86_vendor_id[4]);
576 /* Intel-defined flags: level 0x00000001 */
577 if (c->cpuid_level >= 0x00000001) {
578 u32 junk, tfms, cap0, misc;
580 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
581 c->x86 = (tfms >> 8) & 0xf;
582 c->x86_model = (tfms >> 4) & 0xf;
583 c->x86_mask = tfms & 0xf;
586 c->x86 += (tfms >> 20) & 0xff;
588 c->x86_model += ((tfms >> 16) & 0xf) << 4;
590 if (cap0 & (1<<19)) {
591 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
592 c->x86_cache_alignment = c->x86_clflush_size;
597 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
602 /* Intel-defined flags: level 0x00000001 */
603 if (c->cpuid_level >= 0x00000001) {
604 u32 capability, excap;
606 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
607 c->x86_capability[0] = capability;
608 c->x86_capability[4] = excap;
611 /* Additional Intel-defined flags: level 0x00000007 */
612 if (c->cpuid_level >= 0x00000007) {
613 u32 eax, ebx, ecx, edx;
615 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
617 c->x86_capability[9] = ebx;
620 /* AMD-defined flags: level 0x80000001 */
621 xlvl = cpuid_eax(0x80000000);
622 c->extended_cpuid_level = xlvl;
624 if ((xlvl & 0xffff0000) == 0x80000000) {
625 if (xlvl >= 0x80000001) {
626 c->x86_capability[1] = cpuid_edx(0x80000001);
627 c->x86_capability[6] = cpuid_ecx(0x80000001);
631 if (c->extended_cpuid_level >= 0x80000008) {
632 u32 eax = cpuid_eax(0x80000008);
634 c->x86_virt_bits = (eax >> 8) & 0xff;
635 c->x86_phys_bits = eax & 0xff;
638 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
639 c->x86_phys_bits = 36;
642 if (c->extended_cpuid_level >= 0x80000007)
643 c->x86_power = cpuid_edx(0x80000007);
645 init_scattered_cpuid_features(c);
648 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
654 * First of all, decide if this is a 486 or higher
655 * It's a 486 if we can modify the AC flag
657 if (flag_is_changeable_p(X86_EFLAGS_AC))
662 for (i = 0; i < X86_VENDOR_NUM; i++)
663 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
664 c->x86_vendor_id[0] = 0;
665 cpu_devs[i]->c_identify(c);
666 if (c->x86_vendor_id[0]) {
675 * Do minimum CPU detection early.
676 * Fields really needed: vendor, cpuid_level, family, model, mask,
678 * The others are not touched to avoid unwanted side effects.
680 * WARNING: this function is only called on the BP. Don't add code here
681 * that is supposed to run on all CPUs.
683 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
686 c->x86_clflush_size = 64;
687 c->x86_phys_bits = 36;
688 c->x86_virt_bits = 48;
690 c->x86_clflush_size = 32;
691 c->x86_phys_bits = 32;
692 c->x86_virt_bits = 32;
694 c->x86_cache_alignment = c->x86_clflush_size;
696 memset(&c->x86_capability, 0, sizeof c->x86_capability);
697 c->extended_cpuid_level = 0;
700 identify_cpu_without_cpuid(c);
702 /* cyrix could have cpuid enabled via c_identify()*/
712 if (this_cpu->c_early_init)
713 this_cpu->c_early_init(c);
716 filter_cpuid_features(c, false);
720 if (this_cpu->c_bsp_init)
721 this_cpu->c_bsp_init(c);
724 void __init early_cpu_init(void)
726 const struct cpu_dev *const *cdev;
729 #ifdef CONFIG_PROCESSOR_SELECT
730 printk(KERN_INFO "KERNEL supported cpus:\n");
733 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
734 const struct cpu_dev *cpudev = *cdev;
736 if (count >= X86_VENDOR_NUM)
738 cpu_devs[count] = cpudev;
741 #ifdef CONFIG_PROCESSOR_SELECT
745 for (j = 0; j < 2; j++) {
746 if (!cpudev->c_ident[j])
748 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
754 early_identify_cpu(&boot_cpu_data);
758 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
759 * unfortunately, that's not true in practice because of early VIA
760 * chips and (more importantly) broken virtualizers that are not easy
761 * to detect. In the latter case it doesn't even *fail* reliably, so
762 * probing for it doesn't even work. Disable it completely on 32-bit
763 * unless we can find a reliable way to detect all the broken cases.
764 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
766 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
769 clear_cpu_cap(c, X86_FEATURE_NOPL);
771 set_cpu_cap(c, X86_FEATURE_NOPL);
775 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
777 c->extended_cpuid_level = 0;
780 identify_cpu_without_cpuid(c);
782 /* cyrix could have cpuid enabled via c_identify()*/
792 if (c->cpuid_level >= 0x00000001) {
793 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
795 # ifdef CONFIG_X86_HT
796 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
798 c->apicid = c->initial_apicid;
801 c->phys_proc_id = c->initial_apicid;
806 get_model_name(c); /* Default name */
812 * This does the hard work of actually picking apart the CPU stuff...
814 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
818 c->loops_per_jiffy = loops_per_jiffy;
819 c->x86_cache_size = -1;
820 c->x86_vendor = X86_VENDOR_UNKNOWN;
821 c->x86_model = c->x86_mask = 0; /* So far unknown... */
822 c->x86_vendor_id[0] = '\0'; /* Unset */
823 c->x86_model_id[0] = '\0'; /* Unset */
824 c->x86_max_cores = 1;
825 c->x86_coreid_bits = 0;
827 c->x86_clflush_size = 64;
828 c->x86_phys_bits = 36;
829 c->x86_virt_bits = 48;
831 c->cpuid_level = -1; /* CPUID not detected */
832 c->x86_clflush_size = 32;
833 c->x86_phys_bits = 32;
834 c->x86_virt_bits = 32;
836 c->x86_cache_alignment = c->x86_clflush_size;
837 memset(&c->x86_capability, 0, sizeof c->x86_capability);
841 if (this_cpu->c_identify)
842 this_cpu->c_identify(c);
844 /* Clear/Set all flags overriden by options, after probe */
845 for (i = 0; i < NCAPINTS; i++) {
846 c->x86_capability[i] &= ~cpu_caps_cleared[i];
847 c->x86_capability[i] |= cpu_caps_set[i];
851 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
855 * Vendor-specific initialization. In this section we
856 * canonicalize the feature flags, meaning if there are
857 * features a certain CPU supports which CPUID doesn't
858 * tell us, CPUID claiming incorrect flags, or other bugs,
859 * we handle them here.
861 * At the end of this section, c->x86_capability better
862 * indicate the features this CPU genuinely supports!
864 if (this_cpu->c_init)
867 /* Disable the PN if appropriate */
868 squash_the_stupid_serial_number(c);
871 * The vendor-specific functions might have changed features.
872 * Now we do "generic changes."
875 /* Filter out anything that depends on CPUID levels we don't have */
876 filter_cpuid_features(c, true);
878 /* If the model name is still unset, do table lookup. */
879 if (!c->x86_model_id[0]) {
881 p = table_lookup_model(c);
883 strcpy(c->x86_model_id, p);
886 sprintf(c->x86_model_id, "%02x/%02x",
887 c->x86, c->x86_model);
898 * Clear/Set all flags overriden by options, need do it
899 * before following smp all cpus cap AND.
901 for (i = 0; i < NCAPINTS; i++) {
902 c->x86_capability[i] &= ~cpu_caps_cleared[i];
903 c->x86_capability[i] |= cpu_caps_set[i];
907 * On SMP, boot_cpu_data holds the common feature set between
908 * all CPUs; so make sure that we indicate which features are
909 * common between the CPUs. The first time this routine gets
910 * executed, c == &boot_cpu_data.
912 if (c != &boot_cpu_data) {
913 /* AND the already accumulated flags with these */
914 for (i = 0; i < NCAPINTS; i++)
915 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
918 /* Init Machine Check Exception if available. */
921 select_idle_routine(c);
924 numa_add_cpu(smp_processor_id());
929 static void vgetcpu_set_mode(void)
931 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
932 vgetcpu_mode = VGETCPU_RDTSCP;
934 vgetcpu_mode = VGETCPU_LSL;
938 void __init identify_boot_cpu(void)
940 identify_cpu(&boot_cpu_data);
941 init_amd_e400_c1e_mask();
950 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
952 BUG_ON(c == &boot_cpu_data);
956 * Regardless of whether PCID is enumerated, the SDM says
957 * that it can't be enabled in 32-bit mode.
959 clear_cpu_cap(c, X86_FEATURE_PCID);
970 static const struct msr_range msr_range_array[] __cpuinitconst = {
971 { 0x00000000, 0x00000418},
972 { 0xc0000000, 0xc000040b},
973 { 0xc0010000, 0xc0010142},
974 { 0xc0011000, 0xc001103b},
977 static void __cpuinit print_cpu_msr(void)
979 unsigned index_min, index_max;
984 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
985 index_min = msr_range_array[i].min;
986 index_max = msr_range_array[i].max;
988 for (index = index_min; index < index_max; index++) {
989 if (rdmsrl_amd_safe(index, &val))
991 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
996 static int show_msr __cpuinitdata;
998 static __init int setup_show_msr(char *arg)
1002 get_option(&arg, &num);
1008 __setup("show_msr=", setup_show_msr);
1010 static __init int setup_noclflush(char *arg)
1012 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1015 __setup("noclflush", setup_noclflush);
1017 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1019 const char *vendor = NULL;
1021 if (c->x86_vendor < X86_VENDOR_NUM) {
1022 vendor = this_cpu->c_vendor;
1024 if (c->cpuid_level >= 0)
1025 vendor = c->x86_vendor_id;
1028 if (vendor && !strstr(c->x86_model_id, vendor))
1029 printk(KERN_CONT "%s ", vendor);
1031 if (c->x86_model_id[0])
1032 printk(KERN_CONT "%s", c->x86_model_id);
1034 printk(KERN_CONT "%d86", c->x86);
1036 if (c->x86_mask || c->cpuid_level >= 0)
1037 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1039 printk(KERN_CONT "\n");
1042 if (c->cpu_index < show_msr)
1050 static __init int setup_disablecpuid(char *arg)
1054 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
1055 setup_clear_cpu_cap(bit);
1061 __setup("clearcpuid=", setup_disablecpuid);
1063 #ifdef CONFIG_X86_64
1064 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1066 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1067 irq_stack_union) __aligned(PAGE_SIZE);
1070 * The following four percpu variables are hot. Align current_task to
1071 * cacheline size such that all four fall in the same cacheline.
1073 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1075 EXPORT_PER_CPU_SYMBOL(current_task);
1077 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1078 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1079 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1081 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1082 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1084 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1087 * Special IST stacks which the CPU switches to when it calls
1088 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1089 * limit), all of them are 4K, except the debug stack which
1092 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1093 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1094 [DEBUG_STACK - 1] = DEBUG_STKSZ
1097 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1098 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1100 /* May not be marked __init: used by software suspend */
1101 void syscall_init(void)
1104 * LSTAR and STAR live in a bit strange symbiosis.
1105 * They both write to the same internal register. STAR allows to
1106 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1108 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1109 wrmsrl(MSR_LSTAR, system_call);
1110 wrmsrl(MSR_CSTAR, ignore_sysret);
1112 #ifdef CONFIG_IA32_EMULATION
1113 syscall32_cpu_init();
1116 /* Flags to clear on syscall */
1117 wrmsrl(MSR_SYSCALL_MASK,
1118 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1121 unsigned long kernel_eflags;
1124 * Copies of the original ist values from the tss are only accessed during
1125 * debugging, no special alignment required.
1127 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1129 #else /* CONFIG_X86_64 */
1131 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1132 EXPORT_PER_CPU_SYMBOL(current_task);
1134 #ifdef CONFIG_CC_STACKPROTECTOR
1135 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1138 /* Make sure %fs and %gs are initialized properly in idle threads */
1139 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1141 memset(regs, 0, sizeof(struct pt_regs));
1142 regs->fs = __KERNEL_PERCPU;
1143 regs->gs = __KERNEL_STACK_CANARY;
1147 #endif /* CONFIG_X86_64 */
1150 * Clear all 6 debug registers:
1152 static void clear_all_debug_regs(void)
1156 for (i = 0; i < 8; i++) {
1157 /* Ignore db4, db5 */
1158 if ((i == 4) || (i == 5))
1167 * Restore debug regs if using kgdbwait and you have a kernel debugger
1168 * connection established.
1170 static void dbg_restore_debug_regs(void)
1172 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1173 arch_kgdb_ops.correct_hw_break();
1175 #else /* ! CONFIG_KGDB */
1176 #define dbg_restore_debug_regs()
1177 #endif /* ! CONFIG_KGDB */
1180 * cpu_init() initializes state that is per-CPU. Some data is already
1181 * initialized (naturally) in the bootstrap process, such as the GDT
1182 * and IDT. We reload them nevertheless, this function acts as a
1183 * 'CPU state barrier', nothing should get across.
1184 * A lot of state is already set up in PDA init for 64 bit
1186 #ifdef CONFIG_X86_64
1188 void __cpuinit cpu_init(void)
1190 struct orig_ist *oist;
1191 struct task_struct *me;
1192 struct tss_struct *t;
1197 cpu = stack_smp_processor_id();
1198 t = &per_cpu(init_tss, cpu);
1199 oist = &per_cpu(orig_ist, cpu);
1202 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1203 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1204 set_numa_node(early_cpu_to_node(cpu));
1209 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1210 panic("CPU#%d already initialized!\n", cpu);
1212 pr_debug("Initializing CPU#%d\n", cpu);
1214 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1217 * Initialize the per-CPU GDT with the boot GDT,
1218 * and set up the GDT descriptor:
1221 switch_to_new_gdt(cpu);
1224 load_idt((const struct desc_ptr *)&idt_descr);
1226 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1229 wrmsrl(MSR_FS_BASE, 0);
1230 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1238 * set up and load the per-CPU TSS
1240 if (!oist->ist[0]) {
1241 char *estacks = per_cpu(exception_stacks, cpu);
1243 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1244 estacks += exception_stack_sizes[v];
1245 oist->ist[v] = t->x86_tss.ist[v] =
1246 (unsigned long)estacks;
1250 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1253 * <= is required because the CPU will access up to
1254 * 8 bits beyond the end of the IO permission bitmap.
1256 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1257 t->io_bitmap[i] = ~0UL;
1259 atomic_inc(&init_mm.mm_count);
1260 me->active_mm = &init_mm;
1262 enter_lazy_tlb(&init_mm, me);
1264 load_sp0(t, ¤t->thread);
1265 set_tss_desc(cpu, t);
1267 load_mm_ldt(&init_mm);
1269 clear_all_debug_regs();
1270 dbg_restore_debug_regs();
1275 raw_local_save_flags(kernel_eflags);
1283 void __cpuinit cpu_init(void)
1285 int cpu = smp_processor_id();
1286 struct task_struct *curr = current;
1287 struct tss_struct *t = &per_cpu(init_tss, cpu);
1288 struct thread_struct *thread = &curr->thread;
1290 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1291 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1296 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1298 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1299 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1301 load_idt(&idt_descr);
1302 switch_to_new_gdt(cpu);
1305 * Set up and load the per-CPU TSS and LDT
1307 atomic_inc(&init_mm.mm_count);
1308 curr->active_mm = &init_mm;
1310 enter_lazy_tlb(&init_mm, curr);
1312 load_sp0(t, thread);
1313 set_tss_desc(cpu, t);
1315 load_mm_ldt(&init_mm);
1317 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1319 #ifdef CONFIG_DOUBLEFAULT
1320 /* Set up doublefault TSS pointer in the GDT */
1321 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1324 clear_all_debug_regs();
1325 dbg_restore_debug_regs();