1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/hypervisor.h>
19 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <linux/topology.h>
22 #include <linux/cpumask.h>
23 #include <asm/pgtable.h>
24 #include <asm/atomic.h>
25 #include <asm/proto.h>
26 #include <asm/setup.h>
31 #include <linux/numa.h>
38 #ifdef CONFIG_X86_LOCAL_APIC
39 #include <asm/uv/uv.h>
44 /* all of these masks are initialized in setup_cpu_local_masks() */
45 cpumask_var_t cpu_initialized_mask;
46 cpumask_var_t cpu_callout_mask;
47 cpumask_var_t cpu_callin_mask;
49 /* representing cpus for which sibling maps can be computed */
50 cpumask_var_t cpu_sibling_setup_mask;
52 /* correctly size the local cpu masks */
53 void __init setup_cpu_local_masks(void)
55 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
56 alloc_bootmem_cpumask_var(&cpu_callin_mask);
57 alloc_bootmem_cpumask_var(&cpu_callout_mask);
58 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
61 static void __cpuinit default_init(struct cpuinfo_x86 *c)
66 /* Not much we can do here... */
67 /* Check if at least it has cpuid */
68 if (c->cpuid_level == -1) {
69 /* No cpuid. It must be an ancient CPU */
71 strcpy(c->x86_model_id, "486");
73 strcpy(c->x86_model_id, "386");
78 static const struct cpu_dev __cpuinitconst default_cpu = {
79 .c_init = default_init,
80 .c_vendor = "Unknown",
81 .c_x86_vendor = X86_VENDOR_UNKNOWN,
84 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
86 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
89 * We need valid kernel segments for data and code in long mode too
90 * IRET will check the segment types kkeil 2000/10/28
91 * Also sysret mandates a special GDT layout
93 * TLS descriptors are currently at a different place compared to i386.
94 * Hopefully nobody expects them at a fixed place (Wine?)
96 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
97 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
98 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
99 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
100 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
101 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
103 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
104 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
105 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
108 * Segments used for calling PnP BIOS have byte granularity.
109 * They code segments and data segments have fixed 64k limits,
110 * the transfer segment sizes are set at run time.
113 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
115 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
117 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
119 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
121 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
123 * The APM segments have byte granularity and their bases
124 * are set at run time. All have 64k limits.
127 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
129 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
131 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
133 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
134 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
135 GDT_STACK_CANARY_INIT
138 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
140 static int __init x86_xsave_setup(char *s)
142 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
145 __setup("noxsave", x86_xsave_setup);
148 static int cachesize_override __cpuinitdata = -1;
149 static int disable_x86_serial_nr __cpuinitdata = 1;
151 static int __init cachesize_setup(char *str)
153 get_option(&str, &cachesize_override);
156 __setup("cachesize=", cachesize_setup);
158 static int __init x86_fxsr_setup(char *s)
160 setup_clear_cpu_cap(X86_FEATURE_FXSR);
161 setup_clear_cpu_cap(X86_FEATURE_XMM);
164 __setup("nofxsr", x86_fxsr_setup);
166 static int __init x86_sep_setup(char *s)
168 setup_clear_cpu_cap(X86_FEATURE_SEP);
171 __setup("nosep", x86_sep_setup);
173 /* Standard macro to see if a specific flag is changeable */
174 static inline int flag_is_changeable_p(u32 flag)
179 * Cyrix and IDT cpus allow disabling of CPUID
180 * so the code below may return different results
181 * when it is executed before and after enabling
182 * the CPUID. Add "volatile" to not allow gcc to
183 * optimize the subsequent calls to this function.
185 asm volatile ("pushfl \n\t"
196 : "=&r" (f1), "=&r" (f2)
199 return ((f1^f2) & flag) != 0;
202 /* Probe for the CPUID instruction */
203 static int __cpuinit have_cpuid_p(void)
205 return flag_is_changeable_p(X86_EFLAGS_ID);
208 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
210 unsigned long lo, hi;
212 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
215 /* Disable processor serial number: */
217 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
219 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
221 printk(KERN_NOTICE "CPU serial number disabled.\n");
222 clear_cpu_cap(c, X86_FEATURE_PN);
224 /* Disabling the serial number may affect the cpuid level */
225 c->cpuid_level = cpuid_eax(0);
228 static int __init x86_serial_nr_setup(char *s)
230 disable_x86_serial_nr = 0;
233 __setup("serialnumber", x86_serial_nr_setup);
235 static inline int flag_is_changeable_p(u32 flag)
239 /* Probe for the CPUID instruction */
240 static inline int have_cpuid_p(void)
244 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
250 * Some CPU features depend on higher CPUID levels, which may not always
251 * be available due to CPUID level capping or broken virtualization
252 * software. Add those features to this table to auto-disable them.
254 struct cpuid_dependent_feature {
259 static const struct cpuid_dependent_feature __cpuinitconst
260 cpuid_dependent_features[] = {
261 { X86_FEATURE_MWAIT, 0x00000005 },
262 { X86_FEATURE_DCA, 0x00000009 },
263 { X86_FEATURE_XSAVE, 0x0000000d },
267 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
269 const struct cpuid_dependent_feature *df;
271 for (df = cpuid_dependent_features; df->feature; df++) {
273 if (!cpu_has(c, df->feature))
276 * Note: cpuid_level is set to -1 if unavailable, but
277 * extended_extended_level is set to 0 if unavailable
278 * and the legitimate extended levels are all negative
279 * when signed; hence the weird messing around with
282 if (!((s32)df->level < 0 ?
283 (u32)df->level > (u32)c->extended_cpuid_level :
284 (s32)df->level > (s32)c->cpuid_level))
287 clear_cpu_cap(c, df->feature);
292 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
293 x86_cap_flags[df->feature], df->level);
298 * Naming convention should be: <Name> [(<Codename>)]
299 * This table only is used unless init_<vendor>() below doesn't set it;
300 * in particular, if CPUID levels 0x80000002..4 are supported, this
304 /* Look up CPU names by table lookup. */
305 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
307 const struct cpu_model_info *info;
309 if (c->x86_model >= 16)
310 return NULL; /* Range check */
315 info = this_cpu->c_models;
317 while (info && info->family) {
318 if (info->family == c->x86)
319 return info->model_names[c->x86_model];
322 return NULL; /* Not found */
325 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
326 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
328 void load_percpu_segment(int cpu)
331 loadsegment(fs, __KERNEL_PERCPU);
334 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
336 load_stack_canary_segment();
340 * Current gdt points %fs at the "master" per-cpu area: after this,
341 * it's on the real one.
343 void switch_to_new_gdt(int cpu)
345 struct desc_ptr gdt_descr;
347 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
348 gdt_descr.size = GDT_SIZE - 1;
349 load_gdt(&gdt_descr);
350 /* Reload the per-cpu base */
352 load_percpu_segment(cpu);
355 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
357 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
362 if (c->extended_cpuid_level < 0x80000004)
365 v = (unsigned int *)c->x86_model_id;
366 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
367 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
368 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
369 c->x86_model_id[48] = 0;
372 * Intel chips right-justify this string for some dumb reason;
373 * undo that brain damage:
375 p = q = &c->x86_model_id[0];
381 while (q <= &c->x86_model_id[48])
382 *q++ = '\0'; /* Zero-pad the rest */
386 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
388 unsigned int n, dummy, ebx, ecx, edx, l2size;
390 n = c->extended_cpuid_level;
392 if (n >= 0x80000005) {
393 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
394 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
395 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
396 c->x86_cache_size = (ecx>>24) + (edx>>24);
398 /* On K8 L1 TLB is inclusive, so don't count it */
403 if (n < 0x80000006) /* Some chips just has a large L1. */
406 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
410 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
412 /* do processor-specific cache resizing */
413 if (this_cpu->c_size_cache)
414 l2size = this_cpu->c_size_cache(c, l2size);
416 /* Allow user to override all this if necessary. */
417 if (cachesize_override != -1)
418 l2size = cachesize_override;
421 return; /* Again, no L2 cache is possible */
424 c->x86_cache_size = l2size;
426 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
430 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
433 u32 eax, ebx, ecx, edx;
434 int index_msb, core_bits;
436 if (!cpu_has(c, X86_FEATURE_HT))
439 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
442 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
445 cpuid(1, &eax, &ebx, &ecx, &edx);
447 smp_num_siblings = (ebx & 0xff0000) >> 16;
449 if (smp_num_siblings == 1) {
450 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
454 if (smp_num_siblings <= 1)
457 if (smp_num_siblings > nr_cpu_ids) {
458 pr_warning("CPU: Unsupported number of siblings %d",
460 smp_num_siblings = 1;
464 index_msb = get_count_order(smp_num_siblings);
465 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
467 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
469 index_msb = get_count_order(smp_num_siblings);
471 core_bits = get_count_order(c->x86_max_cores);
473 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
474 ((1 << core_bits) - 1);
477 if ((c->x86_max_cores * smp_num_siblings) > 1) {
478 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
480 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
486 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
488 char *v = c->x86_vendor_id;
491 for (i = 0; i < X86_VENDOR_NUM; i++) {
495 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
496 (cpu_devs[i]->c_ident[1] &&
497 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
499 this_cpu = cpu_devs[i];
500 c->x86_vendor = this_cpu->c_x86_vendor;
506 "CPU: vendor_id '%s' unknown, using generic init.\n" \
507 "CPU: Your system may be unstable.\n", v);
509 c->x86_vendor = X86_VENDOR_UNKNOWN;
510 this_cpu = &default_cpu;
513 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
515 /* Get vendor name */
516 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
517 (unsigned int *)&c->x86_vendor_id[0],
518 (unsigned int *)&c->x86_vendor_id[8],
519 (unsigned int *)&c->x86_vendor_id[4]);
522 /* Intel-defined flags: level 0x00000001 */
523 if (c->cpuid_level >= 0x00000001) {
524 u32 junk, tfms, cap0, misc;
526 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
527 c->x86 = (tfms >> 8) & 0xf;
528 c->x86_model = (tfms >> 4) & 0xf;
529 c->x86_mask = tfms & 0xf;
532 c->x86 += (tfms >> 20) & 0xff;
534 c->x86_model += ((tfms >> 16) & 0xf) << 4;
536 if (cap0 & (1<<19)) {
537 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
538 c->x86_cache_alignment = c->x86_clflush_size;
543 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
548 /* Intel-defined flags: level 0x00000001 */
549 if (c->cpuid_level >= 0x00000001) {
550 u32 capability, excap;
552 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
553 c->x86_capability[0] = capability;
554 c->x86_capability[4] = excap;
557 /* AMD-defined flags: level 0x80000001 */
558 xlvl = cpuid_eax(0x80000000);
559 c->extended_cpuid_level = xlvl;
561 if ((xlvl & 0xffff0000) == 0x80000000) {
562 if (xlvl >= 0x80000001) {
563 c->x86_capability[1] = cpuid_edx(0x80000001);
564 c->x86_capability[6] = cpuid_ecx(0x80000001);
568 if (c->extended_cpuid_level >= 0x80000008) {
569 u32 eax = cpuid_eax(0x80000008);
571 c->x86_virt_bits = (eax >> 8) & 0xff;
572 c->x86_phys_bits = eax & 0xff;
575 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
576 c->x86_phys_bits = 36;
579 if (c->extended_cpuid_level >= 0x80000007)
580 c->x86_power = cpuid_edx(0x80000007);
584 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
590 * First of all, decide if this is a 486 or higher
591 * It's a 486 if we can modify the AC flag
593 if (flag_is_changeable_p(X86_EFLAGS_AC))
598 for (i = 0; i < X86_VENDOR_NUM; i++)
599 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
600 c->x86_vendor_id[0] = 0;
601 cpu_devs[i]->c_identify(c);
602 if (c->x86_vendor_id[0]) {
611 * Do minimum CPU detection early.
612 * Fields really needed: vendor, cpuid_level, family, model, mask,
614 * The others are not touched to avoid unwanted side effects.
616 * WARNING: this function is only called on the BP. Don't add code here
617 * that is supposed to run on all CPUs.
619 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
622 c->x86_clflush_size = 64;
623 c->x86_phys_bits = 36;
624 c->x86_virt_bits = 48;
626 c->x86_clflush_size = 32;
627 c->x86_phys_bits = 32;
628 c->x86_virt_bits = 32;
630 c->x86_cache_alignment = c->x86_clflush_size;
632 memset(&c->x86_capability, 0, sizeof c->x86_capability);
633 c->extended_cpuid_level = 0;
636 identify_cpu_without_cpuid(c);
638 /* cyrix could have cpuid enabled via c_identify()*/
648 if (this_cpu->c_early_init)
649 this_cpu->c_early_init(c);
652 c->cpu_index = boot_cpu_id;
654 filter_cpuid_features(c, false);
657 void __init early_cpu_init(void)
659 const struct cpu_dev *const *cdev;
662 printk(KERN_INFO "KERNEL supported cpus:\n");
663 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
664 const struct cpu_dev *cpudev = *cdev;
667 if (count >= X86_VENDOR_NUM)
669 cpu_devs[count] = cpudev;
672 for (j = 0; j < 2; j++) {
673 if (!cpudev->c_ident[j])
675 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
680 early_identify_cpu(&boot_cpu_data);
684 * The NOPL instruction is supposed to exist on all CPUs with
685 * family >= 6; unfortunately, that's not true in practice because
686 * of early VIA chips and (more importantly) broken virtualizers that
687 * are not easy to detect. In the latter case it doesn't even *fail*
688 * reliably, so probing for it doesn't even work. Disable it completely
689 * unless we can find a reliable way to detect all the broken cases.
691 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
693 clear_cpu_cap(c, X86_FEATURE_NOPL);
696 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
698 c->extended_cpuid_level = 0;
701 identify_cpu_without_cpuid(c);
703 /* cyrix could have cpuid enabled via c_identify()*/
713 if (c->cpuid_level >= 0x00000001) {
714 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
716 # ifdef CONFIG_X86_HT
717 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
719 c->apicid = c->initial_apicid;
724 c->phys_proc_id = c->initial_apicid;
728 get_model_name(c); /* Default name */
730 init_scattered_cpuid_features(c);
735 * This does the hard work of actually picking apart the CPU stuff...
737 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
741 c->loops_per_jiffy = loops_per_jiffy;
742 c->x86_cache_size = -1;
743 c->x86_vendor = X86_VENDOR_UNKNOWN;
744 c->x86_model = c->x86_mask = 0; /* So far unknown... */
745 c->x86_vendor_id[0] = '\0'; /* Unset */
746 c->x86_model_id[0] = '\0'; /* Unset */
747 c->x86_max_cores = 1;
748 c->x86_coreid_bits = 0;
750 c->x86_clflush_size = 64;
751 c->x86_phys_bits = 36;
752 c->x86_virt_bits = 48;
754 c->cpuid_level = -1; /* CPUID not detected */
755 c->x86_clflush_size = 32;
756 c->x86_phys_bits = 32;
757 c->x86_virt_bits = 32;
759 c->x86_cache_alignment = c->x86_clflush_size;
760 memset(&c->x86_capability, 0, sizeof c->x86_capability);
764 if (this_cpu->c_identify)
765 this_cpu->c_identify(c);
767 /* Clear/Set all flags overriden by options, after probe */
768 for (i = 0; i < NCAPINTS; i++) {
769 c->x86_capability[i] &= ~cpu_caps_cleared[i];
770 c->x86_capability[i] |= cpu_caps_set[i];
774 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
778 * Vendor-specific initialization. In this section we
779 * canonicalize the feature flags, meaning if there are
780 * features a certain CPU supports which CPUID doesn't
781 * tell us, CPUID claiming incorrect flags, or other bugs,
782 * we handle them here.
784 * At the end of this section, c->x86_capability better
785 * indicate the features this CPU genuinely supports!
787 if (this_cpu->c_init)
790 /* Disable the PN if appropriate */
791 squash_the_stupid_serial_number(c);
794 * The vendor-specific functions might have changed features.
795 * Now we do "generic changes."
798 /* Filter out anything that depends on CPUID levels we don't have */
799 filter_cpuid_features(c, true);
801 /* If the model name is still unset, do table lookup. */
802 if (!c->x86_model_id[0]) {
804 p = table_lookup_model(c);
806 strcpy(c->x86_model_id, p);
809 sprintf(c->x86_model_id, "%02x/%02x",
810 c->x86, c->x86_model);
820 * Clear/Set all flags overriden by options, need do it
821 * before following smp all cpus cap AND.
823 for (i = 0; i < NCAPINTS; i++) {
824 c->x86_capability[i] &= ~cpu_caps_cleared[i];
825 c->x86_capability[i] |= cpu_caps_set[i];
829 * On SMP, boot_cpu_data holds the common feature set between
830 * all CPUs; so make sure that we indicate which features are
831 * common between the CPUs. The first time this routine gets
832 * executed, c == &boot_cpu_data.
834 if (c != &boot_cpu_data) {
835 /* AND the already accumulated flags with these */
836 for (i = 0; i < NCAPINTS; i++)
837 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
840 /* Init Machine Check Exception if available. */
843 select_idle_routine(c);
845 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
846 numa_add_cpu(smp_processor_id());
851 static void vgetcpu_set_mode(void)
853 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
854 vgetcpu_mode = VGETCPU_RDTSCP;
856 vgetcpu_mode = VGETCPU_LSL;
860 void __init identify_boot_cpu(void)
862 identify_cpu(&boot_cpu_data);
870 init_hw_perf_events();
873 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
875 BUG_ON(c == &boot_cpu_data);
888 static const struct msr_range msr_range_array[] __cpuinitconst = {
889 { 0x00000000, 0x00000418},
890 { 0xc0000000, 0xc000040b},
891 { 0xc0010000, 0xc0010142},
892 { 0xc0011000, 0xc001103b},
895 static void __cpuinit print_cpu_msr(void)
897 unsigned index_min, index_max;
902 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
903 index_min = msr_range_array[i].min;
904 index_max = msr_range_array[i].max;
906 for (index = index_min; index < index_max; index++) {
907 if (rdmsrl_amd_safe(index, &val))
909 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
914 static int show_msr __cpuinitdata;
916 static __init int setup_show_msr(char *arg)
920 get_option(&arg, &num);
926 __setup("show_msr=", setup_show_msr);
928 static __init int setup_noclflush(char *arg)
930 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
933 __setup("noclflush", setup_noclflush);
935 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
937 const char *vendor = NULL;
939 if (c->x86_vendor < X86_VENDOR_NUM) {
940 vendor = this_cpu->c_vendor;
942 if (c->cpuid_level >= 0)
943 vendor = c->x86_vendor_id;
946 if (vendor && !strstr(c->x86_model_id, vendor))
947 printk(KERN_CONT "%s ", vendor);
949 if (c->x86_model_id[0])
950 printk(KERN_CONT "%s", c->x86_model_id);
952 printk(KERN_CONT "%d86", c->x86);
954 if (c->x86_mask || c->cpuid_level >= 0)
955 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
957 printk(KERN_CONT "\n");
960 if (c->cpu_index < show_msr)
968 static __init int setup_disablecpuid(char *arg)
972 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
973 setup_clear_cpu_cap(bit);
979 __setup("clearcpuid=", setup_disablecpuid);
982 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
984 DEFINE_PER_CPU_FIRST(union irq_stack_union,
985 irq_stack_union) __aligned(PAGE_SIZE);
988 * The following four percpu variables are hot. Align current_task to
989 * cacheline size such that all four fall in the same cacheline.
991 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
993 EXPORT_PER_CPU_SYMBOL(current_task);
995 DEFINE_PER_CPU(unsigned long, kernel_stack) =
996 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
997 EXPORT_PER_CPU_SYMBOL(kernel_stack);
999 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1000 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1002 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1005 * Special IST stacks which the CPU switches to when it calls
1006 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1007 * limit), all of them are 4K, except the debug stack which
1010 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1011 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1012 [DEBUG_STACK - 1] = DEBUG_STKSZ
1015 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1016 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1018 /* May not be marked __init: used by software suspend */
1019 void syscall_init(void)
1022 * LSTAR and STAR live in a bit strange symbiosis.
1023 * They both write to the same internal register. STAR allows to
1024 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1026 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1027 wrmsrl(MSR_LSTAR, system_call);
1028 wrmsrl(MSR_CSTAR, ignore_sysret);
1030 #ifdef CONFIG_IA32_EMULATION
1031 syscall32_cpu_init();
1034 /* Flags to clear on syscall */
1035 wrmsrl(MSR_SYSCALL_MASK,
1036 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1039 unsigned long kernel_eflags;
1042 * Copies of the original ist values from the tss are only accessed during
1043 * debugging, no special alignment required.
1045 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1047 #else /* CONFIG_X86_64 */
1049 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1050 EXPORT_PER_CPU_SYMBOL(current_task);
1052 #ifdef CONFIG_CC_STACKPROTECTOR
1053 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1056 /* Make sure %fs and %gs are initialized properly in idle threads */
1057 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1059 memset(regs, 0, sizeof(struct pt_regs));
1060 regs->fs = __KERNEL_PERCPU;
1061 regs->gs = __KERNEL_STACK_CANARY;
1065 #endif /* CONFIG_X86_64 */
1068 * Clear all 6 debug registers:
1070 static void clear_all_debug_regs(void)
1074 for (i = 0; i < 8; i++) {
1075 /* Ignore db4, db5 */
1076 if ((i == 4) || (i == 5))
1084 * cpu_init() initializes state that is per-CPU. Some data is already
1085 * initialized (naturally) in the bootstrap process, such as the GDT
1086 * and IDT. We reload them nevertheless, this function acts as a
1087 * 'CPU state barrier', nothing should get across.
1088 * A lot of state is already set up in PDA init for 64 bit
1090 #ifdef CONFIG_X86_64
1092 void __cpuinit cpu_init(void)
1094 struct orig_ist *orig_ist;
1095 struct task_struct *me;
1096 struct tss_struct *t;
1101 cpu = stack_smp_processor_id();
1102 t = &per_cpu(init_tss, cpu);
1103 orig_ist = &per_cpu(orig_ist, cpu);
1106 if (cpu != 0 && percpu_read(node_number) == 0 &&
1107 cpu_to_node(cpu) != NUMA_NO_NODE)
1108 percpu_write(node_number, cpu_to_node(cpu));
1113 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1114 panic("CPU#%d already initialized!\n", cpu);
1116 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1118 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1121 * Initialize the per-CPU GDT with the boot GDT,
1122 * and set up the GDT descriptor:
1125 switch_to_new_gdt(cpu);
1128 load_idt((const struct desc_ptr *)&idt_descr);
1130 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1133 wrmsrl(MSR_FS_BASE, 0);
1134 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1142 * set up and load the per-CPU TSS
1144 if (!orig_ist->ist[0]) {
1145 char *estacks = per_cpu(exception_stacks, cpu);
1147 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1148 estacks += exception_stack_sizes[v];
1149 orig_ist->ist[v] = t->x86_tss.ist[v] =
1150 (unsigned long)estacks;
1154 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1157 * <= is required because the CPU will access up to
1158 * 8 bits beyond the end of the IO permission bitmap.
1160 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1161 t->io_bitmap[i] = ~0UL;
1163 atomic_inc(&init_mm.mm_count);
1164 me->active_mm = &init_mm;
1166 enter_lazy_tlb(&init_mm, me);
1168 load_sp0(t, ¤t->thread);
1169 set_tss_desc(cpu, t);
1171 load_LDT(&init_mm.context);
1175 * If the kgdb is connected no debug regs should be altered. This
1176 * is only applicable when KGDB and a KGDB I/O module are built
1177 * into the kernel and you are using early debugging with
1178 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1180 if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1181 arch_kgdb_ops.correct_hw_break();
1184 clear_all_debug_regs();
1188 raw_local_save_flags(kernel_eflags);
1196 void __cpuinit cpu_init(void)
1198 int cpu = smp_processor_id();
1199 struct task_struct *curr = current;
1200 struct tss_struct *t = &per_cpu(init_tss, cpu);
1201 struct thread_struct *thread = &curr->thread;
1203 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1204 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1209 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1211 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1212 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1214 load_idt(&idt_descr);
1215 switch_to_new_gdt(cpu);
1218 * Set up and load the per-CPU TSS and LDT
1220 atomic_inc(&init_mm.mm_count);
1221 curr->active_mm = &init_mm;
1223 enter_lazy_tlb(&init_mm, curr);
1225 load_sp0(t, thread);
1226 set_tss_desc(cpu, t);
1228 load_LDT(&init_mm.context);
1230 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1232 #ifdef CONFIG_DOUBLEFAULT
1233 /* Set up doublefault TSS pointer in the GDT */
1234 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1237 clear_all_debug_regs();
1240 * Force FPU initialization:
1243 current_thread_info()->status = TS_XSAVE;
1245 current_thread_info()->status = 0;
1247 mxcsr_feature_mask_init();
1250 * Boot processor to setup the FP and extended state context info.
1252 if (smp_processor_id() == boot_cpu_id)
1253 init_thread_xstate();