1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/archrandom.h>
19 #include <asm/hypervisor.h>
20 #include <asm/processor.h>
21 #include <asm/sections.h>
22 #include <linux/topology.h>
23 #include <linux/cpumask.h>
24 #include <asm/pgtable.h>
25 #include <linux/atomic.h>
26 #include <asm/proto.h>
27 #include <asm/setup.h>
32 #include <linux/numa.h>
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/uv/uv.h>
45 /* all of these masks are initialized in setup_cpu_local_masks() */
46 cpumask_var_t cpu_initialized_mask;
47 cpumask_var_t cpu_callout_mask;
48 cpumask_var_t cpu_callin_mask;
50 /* representing cpus for which sibling maps can be computed */
51 cpumask_var_t cpu_sibling_setup_mask;
53 /* correctly size the local cpu masks */
54 void __init setup_cpu_local_masks(void)
56 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
57 alloc_bootmem_cpumask_var(&cpu_callin_mask);
58 alloc_bootmem_cpumask_var(&cpu_callout_mask);
59 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
62 static void __cpuinit default_init(struct cpuinfo_x86 *c)
65 cpu_detect_cache_sizes(c);
67 /* Not much we can do here... */
68 /* Check if at least it has cpuid */
69 if (c->cpuid_level == -1) {
70 /* No cpuid. It must be an ancient CPU */
72 strcpy(c->x86_model_id, "486");
74 strcpy(c->x86_model_id, "386");
79 static const struct cpu_dev __cpuinitconst default_cpu = {
80 .c_init = default_init,
81 .c_vendor = "Unknown",
82 .c_x86_vendor = X86_VENDOR_UNKNOWN,
85 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
87 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(struct gdt_page, gdt_page) = { .gdt = {
90 * We need valid kernel segments for data and code in long mode too
91 * IRET will check the segment types kkeil 2000/10/28
92 * Also sysret mandates a special GDT layout
94 * TLS descriptors are currently at a different place compared to i386.
95 * Hopefully nobody expects them at a fixed place (Wine?)
97 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
98 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
99 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
100 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
101 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
102 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
104 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
105 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
107 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
109 * Segments used for calling PnP BIOS have byte granularity.
110 * They code segments and data segments have fixed 64k limits,
111 * the transfer segment sizes are set at run time.
114 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
116 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
118 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
120 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
122 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
124 * The APM segments have byte granularity and their bases
125 * are set at run time. All have 64k limits.
128 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
130 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
132 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
134 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
135 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
136 GDT_STACK_CANARY_INIT
139 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
141 static int __init x86_xsave_setup(char *s)
145 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
146 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
149 __setup("noxsave", x86_xsave_setup);
151 static int __init x86_xsaveopt_setup(char *s)
153 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
156 __setup("noxsaveopt", x86_xsaveopt_setup);
159 static int __init x86_pcid_setup(char *s)
161 /* require an exact match without trailing characters */
165 /* do not emit a message if the feature is not present */
166 if (!boot_cpu_has(X86_FEATURE_PCID))
169 setup_clear_cpu_cap(X86_FEATURE_PCID);
170 pr_info("nopcid: PCID feature disabled\n");
173 __setup("nopcid", x86_pcid_setup);
176 static int __init x86_noinvpcid_setup(char *s)
178 /* noinvpcid doesn't accept parameters */
182 /* do not emit a message if the feature is not present */
183 if (!boot_cpu_has(X86_FEATURE_INVPCID))
186 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
187 pr_info("noinvpcid: INVPCID feature disabled\n");
190 early_param("noinvpcid", x86_noinvpcid_setup);
193 static int cachesize_override __cpuinitdata = -1;
194 static int disable_x86_serial_nr __cpuinitdata = 1;
196 static int __init cachesize_setup(char *str)
198 get_option(&str, &cachesize_override);
201 __setup("cachesize=", cachesize_setup);
203 static int __init x86_fxsr_setup(char *s)
205 setup_clear_cpu_cap(X86_FEATURE_FXSR);
206 setup_clear_cpu_cap(X86_FEATURE_XMM);
209 __setup("nofxsr", x86_fxsr_setup);
211 static int __init x86_sep_setup(char *s)
213 setup_clear_cpu_cap(X86_FEATURE_SEP);
216 __setup("nosep", x86_sep_setup);
218 /* Standard macro to see if a specific flag is changeable */
219 static inline int flag_is_changeable_p(u32 flag)
224 * Cyrix and IDT cpus allow disabling of CPUID
225 * so the code below may return different results
226 * when it is executed before and after enabling
227 * the CPUID. Add "volatile" to not allow gcc to
228 * optimize the subsequent calls to this function.
230 asm volatile ("pushfl \n\t"
241 : "=&r" (f1), "=&r" (f2)
244 return ((f1^f2) & flag) != 0;
247 /* Probe for the CPUID instruction */
248 static int __cpuinit have_cpuid_p(void)
250 return flag_is_changeable_p(X86_EFLAGS_ID);
253 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
255 unsigned long lo, hi;
257 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
260 /* Disable processor serial number: */
262 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
264 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
266 printk(KERN_NOTICE "CPU serial number disabled.\n");
267 clear_cpu_cap(c, X86_FEATURE_PN);
269 /* Disabling the serial number may affect the cpuid level */
270 c->cpuid_level = cpuid_eax(0);
273 static int __init x86_serial_nr_setup(char *s)
275 disable_x86_serial_nr = 0;
278 __setup("serialnumber", x86_serial_nr_setup);
280 static inline int flag_is_changeable_p(u32 flag)
284 /* Probe for the CPUID instruction */
285 static inline int have_cpuid_p(void)
289 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
294 static int disable_smep __cpuinitdata;
295 static __init int setup_disable_smep(char *arg)
300 __setup("nosmep", setup_disable_smep);
302 static __cpuinit void setup_smep(struct cpuinfo_x86 *c)
304 if (cpu_has(c, X86_FEATURE_SMEP)) {
305 if (unlikely(disable_smep)) {
306 setup_clear_cpu_cap(X86_FEATURE_SMEP);
307 clear_in_cr4(X86_CR4_SMEP);
309 set_in_cr4(X86_CR4_SMEP);
313 static void setup_pcid(struct cpuinfo_x86 *c)
315 if (cpu_has(c, X86_FEATURE_PCID)) {
316 if (IS_ENABLED(CONFIG_X86_64) &&
317 (cpu_has(c, X86_FEATURE_PGE) || kaiser_enabled)) {
319 * Regardless of whether PCID is enumerated, the
320 * SDM says that it can't be enabled in 32-bit mode.
322 set_in_cr4(X86_CR4_PCIDE);
324 * INVPCID has two "groups" of types:
325 * 1/2: Invalidate an individual address
326 * 3/4: Invalidate all contexts
328 * 1/2 take a PCID, but 3/4 do not. So, 3/4
329 * ignore the PCID argument in the descriptor.
330 * But, we have to be careful not to call 1/2
331 * with an actual non-zero PCID in them before
332 * we do the above set_in_cr4().
334 if (cpu_has(c, X86_FEATURE_INVPCID))
335 set_cpu_cap(c, X86_FEATURE_INVPCID_SINGLE);
338 * flush_tlb_all(), as currently implemented, won't
339 * work if PCID is on but PGE is not. Since that
340 * combination doesn't exist on real hardware, there's
341 * no reason to try to fully support it, but it's
342 * polite to avoid corrupting data if we're on
343 * an improperly configured VM.
345 clear_cpu_cap(c, X86_FEATURE_PCID);
352 * Some CPU features depend on higher CPUID levels, which may not always
353 * be available due to CPUID level capping or broken virtualization
354 * software. Add those features to this table to auto-disable them.
356 struct cpuid_dependent_feature {
361 static const struct cpuid_dependent_feature __cpuinitconst
362 cpuid_dependent_features[] = {
363 { X86_FEATURE_MWAIT, 0x00000005 },
364 { X86_FEATURE_DCA, 0x00000009 },
365 { X86_FEATURE_XSAVE, 0x0000000d },
369 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
371 const struct cpuid_dependent_feature *df;
373 for (df = cpuid_dependent_features; df->feature; df++) {
375 if (!cpu_has(c, df->feature))
378 * Note: cpuid_level is set to -1 if unavailable, but
379 * extended_extended_level is set to 0 if unavailable
380 * and the legitimate extended levels are all negative
381 * when signed; hence the weird messing around with
384 if (!((s32)df->level < 0 ?
385 (u32)df->level > (u32)c->extended_cpuid_level :
386 (s32)df->level > (s32)c->cpuid_level))
389 clear_cpu_cap(c, df->feature);
394 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
395 x86_cap_flags[df->feature], df->level);
400 * Naming convention should be: <Name> [(<Codename>)]
401 * This table only is used unless init_<vendor>() below doesn't set it;
402 * in particular, if CPUID levels 0x80000002..4 are supported, this
406 /* Look up CPU names by table lookup. */
407 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
409 const struct cpu_model_info *info;
411 if (c->x86_model >= 16)
412 return NULL; /* Range check */
417 info = this_cpu->c_models;
419 while (info && info->family) {
420 if (info->family == c->x86)
421 return info->model_names[c->x86_model];
424 return NULL; /* Not found */
427 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __cpuinitdata;
428 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __cpuinitdata;
430 void load_percpu_segment(int cpu)
433 loadsegment(fs, __KERNEL_PERCPU);
436 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
438 load_stack_canary_segment();
442 * Current gdt points %fs at the "master" per-cpu area: after this,
443 * it's on the real one.
445 void switch_to_new_gdt(int cpu)
447 struct desc_ptr gdt_descr;
449 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
450 gdt_descr.size = GDT_SIZE - 1;
451 load_gdt(&gdt_descr);
452 /* Reload the per-cpu base */
454 load_percpu_segment(cpu);
457 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
459 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
464 if (c->extended_cpuid_level < 0x80000004)
467 v = (unsigned int *)c->x86_model_id;
468 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
469 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
470 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
471 c->x86_model_id[48] = 0;
474 * Intel chips right-justify this string for some dumb reason;
475 * undo that brain damage:
477 p = q = &c->x86_model_id[0];
483 while (q <= &c->x86_model_id[48])
484 *q++ = '\0'; /* Zero-pad the rest */
488 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
490 unsigned int n, dummy, ebx, ecx, edx, l2size;
492 n = c->extended_cpuid_level;
494 if (n >= 0x80000005) {
495 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
496 c->x86_cache_size = (ecx>>24) + (edx>>24);
498 /* On K8 L1 TLB is inclusive, so don't count it */
503 if (n < 0x80000006) /* Some chips just has a large L1. */
506 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
510 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
512 /* do processor-specific cache resizing */
513 if (this_cpu->c_size_cache)
514 l2size = this_cpu->c_size_cache(c, l2size);
516 /* Allow user to override all this if necessary. */
517 if (cachesize_override != -1)
518 l2size = cachesize_override;
521 return; /* Again, no L2 cache is possible */
524 c->x86_cache_size = l2size;
527 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
530 u32 eax, ebx, ecx, edx;
531 int index_msb, core_bits;
534 if (!cpu_has(c, X86_FEATURE_HT))
537 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
540 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
543 cpuid(1, &eax, &ebx, &ecx, &edx);
545 smp_num_siblings = (ebx & 0xff0000) >> 16;
547 if (smp_num_siblings == 1) {
548 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
552 if (smp_num_siblings <= 1)
555 index_msb = get_count_order(smp_num_siblings);
556 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
558 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
560 index_msb = get_count_order(smp_num_siblings);
562 core_bits = get_count_order(c->x86_max_cores);
564 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
565 ((1 << core_bits) - 1);
568 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
569 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
571 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
578 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
580 char *v = c->x86_vendor_id;
583 for (i = 0; i < X86_VENDOR_NUM; i++) {
587 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
588 (cpu_devs[i]->c_ident[1] &&
589 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
591 this_cpu = cpu_devs[i];
592 c->x86_vendor = this_cpu->c_x86_vendor;
598 "CPU: vendor_id '%s' unknown, using generic init.\n" \
599 "CPU: Your system may be unstable.\n", v);
601 c->x86_vendor = X86_VENDOR_UNKNOWN;
602 this_cpu = &default_cpu;
605 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
607 /* Get vendor name */
608 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
609 (unsigned int *)&c->x86_vendor_id[0],
610 (unsigned int *)&c->x86_vendor_id[8],
611 (unsigned int *)&c->x86_vendor_id[4]);
614 /* Intel-defined flags: level 0x00000001 */
615 if (c->cpuid_level >= 0x00000001) {
616 u32 junk, tfms, cap0, misc;
618 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
619 c->x86 = (tfms >> 8) & 0xf;
620 c->x86_model = (tfms >> 4) & 0xf;
621 c->x86_mask = tfms & 0xf;
624 c->x86 += (tfms >> 20) & 0xff;
626 c->x86_model += ((tfms >> 16) & 0xf) << 4;
628 if (cap0 & (1<<19)) {
629 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
630 c->x86_cache_alignment = c->x86_clflush_size;
635 static void apply_forced_caps(struct cpuinfo_x86 *c)
639 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
640 c->x86_capability[i] &= ~cpu_caps_cleared[i];
641 c->x86_capability[i] |= cpu_caps_set[i];
645 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
650 /* Intel-defined flags: level 0x00000001 */
651 if (c->cpuid_level >= 0x00000001) {
652 u32 capability, excap;
654 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
655 c->x86_capability[0] = capability;
656 c->x86_capability[4] = excap;
659 /* Additional Intel-defined flags: level 0x00000007 */
660 if (c->cpuid_level >= 0x00000007) {
661 u32 eax, ebx, ecx, edx;
663 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
665 c->x86_capability[9] = ebx;
668 /* AMD-defined flags: level 0x80000001 */
669 xlvl = cpuid_eax(0x80000000);
670 c->extended_cpuid_level = xlvl;
672 if ((xlvl & 0xffff0000) == 0x80000000) {
673 if (xlvl >= 0x80000001) {
674 c->x86_capability[1] = cpuid_edx(0x80000001);
675 c->x86_capability[6] = cpuid_ecx(0x80000001);
679 if (c->extended_cpuid_level >= 0x80000008) {
680 u32 eax = cpuid_eax(0x80000008);
682 c->x86_virt_bits = (eax >> 8) & 0xff;
683 c->x86_phys_bits = eax & 0xff;
686 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
687 c->x86_phys_bits = 36;
690 if (c->extended_cpuid_level >= 0x80000007)
691 c->x86_power = cpuid_edx(0x80000007);
693 init_scattered_cpuid_features(c);
696 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
702 * First of all, decide if this is a 486 or higher
703 * It's a 486 if we can modify the AC flag
705 if (flag_is_changeable_p(X86_EFLAGS_AC))
710 for (i = 0; i < X86_VENDOR_NUM; i++)
711 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
712 c->x86_vendor_id[0] = 0;
713 cpu_devs[i]->c_identify(c);
714 if (c->x86_vendor_id[0]) {
723 * Do minimum CPU detection early.
724 * Fields really needed: vendor, cpuid_level, family, model, mask,
726 * The others are not touched to avoid unwanted side effects.
728 * WARNING: this function is only called on the BP. Don't add code here
729 * that is supposed to run on all CPUs.
731 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
734 c->x86_clflush_size = 64;
735 c->x86_phys_bits = 36;
736 c->x86_virt_bits = 48;
738 c->x86_clflush_size = 32;
739 c->x86_phys_bits = 32;
740 c->x86_virt_bits = 32;
742 c->x86_cache_alignment = c->x86_clflush_size;
744 memset(&c->x86_capability, 0, sizeof c->x86_capability);
745 c->extended_cpuid_level = 0;
748 identify_cpu_without_cpuid(c);
750 /* cyrix could have cpuid enabled via c_identify()*/
760 if (this_cpu->c_early_init)
761 this_cpu->c_early_init(c);
764 filter_cpuid_features(c, false);
768 if (this_cpu->c_bsp_init)
769 this_cpu->c_bsp_init(c);
771 if (c->x86_vendor != X86_VENDOR_AMD)
772 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
775 void __init early_cpu_init(void)
777 const struct cpu_dev *const *cdev;
780 #ifdef CONFIG_PROCESSOR_SELECT
781 printk(KERN_INFO "KERNEL supported cpus:\n");
784 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
785 const struct cpu_dev *cpudev = *cdev;
787 if (count >= X86_VENDOR_NUM)
789 cpu_devs[count] = cpudev;
792 #ifdef CONFIG_PROCESSOR_SELECT
796 for (j = 0; j < 2; j++) {
797 if (!cpudev->c_ident[j])
799 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
805 early_identify_cpu(&boot_cpu_data);
809 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
810 * unfortunately, that's not true in practice because of early VIA
811 * chips and (more importantly) broken virtualizers that are not easy
812 * to detect. In the latter case it doesn't even *fail* reliably, so
813 * probing for it doesn't even work. Disable it completely on 32-bit
814 * unless we can find a reliable way to detect all the broken cases.
815 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
817 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
820 clear_cpu_cap(c, X86_FEATURE_NOPL);
822 set_cpu_cap(c, X86_FEATURE_NOPL);
826 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
828 c->extended_cpuid_level = 0;
831 identify_cpu_without_cpuid(c);
833 /* cyrix could have cpuid enabled via c_identify()*/
843 if (c->cpuid_level >= 0x00000001) {
844 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
846 # ifdef CONFIG_X86_HT
847 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
849 c->apicid = c->initial_apicid;
852 c->phys_proc_id = c->initial_apicid;
857 get_model_name(c); /* Default name */
863 * This does the hard work of actually picking apart the CPU stuff...
865 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
869 c->loops_per_jiffy = loops_per_jiffy;
870 c->x86_cache_size = -1;
871 c->x86_vendor = X86_VENDOR_UNKNOWN;
872 c->x86_model = c->x86_mask = 0; /* So far unknown... */
873 c->x86_vendor_id[0] = '\0'; /* Unset */
874 c->x86_model_id[0] = '\0'; /* Unset */
875 c->x86_max_cores = 1;
876 c->x86_coreid_bits = 0;
878 c->x86_clflush_size = 64;
879 c->x86_phys_bits = 36;
880 c->x86_virt_bits = 48;
882 c->cpuid_level = -1; /* CPUID not detected */
883 c->x86_clflush_size = 32;
884 c->x86_phys_bits = 32;
885 c->x86_virt_bits = 32;
887 c->x86_cache_alignment = c->x86_clflush_size;
888 memset(&c->x86_capability, 0, sizeof c->x86_capability);
892 if (this_cpu->c_identify)
893 this_cpu->c_identify(c);
895 /* Clear/Set all flags overriden by options, after probe */
896 apply_forced_caps(c);
899 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
903 * Vendor-specific initialization. In this section we
904 * canonicalize the feature flags, meaning if there are
905 * features a certain CPU supports which CPUID doesn't
906 * tell us, CPUID claiming incorrect flags, or other bugs,
907 * we handle them here.
909 * At the end of this section, c->x86_capability better
910 * indicate the features this CPU genuinely supports!
912 if (this_cpu->c_init)
915 /* Disable the PN if appropriate */
916 squash_the_stupid_serial_number(c);
922 * The vendor-specific functions might have changed features.
923 * Now we do "generic changes."
926 /* Filter out anything that depends on CPUID levels we don't have */
927 filter_cpuid_features(c, true);
929 /* If the model name is still unset, do table lookup. */
930 if (!c->x86_model_id[0]) {
932 p = table_lookup_model(c);
934 strcpy(c->x86_model_id, p);
937 sprintf(c->x86_model_id, "%02x/%02x",
938 c->x86, c->x86_model);
949 * Clear/Set all flags overriden by options, need do it
950 * before following smp all cpus cap AND.
952 apply_forced_caps(c);
955 * On SMP, boot_cpu_data holds the common feature set between
956 * all CPUs; so make sure that we indicate which features are
957 * common between the CPUs. The first time this routine gets
958 * executed, c == &boot_cpu_data.
960 if (c != &boot_cpu_data) {
961 /* AND the already accumulated flags with these */
962 for (i = 0; i < NCAPINTS; i++)
963 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
965 /* OR, i.e. replicate the bug flags */
966 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
967 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
970 /* Init Machine Check Exception if available. */
973 select_idle_routine(c);
976 numa_add_cpu(smp_processor_id());
981 static void vgetcpu_set_mode(void)
983 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
984 vgetcpu_mode = VGETCPU_RDTSCP;
986 vgetcpu_mode = VGETCPU_LSL;
990 void __init identify_boot_cpu(void)
992 identify_cpu(&boot_cpu_data);
993 init_amd_e400_c1e_mask();
1002 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1004 BUG_ON(c == &boot_cpu_data);
1006 #ifdef CONFIG_X86_32
1017 static const struct msr_range msr_range_array[] __cpuinitconst = {
1018 { 0x00000000, 0x00000418},
1019 { 0xc0000000, 0xc000040b},
1020 { 0xc0010000, 0xc0010142},
1021 { 0xc0011000, 0xc001103b},
1024 static void __cpuinit print_cpu_msr(void)
1026 unsigned index_min, index_max;
1031 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1032 index_min = msr_range_array[i].min;
1033 index_max = msr_range_array[i].max;
1035 for (index = index_min; index < index_max; index++) {
1036 if (rdmsrl_amd_safe(index, &val))
1038 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1043 static int show_msr __cpuinitdata;
1045 static __init int setup_show_msr(char *arg)
1049 get_option(&arg, &num);
1055 __setup("show_msr=", setup_show_msr);
1057 static __init int setup_noclflush(char *arg)
1059 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1062 __setup("noclflush", setup_noclflush);
1064 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1066 const char *vendor = NULL;
1068 if (c->x86_vendor < X86_VENDOR_NUM) {
1069 vendor = this_cpu->c_vendor;
1071 if (c->cpuid_level >= 0)
1072 vendor = c->x86_vendor_id;
1075 if (vendor && !strstr(c->x86_model_id, vendor))
1076 printk(KERN_CONT "%s ", vendor);
1078 if (c->x86_model_id[0])
1079 printk(KERN_CONT "%s", c->x86_model_id);
1081 printk(KERN_CONT "%d86", c->x86);
1083 if (c->x86_mask || c->cpuid_level >= 0)
1084 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1086 printk(KERN_CONT "\n");
1089 if (c->cpu_index < show_msr)
1097 static __init int setup_disablecpuid(char *arg)
1101 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
1102 setup_clear_cpu_cap(bit);
1108 __setup("clearcpuid=", setup_disablecpuid);
1110 #ifdef CONFIG_X86_64
1111 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1113 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1114 irq_stack_union) __aligned(PAGE_SIZE);
1117 * The following four percpu variables are hot. Align current_task to
1118 * cacheline size such that all four fall in the same cacheline.
1120 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1122 EXPORT_PER_CPU_SYMBOL(current_task);
1124 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1125 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1126 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1128 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1129 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1131 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1134 * Special IST stacks which the CPU switches to when it calls
1135 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1136 * limit), all of them are 4K, except the debug stack which
1139 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1140 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1141 [DEBUG_STACK - 1] = DEBUG_STKSZ
1144 DEFINE_PER_CPU_PAGE_ALIGNED_USER_MAPPED(char, exception_stacks
1145 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1147 /* May not be marked __init: used by software suspend */
1148 void syscall_init(void)
1151 * LSTAR and STAR live in a bit strange symbiosis.
1152 * They both write to the same internal register. STAR allows to
1153 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1155 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1156 wrmsrl(MSR_LSTAR, system_call);
1157 wrmsrl(MSR_CSTAR, ignore_sysret);
1159 #ifdef CONFIG_IA32_EMULATION
1160 syscall32_cpu_init();
1163 /* Flags to clear on syscall */
1164 wrmsrl(MSR_SYSCALL_MASK,
1165 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1168 unsigned long kernel_eflags;
1171 * Copies of the original ist values from the tss are only accessed during
1172 * debugging, no special alignment required.
1174 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1176 #else /* CONFIG_X86_64 */
1178 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1179 EXPORT_PER_CPU_SYMBOL(current_task);
1181 #ifdef CONFIG_CC_STACKPROTECTOR
1182 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1185 /* Make sure %fs and %gs are initialized properly in idle threads */
1186 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1188 memset(regs, 0, sizeof(struct pt_regs));
1189 regs->fs = __KERNEL_PERCPU;
1190 regs->gs = __KERNEL_STACK_CANARY;
1194 #endif /* CONFIG_X86_64 */
1197 * Clear all 6 debug registers:
1199 static void clear_all_debug_regs(void)
1203 for (i = 0; i < 8; i++) {
1204 /* Ignore db4, db5 */
1205 if ((i == 4) || (i == 5))
1214 * Restore debug regs if using kgdbwait and you have a kernel debugger
1215 * connection established.
1217 static void dbg_restore_debug_regs(void)
1219 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1220 arch_kgdb_ops.correct_hw_break();
1222 #else /* ! CONFIG_KGDB */
1223 #define dbg_restore_debug_regs()
1224 #endif /* ! CONFIG_KGDB */
1227 * cpu_init() initializes state that is per-CPU. Some data is already
1228 * initialized (naturally) in the bootstrap process, such as the GDT
1229 * and IDT. We reload them nevertheless, this function acts as a
1230 * 'CPU state barrier', nothing should get across.
1231 * A lot of state is already set up in PDA init for 64 bit
1233 #ifdef CONFIG_X86_64
1235 void __cpuinit cpu_init(void)
1237 struct orig_ist *oist;
1238 struct task_struct *me;
1239 struct tss_struct *t;
1244 if (!kaiser_enabled) {
1246 * secondary_startup_64() deferred setting PGE in cr4:
1247 * init_memory_mapping() sets it on the boot cpu,
1248 * but it needs to be set on each secondary cpu.
1250 set_in_cr4(X86_CR4_PGE);
1253 cpu = stack_smp_processor_id();
1254 t = &per_cpu(init_tss, cpu);
1255 oist = &per_cpu(orig_ist, cpu);
1258 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1259 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1260 set_numa_node(early_cpu_to_node(cpu));
1265 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1266 panic("CPU#%d already initialized!\n", cpu);
1268 pr_debug("Initializing CPU#%d\n", cpu);
1270 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1273 * Initialize the per-CPU GDT with the boot GDT,
1274 * and set up the GDT descriptor:
1277 switch_to_new_gdt(cpu);
1280 load_idt((const struct desc_ptr *)&idt_descr);
1282 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1285 wrmsrl(MSR_FS_BASE, 0);
1286 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1294 * set up and load the per-CPU TSS
1296 if (!oist->ist[0]) {
1297 char *estacks = per_cpu(exception_stacks, cpu);
1299 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1300 estacks += exception_stack_sizes[v];
1301 oist->ist[v] = t->x86_tss.ist[v] =
1302 (unsigned long)estacks;
1306 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1309 * <= is required because the CPU will access up to
1310 * 8 bits beyond the end of the IO permission bitmap.
1312 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1313 t->io_bitmap[i] = ~0UL;
1315 atomic_inc(&init_mm.mm_count);
1316 me->active_mm = &init_mm;
1318 enter_lazy_tlb(&init_mm, me);
1320 load_sp0(t, ¤t->thread);
1321 set_tss_desc(cpu, t);
1323 load_mm_ldt(&init_mm);
1325 clear_all_debug_regs();
1326 dbg_restore_debug_regs();
1331 raw_local_save_flags(kernel_eflags);
1339 void __cpuinit cpu_init(void)
1341 int cpu = smp_processor_id();
1342 struct task_struct *curr = current;
1343 struct tss_struct *t = &per_cpu(init_tss, cpu);
1344 struct thread_struct *thread = &curr->thread;
1346 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1347 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1352 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1354 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1355 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1357 load_idt(&idt_descr);
1358 switch_to_new_gdt(cpu);
1361 * Set up and load the per-CPU TSS and LDT
1363 atomic_inc(&init_mm.mm_count);
1364 curr->active_mm = &init_mm;
1366 enter_lazy_tlb(&init_mm, curr);
1368 load_sp0(t, thread);
1369 set_tss_desc(cpu, t);
1371 load_mm_ldt(&init_mm);
1373 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1375 #ifdef CONFIG_DOUBLEFAULT
1376 /* Set up doublefault TSS pointer in the GDT */
1377 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1380 clear_all_debug_regs();
1381 dbg_restore_debug_regs();