2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/smp.h>
37 #include <asm/perf_event.h>
38 #include <asm/x86_init.h>
39 #include <asm/pgalloc.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
46 #include <asm/io_apic.h>
54 #include <asm/hypervisor.h>
56 unsigned int num_processors;
58 unsigned disabled_cpus __cpuinitdata;
60 /* Processor that is doing the boot up */
61 unsigned int boot_cpu_physical_apicid = -1U;
64 * The highest APIC ID seen during enumeration.
66 unsigned int max_physical_apicid;
69 * Bitmask of physically existing CPUs:
71 physid_mask_t phys_cpu_present_map;
74 * Map cpu index to physical APIC ID
76 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
77 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
84 * On x86_32, the mapping between cpu and logical apicid may vary
85 * depending on apic in use. The following early percpu variable is
86 * used for the mapping. This is where the behaviors of x86_64 and 32
87 * actually diverge. Let's keep it ugly for now.
89 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID);
92 * Knob to control our willingness to enable the local APIC.
96 static int force_enable_local_apic __initdata;
98 * APIC command line parameters
100 static int __init parse_lapic(char *arg)
102 force_enable_local_apic = 1;
105 early_param("lapic", parse_lapic);
106 /* Local APIC was disabled by the BIOS and enabled by the kernel */
107 static int enabled_via_apicbase;
110 * Handle interrupt mode configuration register (IMCR).
111 * This register controls whether the interrupt signals
112 * that reach the BSP come from the master PIC or from the
113 * local APIC. Before entering Symmetric I/O Mode, either
114 * the BIOS or the operating system must switch out of
115 * PIC Mode by changing the IMCR.
117 static inline void imcr_pic_to_apic(void)
119 /* select IMCR register */
121 /* NMI and 8259 INTR go through APIC */
125 static inline void imcr_apic_to_pic(void)
127 /* select IMCR register */
129 /* NMI and 8259 INTR go directly to BSP */
135 static int apic_calibrate_pmtmr __initdata;
136 static __init int setup_apicpmtimer(char *s)
138 apic_calibrate_pmtmr = 1;
142 __setup("apicpmtimer", setup_apicpmtimer);
146 #ifdef CONFIG_X86_X2APIC
147 /* x2apic enabled before OS handover */
148 static int x2apic_preenabled;
149 static __init int setup_nox2apic(char *str)
151 if (x2apic_enabled()) {
152 pr_warning("Bios already enabled x2apic, "
153 "can't enforce nox2apic");
157 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
160 early_param("nox2apic", setup_nox2apic);
163 unsigned long mp_lapic_addr;
165 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
166 static int disable_apic_timer __initdata;
167 /* Local APIC timer works in C2 */
168 int local_apic_timer_c2_ok;
169 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
171 int first_system_vector = 0xfe;
174 * Debug level, exported for io_apic.c
176 unsigned int apic_verbosity;
180 /* Have we found an MP table */
181 int smp_found_config;
183 static struct resource lapic_resource = {
184 .name = "Local APIC",
185 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
188 static unsigned int calibration_result;
190 static void apic_pm_activate(void);
192 static unsigned long apic_phys;
195 * Get the LAPIC version
197 static inline int lapic_get_version(void)
199 return GET_APIC_VERSION(apic_read(APIC_LVR));
203 * Check, if the APIC is integrated or a separate chip
205 static inline int lapic_is_integrated(void)
210 return APIC_INTEGRATED(lapic_get_version());
215 * Check, whether this is a modern or a first generation APIC
217 static int modern_apic(void)
219 /* AMD systems use old APIC versions, so check the CPU */
220 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
221 boot_cpu_data.x86 >= 0xf)
223 return lapic_get_version() >= 0x14;
227 * right after this call apic become NOOP driven
228 * so apic->write/read doesn't do anything
230 static void __init apic_disable(void)
232 pr_info("APIC: switched to apic NOOP\n");
236 void native_apic_wait_icr_idle(void)
238 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
242 u32 native_safe_apic_wait_icr_idle(void)
249 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
253 } while (timeout++ < 1000);
258 void native_apic_icr_write(u32 low, u32 id)
260 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
261 apic_write(APIC_ICR, low);
264 u64 native_apic_icr_read(void)
268 icr2 = apic_read(APIC_ICR2);
269 icr1 = apic_read(APIC_ICR);
271 return icr1 | ((u64)icr2 << 32);
276 * get_physical_broadcast - Get number of physical broadcast IDs
278 int get_physical_broadcast(void)
280 return modern_apic() ? 0xff : 0xf;
285 * lapic_get_maxlvt - get the maximum number of local vector table entries
287 int lapic_get_maxlvt(void)
291 v = apic_read(APIC_LVR);
293 * - we always have APIC integrated on 64bit mode
294 * - 82489DXs do not report # of LVT entries
296 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
304 #define APIC_DIVISOR 16
307 * This function sets up the local APIC timer, with a timeout of
308 * 'clocks' APIC bus clock. During calibration we actually call
309 * this function twice on the boot CPU, once with a bogus timeout
310 * value, second time for real. The other (noncalibrating) CPUs
311 * call this function only once, with the real, calibrated value.
313 * We do reads before writes even if unnecessary, to get around the
314 * P5 APIC double write bug.
316 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
318 unsigned int lvtt_value, tmp_value;
320 lvtt_value = LOCAL_TIMER_VECTOR;
322 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
323 if (!lapic_is_integrated())
324 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
327 lvtt_value |= APIC_LVT_MASKED;
329 apic_write(APIC_LVTT, lvtt_value);
334 tmp_value = apic_read(APIC_TDCR);
335 apic_write(APIC_TDCR,
336 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
340 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
344 * Setup extended LVT, AMD specific
346 * Software should use the LVT offsets the BIOS provides. The offsets
347 * are determined by the subsystems using it like those for MCE
348 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
349 * are supported. Beginning with family 10h at least 4 offsets are
352 * Since the offsets must be consistent for all cores, we keep track
353 * of the LVT offsets in software and reserve the offset for the same
354 * vector also to be used on other cores. An offset is freed by
355 * setting the entry to APIC_EILVT_MASKED.
357 * If the BIOS is right, there should be no conflicts. Otherwise a
358 * "[Firmware Bug]: ..." error message is generated. However, if
359 * software does not properly determines the offsets, it is not
360 * necessarily a BIOS bug.
363 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
365 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
367 return (old & APIC_EILVT_MASKED)
368 || (new == APIC_EILVT_MASKED)
369 || ((new & ~APIC_EILVT_MASKED) == old);
372 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
374 unsigned int rsvd; /* 0: uninitialized */
376 if (offset >= APIC_EILVT_NR_MAX)
379 rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED;
382 !eilvt_entry_is_changeable(rsvd, new))
383 /* may not change if vectors are different */
385 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
386 } while (rsvd != new);
392 * If mask=1, the LVT entry does not generate interrupts while mask=0
393 * enables the vector. See also the BKDGs. Must be called with
394 * preemption disabled.
397 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
399 unsigned long reg = APIC_EILVTn(offset);
400 unsigned int new, old, reserved;
402 new = (mask << 16) | (msg_type << 8) | vector;
403 old = apic_read(reg);
404 reserved = reserve_eilvt_offset(offset, new);
406 if (reserved != new) {
407 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
408 "vector 0x%x, but the register is already in use for "
409 "vector 0x%x on another cpu\n",
410 smp_processor_id(), reg, offset, new, reserved);
414 if (!eilvt_entry_is_changeable(old, new)) {
415 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
416 "vector 0x%x, but the register is already in use for "
417 "vector 0x%x on this cpu\n",
418 smp_processor_id(), reg, offset, new, old);
422 apic_write(reg, new);
426 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
429 * Program the next event, relative to now
431 static int lapic_next_event(unsigned long delta,
432 struct clock_event_device *evt)
434 apic_write(APIC_TMICT, delta);
439 * Setup the lapic timer in periodic or oneshot mode
441 static void lapic_timer_setup(enum clock_event_mode mode,
442 struct clock_event_device *evt)
447 /* Lapic used as dummy for broadcast ? */
448 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
451 local_irq_save(flags);
454 case CLOCK_EVT_MODE_PERIODIC:
455 case CLOCK_EVT_MODE_ONESHOT:
456 __setup_APIC_LVTT(calibration_result,
457 mode != CLOCK_EVT_MODE_PERIODIC, 1);
459 case CLOCK_EVT_MODE_UNUSED:
460 case CLOCK_EVT_MODE_SHUTDOWN:
461 v = apic_read(APIC_LVTT);
462 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
463 apic_write(APIC_LVTT, v);
464 apic_write(APIC_TMICT, 0);
466 case CLOCK_EVT_MODE_RESUME:
467 /* Nothing to do here */
471 local_irq_restore(flags);
475 * Local APIC timer broadcast function
477 static void lapic_timer_broadcast(const struct cpumask *mask)
480 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
486 * The local apic timer can be used for any function which is CPU local.
488 static struct clock_event_device lapic_clockevent = {
490 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
491 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
493 .set_mode = lapic_timer_setup,
494 .set_next_event = lapic_next_event,
495 .broadcast = lapic_timer_broadcast,
499 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
502 * Setup the local APIC timer for this CPU. Copy the initialized values
503 * of the boot CPU and register the clock event in the framework.
505 static void __cpuinit setup_APIC_timer(void)
507 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
509 if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_ARAT)) {
510 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
511 /* Make LAPIC timer preferrable over percpu HPET */
512 lapic_clockevent.rating = 150;
515 memcpy(levt, &lapic_clockevent, sizeof(*levt));
516 levt->cpumask = cpumask_of(smp_processor_id());
518 clockevents_register_device(levt);
522 * In this functions we calibrate APIC bus clocks to the external timer.
524 * We want to do the calibration only once since we want to have local timer
525 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
528 * This was previously done by reading the PIT/HPET and waiting for a wrap
529 * around to find out, that a tick has elapsed. I have a box, where the PIT
530 * readout is broken, so it never gets out of the wait loop again. This was
531 * also reported by others.
533 * Monitoring the jiffies value is inaccurate and the clockevents
534 * infrastructure allows us to do a simple substitution of the interrupt
537 * The calibration routine also uses the pm_timer when possible, as the PIT
538 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
539 * back to normal later in the boot process).
542 #define LAPIC_CAL_LOOPS (HZ/10)
544 static __initdata int lapic_cal_loops = -1;
545 static __initdata long lapic_cal_t1, lapic_cal_t2;
546 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
547 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
548 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
551 * Temporary interrupt handler.
553 static void __init lapic_cal_handler(struct clock_event_device *dev)
555 unsigned long long tsc = 0;
556 long tapic = apic_read(APIC_TMCCT);
557 unsigned long pm = acpi_pm_read_early();
562 switch (lapic_cal_loops++) {
564 lapic_cal_t1 = tapic;
565 lapic_cal_tsc1 = tsc;
567 lapic_cal_j1 = jiffies;
570 case LAPIC_CAL_LOOPS:
571 lapic_cal_t2 = tapic;
572 lapic_cal_tsc2 = tsc;
573 if (pm < lapic_cal_pm1)
574 pm += ACPI_PM_OVRRUN;
576 lapic_cal_j2 = jiffies;
582 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
584 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
585 const long pm_thresh = pm_100ms / 100;
589 #ifndef CONFIG_X86_PM_TIMER
593 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
595 /* Check, if the PM timer is available */
599 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
601 if (deltapm > (pm_100ms - pm_thresh) &&
602 deltapm < (pm_100ms + pm_thresh)) {
603 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
607 res = (((u64)deltapm) * mult) >> 22;
608 do_div(res, 1000000);
609 pr_warning("APIC calibration not consistent "
610 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
612 /* Correct the lapic counter value */
613 res = (((u64)(*delta)) * pm_100ms);
614 do_div(res, deltapm);
615 pr_info("APIC delta adjusted to PM-Timer: "
616 "%lu (%ld)\n", (unsigned long)res, *delta);
619 /* Correct the tsc counter value */
621 res = (((u64)(*deltatsc)) * pm_100ms);
622 do_div(res, deltapm);
623 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
624 "PM-Timer: %lu (%ld)\n",
625 (unsigned long)res, *deltatsc);
626 *deltatsc = (long)res;
632 static int __init calibrate_APIC_clock(void)
634 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
635 void (*real_handler)(struct clock_event_device *dev);
636 unsigned long deltaj;
637 long delta, deltatsc;
638 int pm_referenced = 0;
642 /* Replace the global interrupt handler */
643 real_handler = global_clock_event->event_handler;
644 global_clock_event->event_handler = lapic_cal_handler;
647 * Setup the APIC counter to maximum. There is no way the lapic
648 * can underflow in the 100ms detection time frame
650 __setup_APIC_LVTT(0xffffffff, 0, 0);
652 /* Let the interrupts run */
655 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
660 /* Restore the real event handler */
661 global_clock_event->event_handler = real_handler;
663 /* Build delta t1-t2 as apic timer counts down */
664 delta = lapic_cal_t1 - lapic_cal_t2;
665 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
667 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
669 /* we trust the PM based calibration if possible */
670 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
673 /* Calculate the scaled math multiplication factor */
674 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
675 lapic_clockevent.shift);
676 lapic_clockevent.max_delta_ns =
677 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
678 lapic_clockevent.min_delta_ns =
679 clockevent_delta2ns(0xF, &lapic_clockevent);
681 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
683 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
684 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
685 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
689 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
691 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
692 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
695 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
697 calibration_result / (1000000 / HZ),
698 calibration_result % (1000000 / HZ));
701 * Do a sanity check on the APIC calibration result
703 if (calibration_result < (1000000 / HZ)) {
705 pr_warning("APIC frequency too slow, disabling apic timer\n");
709 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
712 * PM timer calibration failed or not turned on
713 * so lets try APIC timer based calibration
715 if (!pm_referenced) {
716 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
719 * Setup the apic timer manually
721 levt->event_handler = lapic_cal_handler;
722 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
723 lapic_cal_loops = -1;
725 /* Let the interrupts run */
728 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
731 /* Stop the lapic timer */
732 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
735 deltaj = lapic_cal_j2 - lapic_cal_j1;
736 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
738 /* Check, if the jiffies result is consistent */
739 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
740 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
742 levt->features |= CLOCK_EVT_FEAT_DUMMY;
746 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
747 pr_warning("APIC timer disabled due to verification failure\n");
755 * Setup the boot APIC
757 * Calibrate and verify the result.
759 void __init setup_boot_APIC_clock(void)
762 * The local apic timer can be disabled via the kernel
763 * commandline or from the CPU detection code. Register the lapic
764 * timer as a dummy clock event source on SMP systems, so the
765 * broadcast mechanism is used. On UP systems simply ignore it.
767 if (disable_apic_timer) {
768 pr_info("Disabling APIC timer\n");
769 /* No broadcast on UP ! */
770 if (num_possible_cpus() > 1) {
771 lapic_clockevent.mult = 1;
777 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
778 "calibrating APIC timer ...\n");
780 if (calibrate_APIC_clock()) {
781 /* No broadcast on UP ! */
782 if (num_possible_cpus() > 1)
788 * If nmi_watchdog is set to IO_APIC, we need the
789 * PIT/HPET going. Otherwise register lapic as a dummy
792 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
794 /* Setup the lapic or request the broadcast */
798 void __cpuinit setup_secondary_APIC_clock(void)
804 * The guts of the apic timer interrupt
806 static void local_apic_timer_interrupt(void)
808 int cpu = smp_processor_id();
809 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
812 * Normally we should not be here till LAPIC has been initialized but
813 * in some cases like kdump, its possible that there is a pending LAPIC
814 * timer interrupt from previous kernel's context and is delivered in
815 * new kernel the moment interrupts are enabled.
817 * Interrupts are enabled early and LAPIC is setup much later, hence
818 * its possible that when we get here evt->event_handler is NULL.
819 * Check for event_handler being NULL and discard the interrupt as
822 if (!evt->event_handler) {
823 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
825 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
830 * the NMI deadlock-detector uses this.
832 inc_irq_stat(apic_timer_irqs);
834 evt->event_handler(evt);
838 * Local APIC timer interrupt. This is the most natural way for doing
839 * local interrupts, but local timer interrupts can be emulated by
840 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
842 * [ if a single-CPU system runs an SMP kernel then we call the local
843 * interrupt as well. Thus we cannot inline the local irq ... ]
845 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
847 struct pt_regs *old_regs = set_irq_regs(regs);
850 * NOTE! We'd better ACK the irq immediately,
851 * because timer handling can be slow.
855 * update_process_times() expects us to have done irq_enter().
856 * Besides, if we don't timer interrupts ignore the global
857 * interrupt lock, which is the WrongThing (tm) to do.
861 local_apic_timer_interrupt();
864 set_irq_regs(old_regs);
867 int setup_profiling_timer(unsigned int multiplier)
873 * Local APIC start and shutdown
877 * clear_local_APIC - shutdown the local APIC
879 * This is called, when a CPU is disabled and before rebooting, so the state of
880 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
881 * leftovers during boot.
883 void clear_local_APIC(void)
888 /* APIC hasn't been mapped yet */
889 if (!x2apic_mode && !apic_phys)
892 maxlvt = lapic_get_maxlvt();
894 * Masking an LVT entry can trigger a local APIC error
895 * if the vector is zero. Mask LVTERR first to prevent this.
898 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
899 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
902 * Careful: we have to set masks only first to deassert
903 * any level-triggered sources.
905 v = apic_read(APIC_LVTT);
906 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
907 v = apic_read(APIC_LVT0);
908 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
909 v = apic_read(APIC_LVT1);
910 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
912 v = apic_read(APIC_LVTPC);
913 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
916 /* lets not touch this if we didn't frob it */
917 #ifdef CONFIG_X86_THERMAL_VECTOR
919 v = apic_read(APIC_LVTTHMR);
920 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
923 #ifdef CONFIG_X86_MCE_INTEL
925 v = apic_read(APIC_LVTCMCI);
926 if (!(v & APIC_LVT_MASKED))
927 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
932 * Clean APIC state for other OSs:
934 apic_write(APIC_LVTT, APIC_LVT_MASKED);
935 apic_write(APIC_LVT0, APIC_LVT_MASKED);
936 apic_write(APIC_LVT1, APIC_LVT_MASKED);
938 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
940 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
942 /* Integrated APIC (!82489DX) ? */
943 if (lapic_is_integrated()) {
945 /* Clear ESR due to Pentium errata 3AP and 11AP */
946 apic_write(APIC_ESR, 0);
952 * disable_local_APIC - clear and disable the local APIC
954 void disable_local_APIC(void)
958 /* APIC hasn't been mapped yet */
959 if (!x2apic_mode && !apic_phys)
965 * Disable APIC (implies clearing of registers
968 value = apic_read(APIC_SPIV);
969 value &= ~APIC_SPIV_APIC_ENABLED;
970 apic_write(APIC_SPIV, value);
974 * When LAPIC was disabled by the BIOS and enabled by the kernel,
975 * restore the disabled state.
977 if (enabled_via_apicbase) {
980 rdmsr(MSR_IA32_APICBASE, l, h);
981 l &= ~MSR_IA32_APICBASE_ENABLE;
982 wrmsr(MSR_IA32_APICBASE, l, h);
988 * If Linux enabled the LAPIC against the BIOS default disable it down before
989 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
990 * not power-off. Additionally clear all LVT entries before disable_local_APIC
991 * for the case where Linux didn't enable the LAPIC.
993 void lapic_shutdown(void)
997 if (!cpu_has_apic && !apic_from_smp_config())
1000 local_irq_save(flags);
1002 #ifdef CONFIG_X86_32
1003 if (!enabled_via_apicbase)
1007 disable_local_APIC();
1010 local_irq_restore(flags);
1014 * This is to verify that we're looking at a real local APIC.
1015 * Check these against your board if the CPUs aren't getting
1016 * started for no apparent reason.
1018 int __init verify_local_APIC(void)
1020 unsigned int reg0, reg1;
1023 * The version register is read-only in a real APIC.
1025 reg0 = apic_read(APIC_LVR);
1026 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1027 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1028 reg1 = apic_read(APIC_LVR);
1029 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1032 * The two version reads above should print the same
1033 * numbers. If the second one is different, then we
1034 * poke at a non-APIC.
1040 * Check if the version looks reasonably.
1042 reg1 = GET_APIC_VERSION(reg0);
1043 if (reg1 == 0x00 || reg1 == 0xff)
1045 reg1 = lapic_get_maxlvt();
1046 if (reg1 < 0x02 || reg1 == 0xff)
1050 * The ID register is read/write in a real APIC.
1052 reg0 = apic_read(APIC_ID);
1053 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1054 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1055 reg1 = apic_read(APIC_ID);
1056 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1057 apic_write(APIC_ID, reg0);
1058 if (reg1 != (reg0 ^ apic->apic_id_mask))
1062 * The next two are just to see if we have sane values.
1063 * They're only really relevant if we're in Virtual Wire
1064 * compatibility mode, but most boxes are anymore.
1066 reg0 = apic_read(APIC_LVT0);
1067 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1068 reg1 = apic_read(APIC_LVT1);
1069 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1075 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1077 void __init sync_Arb_IDs(void)
1080 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1083 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1089 apic_wait_icr_idle();
1091 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1092 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1093 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1097 * An initial setup of the virtual wire mode.
1099 void __init init_bsp_APIC(void)
1104 * Don't do the setup now if we have a SMP BIOS as the
1105 * through-I/O-APIC virtual wire mode might be active.
1107 if (smp_found_config || !cpu_has_apic)
1111 * Do not trust the local APIC being empty at bootup.
1118 value = apic_read(APIC_SPIV);
1119 value &= ~APIC_VECTOR_MASK;
1120 value |= APIC_SPIV_APIC_ENABLED;
1122 #ifdef CONFIG_X86_32
1123 /* This bit is reserved on P4/Xeon and should be cleared */
1124 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1125 (boot_cpu_data.x86 == 15))
1126 value &= ~APIC_SPIV_FOCUS_DISABLED;
1129 value |= APIC_SPIV_FOCUS_DISABLED;
1130 value |= SPURIOUS_APIC_VECTOR;
1131 apic_write(APIC_SPIV, value);
1134 * Set up the virtual wire mode.
1136 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1137 value = APIC_DM_NMI;
1138 if (!lapic_is_integrated()) /* 82489DX */
1139 value |= APIC_LVT_LEVEL_TRIGGER;
1140 apic_write(APIC_LVT1, value);
1143 static void __cpuinit lapic_setup_esr(void)
1145 unsigned int oldvalue, value, maxlvt;
1147 if (!lapic_is_integrated()) {
1148 pr_info("No ESR for 82489DX.\n");
1152 if (apic->disable_esr) {
1154 * Something untraceable is creating bad interrupts on
1155 * secondary quads ... for the moment, just leave the
1156 * ESR disabled - we can't do anything useful with the
1157 * errors anyway - mbligh
1159 pr_info("Leaving ESR disabled.\n");
1163 maxlvt = lapic_get_maxlvt();
1164 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1165 apic_write(APIC_ESR, 0);
1166 oldvalue = apic_read(APIC_ESR);
1168 /* enables sending errors */
1169 value = ERROR_APIC_VECTOR;
1170 apic_write(APIC_LVTERR, value);
1173 * spec says clear errors after enabling vector.
1176 apic_write(APIC_ESR, 0);
1177 value = apic_read(APIC_ESR);
1178 if (value != oldvalue)
1179 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1180 "vector: 0x%08x after: 0x%08x\n",
1185 * setup_local_APIC - setup the local APIC
1187 * Used to setup local APIC while initializing BSP or bringin up APs.
1188 * Always called with preemption disabled.
1190 void __cpuinit setup_local_APIC(void)
1192 int cpu = smp_processor_id();
1193 unsigned int value, queued;
1194 int i, j, acked = 0;
1195 unsigned long long tsc = 0, ntsc;
1196 long long max_loops = cpu_khz;
1202 disable_ioapic_support();
1206 #ifdef CONFIG_X86_32
1207 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1208 if (lapic_is_integrated() && apic->disable_esr) {
1209 apic_write(APIC_ESR, 0);
1210 apic_write(APIC_ESR, 0);
1211 apic_write(APIC_ESR, 0);
1212 apic_write(APIC_ESR, 0);
1215 perf_events_lapic_init();
1218 * Double-check whether this APIC is really registered.
1219 * This is meaningless in clustered apic mode, so we skip it.
1221 BUG_ON(!apic->apic_id_registered());
1224 * Intel recommends to set DFR, LDR and TPR before enabling
1225 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1226 * document number 292116). So here it goes...
1228 apic->init_apic_ldr();
1230 #ifdef CONFIG_X86_32
1232 * APIC LDR is initialized. If logical_apicid mapping was
1233 * initialized during get_smp_config(), make sure it matches the
1236 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1237 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1238 /* always use the value from LDR */
1239 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1240 logical_smp_processor_id();
1244 * Set Task Priority to 'accept all'. We never change this
1247 value = apic_read(APIC_TASKPRI);
1248 value &= ~APIC_TPRI_MASK;
1249 apic_write(APIC_TASKPRI, value);
1252 * After a crash, we no longer service the interrupts and a pending
1253 * interrupt from previous kernel might still have ISR bit set.
1255 * Most probably by now CPU has serviced that pending interrupt and
1256 * it might not have done the ack_APIC_irq() because it thought,
1257 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1258 * does not clear the ISR bit and cpu thinks it has already serivced
1259 * the interrupt. Hence a vector might get locked. It was noticed
1260 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1264 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1265 queued |= apic_read(APIC_IRR + i*0x10);
1267 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1268 value = apic_read(APIC_ISR + i*0x10);
1269 for (j = 31; j >= 0; j--) {
1270 if (value & (1<<j)) {
1277 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1283 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1286 } while (queued && max_loops > 0);
1287 WARN_ON(max_loops <= 0);
1290 * Now that we are all set up, enable the APIC
1292 value = apic_read(APIC_SPIV);
1293 value &= ~APIC_VECTOR_MASK;
1297 value |= APIC_SPIV_APIC_ENABLED;
1299 #ifdef CONFIG_X86_32
1301 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1302 * certain networking cards. If high frequency interrupts are
1303 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1304 * entry is masked/unmasked at a high rate as well then sooner or
1305 * later IOAPIC line gets 'stuck', no more interrupts are received
1306 * from the device. If focus CPU is disabled then the hang goes
1309 * [ This bug can be reproduced easily with a level-triggered
1310 * PCI Ne2000 networking cards and PII/PIII processors, dual
1314 * Actually disabling the focus CPU check just makes the hang less
1315 * frequent as it makes the interrupt distributon model be more
1316 * like LRU than MRU (the short-term load is more even across CPUs).
1317 * See also the comment in end_level_ioapic_irq(). --macro
1321 * - enable focus processor (bit==0)
1322 * - 64bit mode always use processor focus
1323 * so no need to set it
1325 value &= ~APIC_SPIV_FOCUS_DISABLED;
1329 * Set spurious IRQ vector
1331 value |= SPURIOUS_APIC_VECTOR;
1332 apic_write(APIC_SPIV, value);
1335 * Set up LVT0, LVT1:
1337 * set up through-local-APIC on the BP's LINT0. This is not
1338 * strictly necessary in pure symmetric-IO mode, but sometimes
1339 * we delegate interrupts to the 8259A.
1342 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1344 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1345 if (!cpu && (pic_mode || !value)) {
1346 value = APIC_DM_EXTINT;
1347 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1349 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1350 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1352 apic_write(APIC_LVT0, value);
1355 * only the BP should see the LINT1 NMI signal, obviously.
1358 value = APIC_DM_NMI;
1360 value = APIC_DM_NMI | APIC_LVT_MASKED;
1361 if (!lapic_is_integrated()) /* 82489DX */
1362 value |= APIC_LVT_LEVEL_TRIGGER;
1363 apic_write(APIC_LVT1, value);
1365 #ifdef CONFIG_X86_MCE_INTEL
1366 /* Recheck CMCI information after local APIC is up on CPU #0 */
1372 void __cpuinit end_local_APIC_setup(void)
1376 #ifdef CONFIG_X86_32
1379 /* Disable the local apic timer */
1380 value = apic_read(APIC_LVTT);
1381 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1382 apic_write(APIC_LVTT, value);
1389 void __init bsp_end_local_APIC_setup(void)
1391 end_local_APIC_setup();
1394 * Now that local APIC setup is completed for BP, configure the fault
1395 * handling for interrupt remapping.
1397 if (intr_remapping_enabled)
1398 enable_drhd_fault_handling();
1402 #ifdef CONFIG_X86_X2APIC
1403 void check_x2apic(void)
1405 if (x2apic_enabled()) {
1406 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1407 x2apic_preenabled = x2apic_mode = 1;
1411 void enable_x2apic(void)
1418 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1419 if (!(msr & X2APIC_ENABLE)) {
1420 printk_once(KERN_INFO "Enabling x2apic\n");
1421 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1424 #endif /* CONFIG_X86_X2APIC */
1426 int __init enable_IR(void)
1428 #ifdef CONFIG_INTR_REMAP
1429 if (!intr_remapping_supported()) {
1430 pr_debug("intr-remapping not supported\n");
1434 if (!x2apic_preenabled && skip_ioapic_setup) {
1435 pr_info("Skipped enabling intr-remap because of skipping "
1440 if (enable_intr_remapping(x2apic_supported()))
1443 pr_info("Enabled Interrupt-remapping\n");
1451 void __init enable_IR_x2apic(void)
1453 unsigned long flags;
1454 struct IO_APIC_route_entry **ioapic_entries;
1455 int ret, x2apic_enabled = 0;
1456 int dmar_table_init_ret;
1458 dmar_table_init_ret = dmar_table_init();
1459 if (dmar_table_init_ret && !x2apic_supported())
1462 ioapic_entries = alloc_ioapic_entries();
1463 if (!ioapic_entries) {
1464 pr_err("Allocate ioapic_entries failed\n");
1468 ret = save_IO_APIC_setup(ioapic_entries);
1470 pr_info("Saving IO-APIC state failed: %d\n", ret);
1474 local_irq_save(flags);
1475 legacy_pic->mask_all();
1476 mask_IO_APIC_setup(ioapic_entries);
1478 if (dmar_table_init_ret)
1484 /* IR is required if there is APIC ID > 255 even when running
1487 if (max_physical_apicid > 255 ||
1488 !hypervisor_x2apic_available())
1491 * without IR all CPUs can be addressed by IOAPIC/MSI
1492 * only in physical mode
1494 x2apic_force_phys();
1499 if (x2apic_supported() && !x2apic_mode) {
1502 pr_info("Enabled x2apic\n");
1506 if (!ret) /* IR enabling failed */
1507 restore_IO_APIC_setup(ioapic_entries);
1508 legacy_pic->restore_mask();
1509 local_irq_restore(flags);
1513 free_ioapic_entries(ioapic_entries);
1518 if (x2apic_preenabled)
1519 panic("x2apic: enabled by BIOS but kernel init failed.");
1520 else if (cpu_has_x2apic)
1521 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1524 #ifdef CONFIG_X86_64
1526 * Detect and enable local APICs on non-SMP boards.
1527 * Original code written by Keir Fraser.
1528 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1529 * not correctly set up (usually the APIC timer won't work etc.)
1531 static int __init detect_init_APIC(void)
1533 if (!cpu_has_apic) {
1534 pr_info("No local APIC present\n");
1538 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1543 static int __init apic_verify(void)
1548 * The APIC feature bit should now be enabled
1551 features = cpuid_edx(1);
1552 if (!(features & (1 << X86_FEATURE_APIC))) {
1553 pr_warning("Could not enable APIC!\n");
1556 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1557 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1559 /* The BIOS may have set up the APIC at some other address */
1560 rdmsr(MSR_IA32_APICBASE, l, h);
1561 if (l & MSR_IA32_APICBASE_ENABLE)
1562 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1564 pr_info("Found and enabled local APIC!\n");
1568 int __init apic_force_enable(unsigned long addr)
1576 * Some BIOSes disable the local APIC in the APIC_BASE
1577 * MSR. This can only be done in software for Intel P6 or later
1578 * and AMD K7 (Model > 1) or later.
1580 rdmsr(MSR_IA32_APICBASE, l, h);
1581 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1582 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1583 l &= ~MSR_IA32_APICBASE_BASE;
1584 l |= MSR_IA32_APICBASE_ENABLE | addr;
1585 wrmsr(MSR_IA32_APICBASE, l, h);
1586 enabled_via_apicbase = 1;
1588 return apic_verify();
1592 * Detect and initialize APIC
1594 static int __init detect_init_APIC(void)
1596 /* Disabled by kernel option? */
1600 switch (boot_cpu_data.x86_vendor) {
1601 case X86_VENDOR_AMD:
1602 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1603 (boot_cpu_data.x86 >= 15))
1606 case X86_VENDOR_INTEL:
1607 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1608 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1615 if (!cpu_has_apic) {
1617 * Over-ride BIOS and try to enable the local APIC only if
1618 * "lapic" specified.
1620 if (!force_enable_local_apic) {
1621 pr_info("Local APIC disabled by BIOS -- "
1622 "you can enable it with \"lapic\"\n");
1625 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1637 pr_info("No local APIC present or hardware disabled\n");
1643 * init_apic_mappings - initialize APIC mappings
1645 void __init init_apic_mappings(void)
1647 unsigned int new_apicid;
1650 boot_cpu_physical_apicid = read_apic_id();
1654 /* If no local APIC can be found return early */
1655 if (!smp_found_config && detect_init_APIC()) {
1656 /* lets NOP'ify apic operations */
1657 pr_info("APIC: disable apic facility\n");
1660 apic_phys = mp_lapic_addr;
1663 * acpi lapic path already maps that address in
1664 * acpi_register_lapic_address()
1666 if (!acpi_lapic && !smp_found_config)
1667 register_lapic_address(apic_phys);
1671 * Fetch the APIC ID of the BSP in case we have a
1672 * default configuration (or the MP table is broken).
1674 new_apicid = read_apic_id();
1675 if (boot_cpu_physical_apicid != new_apicid) {
1676 boot_cpu_physical_apicid = new_apicid;
1678 * yeah -- we lie about apic_version
1679 * in case if apic was disabled via boot option
1680 * but it's not a problem for SMP compiled kernel
1681 * since smp_sanity_check is prepared for such a case
1682 * and disable smp mode
1684 apic_version[new_apicid] =
1685 GET_APIC_VERSION(apic_read(APIC_LVR));
1689 void __init register_lapic_address(unsigned long address)
1691 mp_lapic_addr = address;
1694 set_fixmap_nocache(FIX_APIC_BASE, address);
1695 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1696 APIC_BASE, mp_lapic_addr);
1698 if (boot_cpu_physical_apicid == -1U) {
1699 boot_cpu_physical_apicid = read_apic_id();
1700 apic_version[boot_cpu_physical_apicid] =
1701 GET_APIC_VERSION(apic_read(APIC_LVR));
1706 * This initializes the IO-APIC and APIC hardware if this is
1709 int apic_version[MAX_LOCAL_APIC];
1711 int __init APIC_init_uniprocessor(void)
1714 pr_info("Apic disabled\n");
1717 #ifdef CONFIG_X86_64
1718 if (!cpu_has_apic) {
1720 pr_info("Apic disabled by BIOS\n");
1724 if (!smp_found_config && !cpu_has_apic)
1728 * Complain if the BIOS pretends there is one.
1730 if (!cpu_has_apic &&
1731 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1732 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1733 boot_cpu_physical_apicid);
1738 default_setup_apic_routing();
1740 verify_local_APIC();
1743 #ifdef CONFIG_X86_64
1744 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1747 * Hack: In case of kdump, after a crash, kernel might be booting
1748 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1749 * might be zero if read from MP tables. Get it from LAPIC.
1751 # ifdef CONFIG_CRASH_DUMP
1752 boot_cpu_physical_apicid = read_apic_id();
1755 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1758 #ifdef CONFIG_X86_IO_APIC
1760 * Now enable IO-APICs, actually call clear_IO_APIC
1761 * We need clear_IO_APIC before enabling error vector
1763 if (!skip_ioapic_setup && nr_ioapics)
1767 bsp_end_local_APIC_setup();
1769 #ifdef CONFIG_X86_IO_APIC
1770 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1777 x86_init.timers.setup_percpu_clockev();
1782 * Local APIC interrupts
1786 * This interrupt should _never_ happen with our APIC/SMP architecture
1788 void smp_spurious_interrupt(struct pt_regs *regs)
1795 * Check if this really is a spurious interrupt and ACK it
1796 * if it is a vectored one. Just in case...
1797 * Spurious interrupts should not be ACKed.
1799 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1800 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1803 inc_irq_stat(irq_spurious_count);
1805 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1806 pr_info("spurious APIC interrupt on CPU#%d, "
1807 "should never happen.\n", smp_processor_id());
1812 * This interrupt should never happen with our APIC/SMP architecture
1814 void smp_error_interrupt(struct pt_regs *regs)
1820 /* First tickle the hardware, only then report what went on. -- REW */
1821 v = apic_read(APIC_ESR);
1822 apic_write(APIC_ESR, 0);
1823 v1 = apic_read(APIC_ESR);
1825 atomic_inc(&irq_err_count);
1828 * Here is what the APIC error bits mean:
1830 * 1: Receive CS error
1831 * 2: Send accept error
1832 * 3: Receive accept error
1834 * 5: Send illegal vector
1835 * 6: Received illegal vector
1836 * 7: Illegal register address
1838 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1839 smp_processor_id(), v , v1);
1844 * connect_bsp_APIC - attach the APIC to the interrupt system
1846 void __init connect_bsp_APIC(void)
1848 #ifdef CONFIG_X86_32
1851 * Do not trust the local APIC being empty at bootup.
1855 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1856 * local APIC to INT and NMI lines.
1858 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1859 "enabling APIC mode.\n");
1863 if (apic->enable_apic_mode)
1864 apic->enable_apic_mode();
1868 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1869 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1871 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1874 void disconnect_bsp_APIC(int virt_wire_setup)
1878 #ifdef CONFIG_X86_32
1881 * Put the board back into PIC mode (has an effect only on
1882 * certain older boards). Note that APIC interrupts, including
1883 * IPIs, won't work beyond this point! The only exception are
1886 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1887 "entering PIC mode.\n");
1893 /* Go back to Virtual Wire compatibility mode */
1895 /* For the spurious interrupt use vector F, and enable it */
1896 value = apic_read(APIC_SPIV);
1897 value &= ~APIC_VECTOR_MASK;
1898 value |= APIC_SPIV_APIC_ENABLED;
1900 apic_write(APIC_SPIV, value);
1902 if (!virt_wire_setup) {
1904 * For LVT0 make it edge triggered, active high,
1905 * external and enabled
1907 value = apic_read(APIC_LVT0);
1908 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1909 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1910 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1911 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1912 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1913 apic_write(APIC_LVT0, value);
1916 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1920 * For LVT1 make it edge triggered, active high,
1923 value = apic_read(APIC_LVT1);
1924 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1925 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1926 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1927 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1928 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1929 apic_write(APIC_LVT1, value);
1932 void __cpuinit generic_processor_info(int apicid, int version)
1936 if (num_processors >= nr_cpu_ids) {
1937 int max = nr_cpu_ids;
1938 int thiscpu = max + disabled_cpus;
1941 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1942 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1949 if (apicid == boot_cpu_physical_apicid) {
1951 * x86_bios_cpu_apicid is required to have processors listed
1952 * in same order as logical cpu numbers. Hence the first
1953 * entry is BSP, and so on.
1954 * boot_cpu_init() already hold bit 0 in cpu_present_mask
1959 cpu = cpumask_next_zero(-1, cpu_present_mask);
1964 if (version == 0x0) {
1965 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
1969 apic_version[apicid] = version;
1971 if (version != apic_version[boot_cpu_physical_apicid]) {
1972 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
1973 apic_version[boot_cpu_physical_apicid], cpu, version);
1976 physid_set(apicid, phys_cpu_present_map);
1977 if (apicid > max_physical_apicid)
1978 max_physical_apicid = apicid;
1980 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1981 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1982 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1984 #ifdef CONFIG_X86_32
1985 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1986 apic->x86_32_early_logical_apicid(cpu);
1988 set_cpu_possible(cpu, true);
1989 set_cpu_present(cpu, true);
1992 int hard_smp_processor_id(void)
1994 return read_apic_id();
1997 void default_init_apic_ldr(void)
2001 apic_write(APIC_DFR, APIC_DFR_VALUE);
2002 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2003 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2004 apic_write(APIC_LDR, val);
2007 #ifdef CONFIG_X86_32
2008 int default_x86_32_numa_cpu_node(int cpu)
2011 int apicid = early_per_cpu(x86_cpu_to_apicid, cpu);
2013 if (apicid != BAD_APICID)
2014 return __apicid_to_node[apicid];
2015 return NUMA_NO_NODE;
2029 * 'active' is true if the local APIC was enabled by us and
2030 * not the BIOS; this signifies that we are also responsible
2031 * for disabling it before entering apm/acpi suspend
2034 /* r/w apic fields */
2035 unsigned int apic_id;
2036 unsigned int apic_taskpri;
2037 unsigned int apic_ldr;
2038 unsigned int apic_dfr;
2039 unsigned int apic_spiv;
2040 unsigned int apic_lvtt;
2041 unsigned int apic_lvtpc;
2042 unsigned int apic_lvt0;
2043 unsigned int apic_lvt1;
2044 unsigned int apic_lvterr;
2045 unsigned int apic_tmict;
2046 unsigned int apic_tdcr;
2047 unsigned int apic_thmr;
2050 static int lapic_suspend(void)
2052 unsigned long flags;
2055 if (!apic_pm_state.active)
2058 maxlvt = lapic_get_maxlvt();
2060 apic_pm_state.apic_id = apic_read(APIC_ID);
2061 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2062 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2063 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2064 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2065 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2067 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2068 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2069 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2070 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2071 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2072 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2073 #ifdef CONFIG_X86_THERMAL_VECTOR
2075 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2078 local_irq_save(flags);
2079 disable_local_APIC();
2081 if (intr_remapping_enabled)
2082 disable_intr_remapping();
2084 local_irq_restore(flags);
2088 static void lapic_resume(void)
2091 unsigned long flags;
2093 struct IO_APIC_route_entry **ioapic_entries = NULL;
2095 if (!apic_pm_state.active)
2098 local_irq_save(flags);
2099 if (intr_remapping_enabled) {
2100 ioapic_entries = alloc_ioapic_entries();
2101 if (!ioapic_entries) {
2102 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2106 ret = save_IO_APIC_setup(ioapic_entries);
2108 WARN(1, "Saving IO-APIC state failed: %d\n", ret);
2109 free_ioapic_entries(ioapic_entries);
2113 mask_IO_APIC_setup(ioapic_entries);
2114 legacy_pic->mask_all();
2121 * Make sure the APICBASE points to the right address
2123 * FIXME! This will be wrong if we ever support suspend on
2124 * SMP! We'll need to do this as part of the CPU restore!
2126 rdmsr(MSR_IA32_APICBASE, l, h);
2127 l &= ~MSR_IA32_APICBASE_BASE;
2128 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2129 wrmsr(MSR_IA32_APICBASE, l, h);
2132 maxlvt = lapic_get_maxlvt();
2133 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2134 apic_write(APIC_ID, apic_pm_state.apic_id);
2135 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2136 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2137 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2138 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2139 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2140 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2141 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2143 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2146 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2147 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2148 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2149 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2150 apic_write(APIC_ESR, 0);
2151 apic_read(APIC_ESR);
2152 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2153 apic_write(APIC_ESR, 0);
2154 apic_read(APIC_ESR);
2156 if (intr_remapping_enabled) {
2157 reenable_intr_remapping(x2apic_mode);
2158 legacy_pic->restore_mask();
2159 restore_IO_APIC_setup(ioapic_entries);
2160 free_ioapic_entries(ioapic_entries);
2163 local_irq_restore(flags);
2167 * This device has no shutdown method - fully functioning local APICs
2168 * are needed on every CPU up until machine_halt/restart/poweroff.
2171 static struct syscore_ops lapic_syscore_ops = {
2172 .resume = lapic_resume,
2173 .suspend = lapic_suspend,
2176 static void __cpuinit apic_pm_activate(void)
2178 apic_pm_state.active = 1;
2181 static int __init init_lapic_sysfs(void)
2183 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2185 register_syscore_ops(&lapic_syscore_ops);
2190 /* local apic needs to resume before other devices access its registers. */
2191 core_initcall(init_lapic_sysfs);
2193 #else /* CONFIG_PM */
2195 static void apic_pm_activate(void) { }
2197 #endif /* CONFIG_PM */
2199 #ifdef CONFIG_X86_64
2201 static int __cpuinit apic_cluster_num(void)
2203 int i, clusters, zeros;
2205 u16 *bios_cpu_apicid;
2206 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2208 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2209 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2211 for (i = 0; i < nr_cpu_ids; i++) {
2212 /* are we being called early in kernel startup? */
2213 if (bios_cpu_apicid) {
2214 id = bios_cpu_apicid[i];
2215 } else if (i < nr_cpu_ids) {
2217 id = per_cpu(x86_bios_cpu_apicid, i);
2223 if (id != BAD_APICID)
2224 __set_bit(APIC_CLUSTERID(id), clustermap);
2227 /* Problem: Partially populated chassis may not have CPUs in some of
2228 * the APIC clusters they have been allocated. Only present CPUs have
2229 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2230 * Since clusters are allocated sequentially, count zeros only if
2231 * they are bounded by ones.
2235 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2236 if (test_bit(i, clustermap)) {
2237 clusters += 1 + zeros;
2246 static int __cpuinitdata multi_checked;
2247 static int __cpuinitdata multi;
2249 static int __cpuinit set_multi(const struct dmi_system_id *d)
2253 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2258 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2260 .callback = set_multi,
2261 .ident = "IBM System Summit2",
2263 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2264 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2270 static void __cpuinit dmi_check_multi(void)
2275 dmi_check_system(multi_dmi_table);
2280 * apic_is_clustered_box() -- Check if we can expect good TSC
2282 * Thus far, the major user of this is IBM's Summit2 series:
2283 * Clustered boxes may have unsynced TSC problems if they are
2285 * Use DMI to check them
2287 __cpuinit int apic_is_clustered_box(void)
2297 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2298 * not guaranteed to be synced between boards
2300 if (apic_cluster_num() > 1)
2308 * APIC command line parameters
2310 static int __init setup_disableapic(char *arg)
2313 setup_clear_cpu_cap(X86_FEATURE_APIC);
2316 early_param("disableapic", setup_disableapic);
2318 /* same as disableapic, for compatibility */
2319 static int __init setup_nolapic(char *arg)
2321 return setup_disableapic(arg);
2323 early_param("nolapic", setup_nolapic);
2325 static int __init parse_lapic_timer_c2_ok(char *arg)
2327 local_apic_timer_c2_ok = 1;
2330 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2332 static int __init parse_disable_apic_timer(char *arg)
2334 disable_apic_timer = 1;
2337 early_param("noapictimer", parse_disable_apic_timer);
2339 static int __init parse_nolapic_timer(char *arg)
2341 disable_apic_timer = 1;
2344 early_param("nolapic_timer", parse_nolapic_timer);
2346 static int __init apic_set_verbosity(char *arg)
2349 #ifdef CONFIG_X86_64
2350 skip_ioapic_setup = 0;
2356 if (strcmp("debug", arg) == 0)
2357 apic_verbosity = APIC_DEBUG;
2358 else if (strcmp("verbose", arg) == 0)
2359 apic_verbosity = APIC_VERBOSE;
2361 pr_warning("APIC Verbosity level %s not recognised"
2362 " use apic=verbose or apic=debug\n", arg);
2368 early_param("apic", apic_set_verbosity);
2370 static int __init lapic_insert_resource(void)
2375 /* Put local APIC into the resource map. */
2376 lapic_resource.start = apic_phys;
2377 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2378 insert_resource(&iomem_resource, &lapic_resource);
2384 * need call insert after e820_reserve_resources()
2385 * that is using request_resource
2387 late_initcall(lapic_insert_resource);