2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops;
50 * general struct to manage commands send to an IOMMU
56 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
57 struct unity_map_entry *e);
58 static struct dma_ops_domain *find_protection_domain(u16 devid);
61 #ifdef CONFIG_AMD_IOMMU_STATS
64 * Initialization code for statistics collection
67 DECLARE_STATS_COUNTER(compl_wait);
68 DECLARE_STATS_COUNTER(cnt_map_single);
69 DECLARE_STATS_COUNTER(cnt_unmap_single);
70 DECLARE_STATS_COUNTER(cnt_map_sg);
71 DECLARE_STATS_COUNTER(cnt_unmap_sg);
72 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
73 DECLARE_STATS_COUNTER(cnt_free_coherent);
74 DECLARE_STATS_COUNTER(cross_page);
75 DECLARE_STATS_COUNTER(domain_flush_single);
76 DECLARE_STATS_COUNTER(domain_flush_all);
78 static struct dentry *stats_dir;
79 static struct dentry *de_isolate;
80 static struct dentry *de_fflush;
82 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
84 if (stats_dir == NULL)
87 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
91 static void amd_iommu_stats_init(void)
93 stats_dir = debugfs_create_dir("amd-iommu", NULL);
94 if (stats_dir == NULL)
97 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
98 (u32 *)&amd_iommu_isolate);
100 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
101 (u32 *)&amd_iommu_unmap_flush);
103 amd_iommu_stats_add(&compl_wait);
104 amd_iommu_stats_add(&cnt_map_single);
105 amd_iommu_stats_add(&cnt_unmap_single);
106 amd_iommu_stats_add(&cnt_map_sg);
107 amd_iommu_stats_add(&cnt_unmap_sg);
108 amd_iommu_stats_add(&cnt_alloc_coherent);
109 amd_iommu_stats_add(&cnt_free_coherent);
110 amd_iommu_stats_add(&cross_page);
111 amd_iommu_stats_add(&domain_flush_single);
112 amd_iommu_stats_add(&domain_flush_all);
117 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
118 static int iommu_has_npcache(struct amd_iommu *iommu)
120 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
123 /****************************************************************************
125 * Interrupt handling functions
127 ****************************************************************************/
129 static void iommu_print_event(void *__evt)
132 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
133 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
134 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
135 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
136 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
138 printk(KERN_ERR "AMD IOMMU: Event logged [");
141 case EVENT_TYPE_ILL_DEV:
142 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
143 "address=0x%016llx flags=0x%04x]\n",
144 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
147 case EVENT_TYPE_IO_FAULT:
148 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
149 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
150 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
151 domid, address, flags);
153 case EVENT_TYPE_DEV_TAB_ERR:
154 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
155 "address=0x%016llx flags=0x%04x]\n",
156 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
159 case EVENT_TYPE_PAGE_TAB_ERR:
160 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
161 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
162 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
163 domid, address, flags);
165 case EVENT_TYPE_ILL_CMD:
166 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
168 case EVENT_TYPE_CMD_HARD_ERR:
169 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
170 "flags=0x%04x]\n", address, flags);
172 case EVENT_TYPE_IOTLB_INV_TO:
173 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
174 "address=0x%016llx]\n",
175 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
178 case EVENT_TYPE_INV_DEV_REQ:
179 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
180 "address=0x%016llx flags=0x%04x]\n",
181 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
185 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
189 static void iommu_poll_events(struct amd_iommu *iommu)
194 spin_lock_irqsave(&iommu->lock, flags);
196 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
197 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
199 while (head != tail) {
200 iommu_print_event(iommu->evt_buf + head);
201 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
204 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
206 spin_unlock_irqrestore(&iommu->lock, flags);
209 irqreturn_t amd_iommu_int_handler(int irq, void *data)
211 struct amd_iommu *iommu;
213 list_for_each_entry(iommu, &amd_iommu_list, list)
214 iommu_poll_events(iommu);
219 /****************************************************************************
221 * IOMMU command queuing functions
223 ****************************************************************************/
226 * Writes the command to the IOMMUs command buffer and informs the
227 * hardware about the new command. Must be called with iommu->lock held.
229 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
234 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
235 target = iommu->cmd_buf + tail;
236 memcpy_toio(target, cmd, sizeof(*cmd));
237 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
238 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
241 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
247 * General queuing function for commands. Takes iommu->lock and calls
248 * __iommu_queue_command().
250 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
255 spin_lock_irqsave(&iommu->lock, flags);
256 ret = __iommu_queue_command(iommu, cmd);
258 iommu->need_sync = true;
259 spin_unlock_irqrestore(&iommu->lock, flags);
265 * This function waits until an IOMMU has completed a completion
268 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
274 INC_STATS_COUNTER(compl_wait);
276 while (!ready && (i < EXIT_LOOP_COUNT)) {
278 /* wait for the bit to become one */
279 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
280 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
283 /* set bit back to zero */
284 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
285 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
287 if (unlikely(i == EXIT_LOOP_COUNT))
288 panic("AMD IOMMU: Completion wait loop failed\n");
292 * This function queues a completion wait command into the command
295 static int __iommu_completion_wait(struct amd_iommu *iommu)
297 struct iommu_cmd cmd;
299 memset(&cmd, 0, sizeof(cmd));
300 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
301 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
303 return __iommu_queue_command(iommu, &cmd);
307 * This function is called whenever we need to ensure that the IOMMU has
308 * completed execution of all commands we sent. It sends a
309 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
310 * us about that by writing a value to a physical address we pass with
313 static int iommu_completion_wait(struct amd_iommu *iommu)
318 spin_lock_irqsave(&iommu->lock, flags);
320 if (!iommu->need_sync)
323 ret = __iommu_completion_wait(iommu);
325 iommu->need_sync = false;
330 __iommu_wait_for_completion(iommu);
333 spin_unlock_irqrestore(&iommu->lock, flags);
339 * Command send function for invalidating a device table entry
341 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
343 struct iommu_cmd cmd;
346 BUG_ON(iommu == NULL);
348 memset(&cmd, 0, sizeof(cmd));
349 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
352 ret = iommu_queue_command(iommu, &cmd);
357 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
358 u16 domid, int pde, int s)
360 memset(cmd, 0, sizeof(*cmd));
361 address &= PAGE_MASK;
362 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
363 cmd->data[1] |= domid;
364 cmd->data[2] = lower_32_bits(address);
365 cmd->data[3] = upper_32_bits(address);
366 if (s) /* size bit - we flush more than one 4kb page */
367 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
368 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
369 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
373 * Generic command send function for invalidaing TLB entries
375 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
376 u64 address, u16 domid, int pde, int s)
378 struct iommu_cmd cmd;
381 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
383 ret = iommu_queue_command(iommu, &cmd);
389 * TLB invalidation function which is called from the mapping functions.
390 * It invalidates a single PTE if the range to flush is within a single
391 * page. Otherwise it flushes the whole TLB of the IOMMU.
393 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
394 u64 address, size_t size)
397 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
399 address &= PAGE_MASK;
403 * If we have to flush more than one page, flush all
404 * TLB entries for this domain
406 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
410 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
415 /* Flush the whole IO/TLB for a given protection domain */
416 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
418 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
420 INC_STATS_COUNTER(domain_flush_single);
422 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
425 #ifdef CONFIG_IOMMU_API
427 * This function is used to flush the IO/TLB for a given protection domain
428 * on every IOMMU in the system
430 static void iommu_flush_domain(u16 domid)
433 struct amd_iommu *iommu;
434 struct iommu_cmd cmd;
436 INC_STATS_COUNTER(domain_flush_all);
438 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
441 list_for_each_entry(iommu, &amd_iommu_list, list) {
442 spin_lock_irqsave(&iommu->lock, flags);
443 __iommu_queue_command(iommu, &cmd);
444 __iommu_completion_wait(iommu);
445 __iommu_wait_for_completion(iommu);
446 spin_unlock_irqrestore(&iommu->lock, flags);
451 /****************************************************************************
453 * The functions below are used the create the page table mappings for
454 * unity mapped regions.
456 ****************************************************************************/
459 * Generic mapping functions. It maps a physical address into a DMA
460 * address space. It allocates the page table pages if necessary.
461 * In the future it can be extended to a generic mapping function
462 * supporting all features of AMD IOMMU page tables like level skipping
463 * and full 64 bit address spaces.
465 static int iommu_map_page(struct protection_domain *dom,
466 unsigned long bus_addr,
467 unsigned long phys_addr,
470 u64 __pte, *pte, *page;
472 bus_addr = PAGE_ALIGN(bus_addr);
473 phys_addr = PAGE_ALIGN(phys_addr);
475 /* only support 512GB address spaces for now */
476 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
479 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
481 if (!IOMMU_PTE_PRESENT(*pte)) {
482 page = (u64 *)get_zeroed_page(GFP_KERNEL);
485 *pte = IOMMU_L2_PDE(virt_to_phys(page));
488 pte = IOMMU_PTE_PAGE(*pte);
489 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
491 if (!IOMMU_PTE_PRESENT(*pte)) {
492 page = (u64 *)get_zeroed_page(GFP_KERNEL);
495 *pte = IOMMU_L1_PDE(virt_to_phys(page));
498 pte = IOMMU_PTE_PAGE(*pte);
499 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
501 if (IOMMU_PTE_PRESENT(*pte))
504 __pte = phys_addr | IOMMU_PTE_P;
505 if (prot & IOMMU_PROT_IR)
506 __pte |= IOMMU_PTE_IR;
507 if (prot & IOMMU_PROT_IW)
508 __pte |= IOMMU_PTE_IW;
515 #ifdef CONFIG_IOMMU_API
516 static void iommu_unmap_page(struct protection_domain *dom,
517 unsigned long bus_addr)
521 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
523 if (!IOMMU_PTE_PRESENT(*pte))
526 pte = IOMMU_PTE_PAGE(*pte);
527 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
529 if (!IOMMU_PTE_PRESENT(*pte))
532 pte = IOMMU_PTE_PAGE(*pte);
533 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
540 * This function checks if a specific unity mapping entry is needed for
541 * this specific IOMMU.
543 static int iommu_for_unity_map(struct amd_iommu *iommu,
544 struct unity_map_entry *entry)
548 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
549 bdf = amd_iommu_alias_table[i];
550 if (amd_iommu_rlookup_table[bdf] == iommu)
558 * Init the unity mappings for a specific IOMMU in the system
560 * Basically iterates over all unity mapping entries and applies them to
561 * the default domain DMA of that IOMMU if necessary.
563 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
565 struct unity_map_entry *entry;
568 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
569 if (!iommu_for_unity_map(iommu, entry))
571 ret = dma_ops_unity_map(iommu->default_dom, entry);
580 * This function actually applies the mapping to the page table of the
583 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
584 struct unity_map_entry *e)
589 for (addr = e->address_start; addr < e->address_end;
591 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
595 * if unity mapping is in aperture range mark the page
596 * as allocated in the aperture
598 if (addr < dma_dom->aperture_size)
599 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
606 * Inits the unity mappings required for a specific device
608 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
611 struct unity_map_entry *e;
614 list_for_each_entry(e, &amd_iommu_unity_map, list) {
615 if (!(devid >= e->devid_start && devid <= e->devid_end))
617 ret = dma_ops_unity_map(dma_dom, e);
625 /****************************************************************************
627 * The next functions belong to the address allocator for the dma_ops
628 * interface functions. They work like the allocators in the other IOMMU
629 * drivers. Its basically a bitmap which marks the allocated pages in
630 * the aperture. Maybe it could be enhanced in the future to a more
631 * efficient allocator.
633 ****************************************************************************/
636 * The address allocator core function.
638 * called with domain->lock held
640 static unsigned long dma_ops_alloc_addresses(struct device *dev,
641 struct dma_ops_domain *dom,
643 unsigned long align_mask,
647 unsigned long address;
648 unsigned long boundary_size;
650 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
651 PAGE_SIZE) >> PAGE_SHIFT;
652 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
653 dma_mask >> PAGE_SHIFT);
655 if (dom->next_bit >= limit) {
657 dom->need_flush = true;
660 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
661 0 , boundary_size, align_mask);
663 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
664 0, boundary_size, align_mask);
665 dom->need_flush = true;
668 if (likely(address != -1)) {
669 dom->next_bit = address + pages;
670 address <<= PAGE_SHIFT;
672 address = bad_dma_address;
674 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
680 * The address free function.
682 * called with domain->lock held
684 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
685 unsigned long address,
688 address >>= PAGE_SHIFT;
689 iommu_area_free(dom->bitmap, address, pages);
691 if (address >= dom->next_bit)
692 dom->need_flush = true;
695 /****************************************************************************
697 * The next functions belong to the domain allocation. A domain is
698 * allocated for every IOMMU as the default domain. If device isolation
699 * is enabled, every device get its own domain. The most important thing
700 * about domains is the page table mapping the DMA address space they
703 ****************************************************************************/
705 static u16 domain_id_alloc(void)
710 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
711 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
713 if (id > 0 && id < MAX_DOMAIN_ID)
714 __set_bit(id, amd_iommu_pd_alloc_bitmap);
717 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
722 #ifdef CONFIG_IOMMU_API
723 static void domain_id_free(int id)
727 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
728 if (id > 0 && id < MAX_DOMAIN_ID)
729 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
730 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
735 * Used to reserve address ranges in the aperture (e.g. for exclusion
738 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
739 unsigned long start_page,
742 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
744 if (start_page + pages > last_page)
745 pages = last_page - start_page;
747 iommu_area_reserve(dom->bitmap, start_page, pages);
750 static void free_pagetable(struct protection_domain *domain)
755 p1 = domain->pt_root;
760 for (i = 0; i < 512; ++i) {
761 if (!IOMMU_PTE_PRESENT(p1[i]))
764 p2 = IOMMU_PTE_PAGE(p1[i]);
765 for (j = 0; j < 512; ++j) {
766 if (!IOMMU_PTE_PRESENT(p2[j]))
768 p3 = IOMMU_PTE_PAGE(p2[j]);
769 free_page((unsigned long)p3);
772 free_page((unsigned long)p2);
775 free_page((unsigned long)p1);
777 domain->pt_root = NULL;
781 * Free a domain, only used if something went wrong in the
782 * allocation path and we need to free an already allocated page table
784 static void dma_ops_domain_free(struct dma_ops_domain *dom)
789 free_pagetable(&dom->domain);
791 kfree(dom->pte_pages);
799 * Allocates a new protection domain usable for the dma_ops functions.
800 * It also intializes the page table and the address allocator data
801 * structures required for the dma_ops interface
803 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
806 struct dma_ops_domain *dma_dom;
807 unsigned i, num_pte_pages;
812 * Currently the DMA aperture must be between 32 MB and 1GB in size
814 if ((order < 25) || (order > 30))
817 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
821 spin_lock_init(&dma_dom->domain.lock);
823 dma_dom->domain.id = domain_id_alloc();
824 if (dma_dom->domain.id == 0)
826 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
827 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
828 dma_dom->domain.flags = PD_DMA_OPS_MASK;
829 dma_dom->domain.priv = dma_dom;
830 if (!dma_dom->domain.pt_root)
832 dma_dom->aperture_size = (1ULL << order);
833 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
835 if (!dma_dom->bitmap)
838 * mark the first page as allocated so we never return 0 as
839 * a valid dma-address. So we can use 0 as error value
841 dma_dom->bitmap[0] = 1;
842 dma_dom->next_bit = 0;
844 dma_dom->need_flush = false;
845 dma_dom->target_dev = 0xffff;
847 /* Intialize the exclusion range if necessary */
848 if (iommu->exclusion_start &&
849 iommu->exclusion_start < dma_dom->aperture_size) {
850 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
851 int pages = iommu_num_pages(iommu->exclusion_start,
852 iommu->exclusion_length,
854 dma_ops_reserve_addresses(dma_dom, startpage, pages);
858 * At the last step, build the page tables so we don't need to
859 * allocate page table pages in the dma_ops mapping/unmapping
862 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
863 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
865 if (!dma_dom->pte_pages)
868 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
872 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
874 for (i = 0; i < num_pte_pages; ++i) {
875 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
876 if (!dma_dom->pte_pages[i])
878 address = virt_to_phys(dma_dom->pte_pages[i]);
879 l2_pde[i] = IOMMU_L1_PDE(address);
885 dma_ops_domain_free(dma_dom);
891 * little helper function to check whether a given protection domain is a
894 static bool dma_ops_domain(struct protection_domain *domain)
896 return domain->flags & PD_DMA_OPS_MASK;
900 * Find out the protection domain structure for a given PCI device. This
901 * will give us the pointer to the page table root for example.
903 static struct protection_domain *domain_for_device(u16 devid)
905 struct protection_domain *dom;
908 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
909 dom = amd_iommu_pd_table[devid];
910 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
916 * If a device is not yet associated with a domain, this function does
917 * assigns it visible for the hardware
919 static void attach_device(struct amd_iommu *iommu,
920 struct protection_domain *domain,
924 u64 pte_root = virt_to_phys(domain->pt_root);
926 domain->dev_cnt += 1;
928 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
929 << DEV_ENTRY_MODE_SHIFT;
930 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
932 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
933 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
934 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
935 amd_iommu_dev_table[devid].data[2] = domain->id;
937 amd_iommu_pd_table[devid] = domain;
938 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
940 iommu_queue_inv_dev_entry(iommu, devid);
944 * Removes a device from a protection domain (unlocked)
946 static void __detach_device(struct protection_domain *domain, u16 devid)
950 spin_lock(&domain->lock);
952 /* remove domain from the lookup table */
953 amd_iommu_pd_table[devid] = NULL;
955 /* remove entry from the device table seen by the hardware */
956 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
957 amd_iommu_dev_table[devid].data[1] = 0;
958 amd_iommu_dev_table[devid].data[2] = 0;
960 /* decrease reference counter */
961 domain->dev_cnt -= 1;
964 spin_unlock(&domain->lock);
968 * Removes a device from a protection domain (with devtable_lock held)
970 static void detach_device(struct protection_domain *domain, u16 devid)
974 /* lock device table */
975 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
976 __detach_device(domain, devid);
977 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
980 static int device_change_notifier(struct notifier_block *nb,
981 unsigned long action, void *data)
983 struct device *dev = data;
984 struct pci_dev *pdev = to_pci_dev(dev);
985 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
986 struct protection_domain *domain;
987 struct dma_ops_domain *dma_domain;
988 struct amd_iommu *iommu;
989 int order = amd_iommu_aperture_order;
992 if (devid > amd_iommu_last_bdf)
995 devid = amd_iommu_alias_table[devid];
997 iommu = amd_iommu_rlookup_table[devid];
1001 domain = domain_for_device(devid);
1003 if (domain && !dma_ops_domain(domain))
1004 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1005 "to a non-dma-ops domain\n", dev_name(dev));
1008 case BUS_NOTIFY_BOUND_DRIVER:
1011 dma_domain = find_protection_domain(devid);
1013 dma_domain = iommu->default_dom;
1014 attach_device(iommu, &dma_domain->domain, devid);
1015 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1016 "device %s\n", dma_domain->domain.id, dev_name(dev));
1018 case BUS_NOTIFY_UNBIND_DRIVER:
1021 detach_device(domain, devid);
1023 case BUS_NOTIFY_ADD_DEVICE:
1024 /* allocate a protection domain if a device is added */
1025 dma_domain = find_protection_domain(devid);
1028 dma_domain = dma_ops_domain_alloc(iommu, order);
1031 dma_domain->target_dev = devid;
1033 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1034 list_add_tail(&dma_domain->list, &iommu_pd_list);
1035 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1042 iommu_queue_inv_dev_entry(iommu, devid);
1043 iommu_completion_wait(iommu);
1049 struct notifier_block device_nb = {
1050 .notifier_call = device_change_notifier,
1053 /*****************************************************************************
1055 * The next functions belong to the dma_ops mapping/unmapping code.
1057 *****************************************************************************/
1060 * This function checks if the driver got a valid device from the caller to
1061 * avoid dereferencing invalid pointers.
1063 static bool check_device(struct device *dev)
1065 if (!dev || !dev->dma_mask)
1072 * In this function the list of preallocated protection domains is traversed to
1073 * find the domain for a specific device
1075 static struct dma_ops_domain *find_protection_domain(u16 devid)
1077 struct dma_ops_domain *entry, *ret = NULL;
1078 unsigned long flags;
1080 if (list_empty(&iommu_pd_list))
1083 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1085 list_for_each_entry(entry, &iommu_pd_list, list) {
1086 if (entry->target_dev == devid) {
1092 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1098 * In the dma_ops path we only have the struct device. This function
1099 * finds the corresponding IOMMU, the protection domain and the
1100 * requestor id for a given device.
1101 * If the device is not yet associated with a domain this is also done
1104 static int get_device_resources(struct device *dev,
1105 struct amd_iommu **iommu,
1106 struct protection_domain **domain,
1109 struct dma_ops_domain *dma_dom;
1110 struct pci_dev *pcidev;
1117 if (dev->bus != &pci_bus_type)
1120 pcidev = to_pci_dev(dev);
1121 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1123 /* device not translated by any IOMMU in the system? */
1124 if (_bdf > amd_iommu_last_bdf)
1127 *bdf = amd_iommu_alias_table[_bdf];
1129 *iommu = amd_iommu_rlookup_table[*bdf];
1132 *domain = domain_for_device(*bdf);
1133 if (*domain == NULL) {
1134 dma_dom = find_protection_domain(*bdf);
1136 dma_dom = (*iommu)->default_dom;
1137 *domain = &dma_dom->domain;
1138 attach_device(*iommu, *domain, *bdf);
1139 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1140 "device %s\n", (*domain)->id, dev_name(dev));
1143 if (domain_for_device(_bdf) == NULL)
1144 attach_device(*iommu, *domain, _bdf);
1150 * This is the generic map function. It maps one 4kb page at paddr to
1151 * the given address in the DMA address space for the domain.
1153 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1154 struct dma_ops_domain *dom,
1155 unsigned long address,
1161 WARN_ON(address > dom->aperture_size);
1165 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1166 pte += IOMMU_PTE_L0_INDEX(address);
1168 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1170 if (direction == DMA_TO_DEVICE)
1171 __pte |= IOMMU_PTE_IR;
1172 else if (direction == DMA_FROM_DEVICE)
1173 __pte |= IOMMU_PTE_IW;
1174 else if (direction == DMA_BIDIRECTIONAL)
1175 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1181 return (dma_addr_t)address;
1185 * The generic unmapping function for on page in the DMA address space.
1187 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1188 struct dma_ops_domain *dom,
1189 unsigned long address)
1193 if (address >= dom->aperture_size)
1196 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1198 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1199 pte += IOMMU_PTE_L0_INDEX(address);
1207 * This function contains common code for mapping of a physically
1208 * contiguous memory region into DMA address space. It is used by all
1209 * mapping functions provided with this IOMMU driver.
1210 * Must be called with the domain lock held.
1212 static dma_addr_t __map_single(struct device *dev,
1213 struct amd_iommu *iommu,
1214 struct dma_ops_domain *dma_dom,
1221 dma_addr_t offset = paddr & ~PAGE_MASK;
1222 dma_addr_t address, start;
1224 unsigned long align_mask = 0;
1227 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1231 INC_STATS_COUNTER(cross_page);
1234 align_mask = (1UL << get_order(size)) - 1;
1236 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1238 if (unlikely(address == bad_dma_address))
1242 for (i = 0; i < pages; ++i) {
1243 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1249 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1250 iommu_flush_tlb(iommu, dma_dom->domain.id);
1251 dma_dom->need_flush = false;
1252 } else if (unlikely(iommu_has_npcache(iommu)))
1253 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1260 * Does the reverse of the __map_single function. Must be called with
1261 * the domain lock held too
1263 static void __unmap_single(struct amd_iommu *iommu,
1264 struct dma_ops_domain *dma_dom,
1265 dma_addr_t dma_addr,
1269 dma_addr_t i, start;
1272 if ((dma_addr == bad_dma_address) ||
1273 (dma_addr + size > dma_dom->aperture_size))
1276 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1277 dma_addr &= PAGE_MASK;
1280 for (i = 0; i < pages; ++i) {
1281 dma_ops_domain_unmap(iommu, dma_dom, start);
1285 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1287 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1288 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1289 dma_dom->need_flush = false;
1294 * The exported map_single function for dma_ops.
1296 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1297 size_t size, int dir)
1299 unsigned long flags;
1300 struct amd_iommu *iommu;
1301 struct protection_domain *domain;
1306 INC_STATS_COUNTER(cnt_map_single);
1308 if (!check_device(dev))
1309 return bad_dma_address;
1311 dma_mask = *dev->dma_mask;
1313 get_device_resources(dev, &iommu, &domain, &devid);
1315 if (iommu == NULL || domain == NULL)
1316 /* device not handled by any AMD IOMMU */
1317 return (dma_addr_t)paddr;
1319 if (!dma_ops_domain(domain))
1320 return bad_dma_address;
1322 spin_lock_irqsave(&domain->lock, flags);
1323 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1325 if (addr == bad_dma_address)
1328 iommu_completion_wait(iommu);
1331 spin_unlock_irqrestore(&domain->lock, flags);
1337 * The exported unmap_single function for dma_ops.
1339 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1340 size_t size, int dir)
1342 unsigned long flags;
1343 struct amd_iommu *iommu;
1344 struct protection_domain *domain;
1347 INC_STATS_COUNTER(cnt_unmap_single);
1349 if (!check_device(dev) ||
1350 !get_device_resources(dev, &iommu, &domain, &devid))
1351 /* device not handled by any AMD IOMMU */
1354 if (!dma_ops_domain(domain))
1357 spin_lock_irqsave(&domain->lock, flags);
1359 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1361 iommu_completion_wait(iommu);
1363 spin_unlock_irqrestore(&domain->lock, flags);
1367 * This is a special map_sg function which is used if we should map a
1368 * device which is not handled by an AMD IOMMU in the system.
1370 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1371 int nelems, int dir)
1373 struct scatterlist *s;
1376 for_each_sg(sglist, s, nelems, i) {
1377 s->dma_address = (dma_addr_t)sg_phys(s);
1378 s->dma_length = s->length;
1385 * The exported map_sg function for dma_ops (handles scatter-gather
1388 static int map_sg(struct device *dev, struct scatterlist *sglist,
1389 int nelems, int dir)
1391 unsigned long flags;
1392 struct amd_iommu *iommu;
1393 struct protection_domain *domain;
1396 struct scatterlist *s;
1398 int mapped_elems = 0;
1401 INC_STATS_COUNTER(cnt_map_sg);
1403 if (!check_device(dev))
1406 dma_mask = *dev->dma_mask;
1408 get_device_resources(dev, &iommu, &domain, &devid);
1410 if (!iommu || !domain)
1411 return map_sg_no_iommu(dev, sglist, nelems, dir);
1413 if (!dma_ops_domain(domain))
1416 spin_lock_irqsave(&domain->lock, flags);
1418 for_each_sg(sglist, s, nelems, i) {
1421 s->dma_address = __map_single(dev, iommu, domain->priv,
1422 paddr, s->length, dir, false,
1425 if (s->dma_address) {
1426 s->dma_length = s->length;
1432 iommu_completion_wait(iommu);
1435 spin_unlock_irqrestore(&domain->lock, flags);
1437 return mapped_elems;
1439 for_each_sg(sglist, s, mapped_elems, i) {
1441 __unmap_single(iommu, domain->priv, s->dma_address,
1442 s->dma_length, dir);
1443 s->dma_address = s->dma_length = 0;
1452 * The exported map_sg function for dma_ops (handles scatter-gather
1455 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1456 int nelems, int dir)
1458 unsigned long flags;
1459 struct amd_iommu *iommu;
1460 struct protection_domain *domain;
1461 struct scatterlist *s;
1465 INC_STATS_COUNTER(cnt_unmap_sg);
1467 if (!check_device(dev) ||
1468 !get_device_resources(dev, &iommu, &domain, &devid))
1471 if (!dma_ops_domain(domain))
1474 spin_lock_irqsave(&domain->lock, flags);
1476 for_each_sg(sglist, s, nelems, i) {
1477 __unmap_single(iommu, domain->priv, s->dma_address,
1478 s->dma_length, dir);
1479 s->dma_address = s->dma_length = 0;
1482 iommu_completion_wait(iommu);
1484 spin_unlock_irqrestore(&domain->lock, flags);
1488 * The exported alloc_coherent function for dma_ops.
1490 static void *alloc_coherent(struct device *dev, size_t size,
1491 dma_addr_t *dma_addr, gfp_t flag)
1493 unsigned long flags;
1495 struct amd_iommu *iommu;
1496 struct protection_domain *domain;
1499 u64 dma_mask = dev->coherent_dma_mask;
1501 INC_STATS_COUNTER(cnt_alloc_coherent);
1503 if (!check_device(dev))
1506 if (!get_device_resources(dev, &iommu, &domain, &devid))
1507 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1510 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1514 paddr = virt_to_phys(virt_addr);
1516 if (!iommu || !domain) {
1517 *dma_addr = (dma_addr_t)paddr;
1521 if (!dma_ops_domain(domain))
1525 dma_mask = *dev->dma_mask;
1527 spin_lock_irqsave(&domain->lock, flags);
1529 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1530 size, DMA_BIDIRECTIONAL, true, dma_mask);
1532 if (*dma_addr == bad_dma_address)
1535 iommu_completion_wait(iommu);
1537 spin_unlock_irqrestore(&domain->lock, flags);
1543 free_pages((unsigned long)virt_addr, get_order(size));
1549 * The exported free_coherent function for dma_ops.
1551 static void free_coherent(struct device *dev, size_t size,
1552 void *virt_addr, dma_addr_t dma_addr)
1554 unsigned long flags;
1555 struct amd_iommu *iommu;
1556 struct protection_domain *domain;
1559 INC_STATS_COUNTER(cnt_free_coherent);
1561 if (!check_device(dev))
1564 get_device_resources(dev, &iommu, &domain, &devid);
1566 if (!iommu || !domain)
1569 if (!dma_ops_domain(domain))
1572 spin_lock_irqsave(&domain->lock, flags);
1574 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1576 iommu_completion_wait(iommu);
1578 spin_unlock_irqrestore(&domain->lock, flags);
1581 free_pages((unsigned long)virt_addr, get_order(size));
1585 * This function is called by the DMA layer to find out if we can handle a
1586 * particular device. It is part of the dma_ops.
1588 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1591 struct pci_dev *pcidev;
1593 /* No device or no PCI device */
1594 if (!dev || dev->bus != &pci_bus_type)
1597 pcidev = to_pci_dev(dev);
1599 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1601 /* Out of our scope? */
1602 if (bdf > amd_iommu_last_bdf)
1609 * The function for pre-allocating protection domains.
1611 * If the driver core informs the DMA layer if a driver grabs a device
1612 * we don't need to preallocate the protection domains anymore.
1613 * For now we have to.
1615 void prealloc_protection_domains(void)
1617 struct pci_dev *dev = NULL;
1618 struct dma_ops_domain *dma_dom;
1619 struct amd_iommu *iommu;
1620 int order = amd_iommu_aperture_order;
1623 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1624 devid = calc_devid(dev->bus->number, dev->devfn);
1625 if (devid > amd_iommu_last_bdf)
1627 devid = amd_iommu_alias_table[devid];
1628 if (domain_for_device(devid))
1630 iommu = amd_iommu_rlookup_table[devid];
1633 dma_dom = dma_ops_domain_alloc(iommu, order);
1636 init_unity_mappings_for_device(dma_dom, devid);
1637 dma_dom->target_dev = devid;
1639 list_add_tail(&dma_dom->list, &iommu_pd_list);
1643 static struct dma_mapping_ops amd_iommu_dma_ops = {
1644 .alloc_coherent = alloc_coherent,
1645 .free_coherent = free_coherent,
1646 .map_single = map_single,
1647 .unmap_single = unmap_single,
1649 .unmap_sg = unmap_sg,
1650 .dma_supported = amd_iommu_dma_supported,
1654 * The function which clues the AMD IOMMU driver into dma_ops.
1656 int __init amd_iommu_init_dma_ops(void)
1658 struct amd_iommu *iommu;
1659 int order = amd_iommu_aperture_order;
1663 * first allocate a default protection domain for every IOMMU we
1664 * found in the system. Devices not assigned to any other
1665 * protection domain will be assigned to the default one.
1667 list_for_each_entry(iommu, &amd_iommu_list, list) {
1668 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1669 if (iommu->default_dom == NULL)
1671 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1672 ret = iommu_init_unity_mappings(iommu);
1678 * If device isolation is enabled, pre-allocate the protection
1679 * domains for each device.
1681 if (amd_iommu_isolate)
1682 prealloc_protection_domains();
1686 bad_dma_address = 0;
1687 #ifdef CONFIG_GART_IOMMU
1688 gart_iommu_aperture_disabled = 1;
1689 gart_iommu_aperture = 0;
1692 /* Make the driver finally visible to the drivers */
1693 dma_ops = &amd_iommu_dma_ops;
1695 #ifdef CONFIG_IOMMU_API
1696 register_iommu(&amd_iommu_ops);
1699 bus_register_notifier(&pci_bus_type, &device_nb);
1701 amd_iommu_stats_init();
1707 list_for_each_entry(iommu, &amd_iommu_list, list) {
1708 if (iommu->default_dom)
1709 dma_ops_domain_free(iommu->default_dom);
1715 /*****************************************************************************
1717 * The following functions belong to the exported interface of AMD IOMMU
1719 * This interface allows access to lower level functions of the IOMMU
1720 * like protection domain handling and assignement of devices to domains
1721 * which is not possible with the dma_ops interface.
1723 *****************************************************************************/
1725 #ifdef CONFIG_IOMMU_API
1727 static void cleanup_domain(struct protection_domain *domain)
1729 unsigned long flags;
1732 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1734 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1735 if (amd_iommu_pd_table[devid] == domain)
1736 __detach_device(domain, devid);
1738 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1741 static int amd_iommu_domain_init(struct iommu_domain *dom)
1743 struct protection_domain *domain;
1745 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1749 spin_lock_init(&domain->lock);
1750 domain->mode = PAGE_MODE_3_LEVEL;
1751 domain->id = domain_id_alloc();
1754 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1755 if (!domain->pt_root)
1768 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1770 struct protection_domain *domain = dom->priv;
1775 if (domain->dev_cnt > 0)
1776 cleanup_domain(domain);
1778 BUG_ON(domain->dev_cnt != 0);
1780 free_pagetable(domain);
1782 domain_id_free(domain->id);
1789 static void amd_iommu_detach_device(struct iommu_domain *dom,
1792 struct protection_domain *domain = dom->priv;
1793 struct amd_iommu *iommu;
1794 struct pci_dev *pdev;
1797 if (dev->bus != &pci_bus_type)
1800 pdev = to_pci_dev(dev);
1802 devid = calc_devid(pdev->bus->number, pdev->devfn);
1805 detach_device(domain, devid);
1807 iommu = amd_iommu_rlookup_table[devid];
1811 iommu_queue_inv_dev_entry(iommu, devid);
1812 iommu_completion_wait(iommu);
1815 static int amd_iommu_attach_device(struct iommu_domain *dom,
1818 struct protection_domain *domain = dom->priv;
1819 struct protection_domain *old_domain;
1820 struct amd_iommu *iommu;
1821 struct pci_dev *pdev;
1824 if (dev->bus != &pci_bus_type)
1827 pdev = to_pci_dev(dev);
1829 devid = calc_devid(pdev->bus->number, pdev->devfn);
1831 if (devid >= amd_iommu_last_bdf ||
1832 devid != amd_iommu_alias_table[devid])
1835 iommu = amd_iommu_rlookup_table[devid];
1839 old_domain = domain_for_device(devid);
1843 attach_device(iommu, domain, devid);
1845 iommu_completion_wait(iommu);
1850 static int amd_iommu_map_range(struct iommu_domain *dom,
1851 unsigned long iova, phys_addr_t paddr,
1852 size_t size, int iommu_prot)
1854 struct protection_domain *domain = dom->priv;
1855 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1859 if (iommu_prot & IOMMU_READ)
1860 prot |= IOMMU_PROT_IR;
1861 if (iommu_prot & IOMMU_WRITE)
1862 prot |= IOMMU_PROT_IW;
1867 for (i = 0; i < npages; ++i) {
1868 ret = iommu_map_page(domain, iova, paddr, prot);
1879 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1880 unsigned long iova, size_t size)
1883 struct protection_domain *domain = dom->priv;
1884 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1888 for (i = 0; i < npages; ++i) {
1889 iommu_unmap_page(domain, iova);
1893 iommu_flush_domain(domain->id);
1896 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1899 struct protection_domain *domain = dom->priv;
1900 unsigned long offset = iova & ~PAGE_MASK;
1904 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1906 if (!IOMMU_PTE_PRESENT(*pte))
1909 pte = IOMMU_PTE_PAGE(*pte);
1910 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1912 if (!IOMMU_PTE_PRESENT(*pte))
1915 pte = IOMMU_PTE_PAGE(*pte);
1916 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1918 if (!IOMMU_PTE_PRESENT(*pte))
1921 paddr = *pte & IOMMU_PAGE_MASK;
1927 static struct iommu_ops amd_iommu_ops = {
1928 .domain_init = amd_iommu_domain_init,
1929 .domain_destroy = amd_iommu_domain_destroy,
1930 .attach_dev = amd_iommu_attach_device,
1931 .detach_dev = amd_iommu_detach_device,
1932 .map = amd_iommu_map_range,
1933 .unmap = amd_iommu_unmap_range,
1934 .iova_to_phys = amd_iommu_iova_to_phys,