1 #ifndef _ASM_X86_TLBFLUSH_H
2 #define _ASM_X86_TLBFLUSH_H
5 #include <linux/sched.h>
7 #include <asm/processor.h>
8 #include <asm/system.h>
11 static inline void __invpcid(unsigned long pcid, unsigned long addr,
14 struct { u64 d[2]; } desc = { { pcid, addr } };
17 * The memory clobber is because the whole point is to invalidate
18 * stale TLB entries and, especially if we're flushing global
19 * mappings, we don't want the compiler to reorder any subsequent
20 * memory accesses before the TLB flush.
22 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
23 * invpcid (%rcx), %rax in long mode.
25 asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
26 : : "m" (desc), "a" (type), "c" (&desc) : "memory");
29 #define INVPCID_TYPE_INDIV_ADDR 0
30 #define INVPCID_TYPE_SINGLE_CTXT 1
31 #define INVPCID_TYPE_ALL_INCL_GLOBAL 2
32 #define INVPCID_TYPE_ALL_NON_GLOBAL 3
34 /* Flush all mappings for a given pcid and addr, not including globals. */
35 static inline void invpcid_flush_one(unsigned long pcid,
38 __invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
41 /* Flush all mappings for a given PCID, not including globals. */
42 static inline void invpcid_flush_single_context(unsigned long pcid)
44 __invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
47 /* Flush all mappings, including globals, for all PCIDs. */
48 static inline void invpcid_flush_all(void)
50 __invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
53 /* Flush all mappings for all PCIDs except globals. */
54 static inline void invpcid_flush_all_nonglobals(void)
56 __invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
59 #ifdef CONFIG_PARAVIRT
60 #include <asm/paravirt.h>
62 #define __flush_tlb() __native_flush_tlb()
63 #define __flush_tlb_global() __native_flush_tlb_global()
64 #define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
68 * Declare a couple of kaiser interfaces here for convenience,
69 * to avoid the need for asm/kaiser.h in unexpected places.
72 extern int kaiser_enabled;
73 extern void kaiser_setup_pcid(void);
74 extern void kaiser_flush_tlb_on_return_to_user(void);
76 #define kaiser_enabled 0
77 static inline void kaiser_setup_pcid(void)
80 static inline void kaiser_flush_tlb_on_return_to_user(void)
85 static inline void __native_flush_tlb(void)
88 * If current->mm == NULL then we borrow a mm which may change during a
89 * task switch and therefore we must not be preempted while we write CR3
94 kaiser_flush_tlb_on_return_to_user();
95 native_write_cr3(native_read_cr3());
99 static inline void __native_flush_tlb_global(void)
104 if (this_cpu_has(X86_FEATURE_INVPCID)) {
106 * Using INVPCID is considerably faster than a pair of writes
107 * to CR4 sandwiched inside an IRQ flag save/restore.
109 * Note, this works with CR4.PCIDE=0 or 1.
116 * Read-modify-write to CR4 - protect it from preemption and
117 * from interrupts. (Use the raw variant because this code can
118 * be called from deep inside debugging code.)
120 raw_local_irq_save(flags);
122 cr4 = native_read_cr4();
123 if (cr4 & X86_CR4_PGE) {
124 /* clear PGE and flush TLB of all entries */
125 native_write_cr4(cr4 & ~X86_CR4_PGE);
126 /* restore PGE as it was before */
127 native_write_cr4(cr4);
129 /* do it with cr3, letting kaiser flush user PCID */
130 __native_flush_tlb();
133 raw_local_irq_restore(flags);
136 static inline void __native_flush_tlb_single(unsigned long addr)
139 * SIMICS #GP's if you run INVPCID with type 2/3
140 * and X86_CR4_PCIDE clear. Shame!
142 * The ASIDs used below are hard-coded. But, we must not
143 * call invpcid(type=1/2) before CR4.PCIDE=1. Just call
144 * invlpg in the case we are called early.
147 if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE)) {
149 kaiser_flush_tlb_on_return_to_user();
150 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
153 /* Flush the address out of both PCIDs. */
155 * An optimization here might be to determine addresses
156 * that are only kernel-mapped and only flush the kernel
157 * ASID. But, userspace flushes are probably much more
158 * important performance-wise.
160 * Make sure to do only a single invpcid when KAISER is
161 * disabled and we have only a single ASID.
164 invpcid_flush_one(X86_CR3_PCID_ASID_USER, addr);
165 invpcid_flush_one(X86_CR3_PCID_ASID_KERN, addr);
168 static inline void __flush_tlb_all(void)
170 __flush_tlb_global();
172 * Note: if we somehow had PCID but not PGE, then this wouldn't work --
173 * we'd end up flushing kernel translations for the current ASID but
174 * we might fail to flush kernel translations for other cached ASIDs.
176 * To avoid this issue, we force PCID off if PGE is off.
180 static inline void __flush_tlb_one(unsigned long addr)
183 __flush_tlb_single(addr);
189 # define TLB_FLUSH_ALL 0xffffffff
191 # define TLB_FLUSH_ALL -1ULL
197 * - flush_tlb() flushes the current mm struct TLBs
198 * - flush_tlb_all() flushes all processes TLBs
199 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
200 * - flush_tlb_page(vma, vmaddr) flushes one page
201 * - flush_tlb_range(vma, start, end) flushes a range of pages
202 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
203 * - flush_tlb_others(cpumask, mm, va) flushes TLBs on other cpus
205 * ..but the i386 has somewhat limited tlb flushing capabilities,
206 * and page-granular flushes are available only on i486 and up.
209 #define local_flush_tlb() __flush_tlb()
211 extern void flush_tlb_all(void);
212 extern void flush_tlb_current_task(void);
213 extern void flush_tlb_mm(struct mm_struct *);
214 extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
216 #define flush_tlb() flush_tlb_current_task()
218 static inline void flush_tlb_range(struct vm_area_struct *vma,
219 unsigned long start, unsigned long end)
221 flush_tlb_mm(vma->vm_mm);
224 void native_flush_tlb_others(const struct cpumask *cpumask,
225 struct mm_struct *mm, unsigned long va);
227 #define TLBSTATE_OK 1
228 #define TLBSTATE_LAZY 2
231 struct mm_struct *active_mm;
234 DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
236 static inline void reset_lazy_tlbstate(void)
238 percpu_write(cpu_tlbstate.state, 0);
239 percpu_write(cpu_tlbstate.active_mm, &init_mm);
242 #ifndef CONFIG_PARAVIRT
243 #define flush_tlb_others(mask, mm, va) native_flush_tlb_others(mask, mm, va)
246 static inline void flush_tlb_kernel_range(unsigned long start,
252 #endif /* _ASM_X86_TLBFLUSH_H */