1 /* $Id: pci_iommu.c,v 1.17 2001/12/17 07:05:09 davem Exp $
2 * pci_iommu.c: UltraSparc PCI controller IOM/STC support.
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
8 #include <linux/kernel.h>
9 #include <linux/sched.h>
11 #include <linux/delay.h>
15 #include "iommu_common.h"
17 #define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
18 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
20 /* Accessing IOMMU and Streaming Buffer registers.
21 * REG parameter is a physical address. All registers
22 * are 64-bits in size.
24 #define pci_iommu_read(__reg) \
26 __asm__ __volatile__("ldxa [%1] %2, %0" \
28 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
32 #define pci_iommu_write(__reg, __val) \
33 __asm__ __volatile__("stxa %0, [%1] %2" \
35 : "r" (__val), "r" (__reg), \
36 "i" (ASI_PHYS_BYPASS_EC_E))
38 /* Must be invoked under the IOMMU lock. */
39 static void __iommu_flushall(struct pci_iommu *iommu)
44 tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
45 for (entry = 0; entry < 16; entry++) {
46 pci_iommu_write(tag, 0);
50 /* Ensure completion of previous PIO writes. */
51 (void) pci_iommu_read(iommu->write_complete_reg);
54 #define IOPTE_CONSISTENT(CTX) \
55 (IOPTE_VALID | IOPTE_CACHE | \
56 (((CTX) << 47) & IOPTE_CONTEXT))
58 #define IOPTE_STREAMING(CTX) \
59 (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
61 /* Existing mappings are never marked invalid, instead they
62 * are pointed to a dummy page.
64 #define IOPTE_IS_DUMMY(iommu, iopte) \
65 ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
67 static inline void iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
69 unsigned long val = iopte_val(*iopte);
72 val |= iommu->dummy_page_pa;
74 iopte_val(*iopte) = val;
77 /* Based largely upon the ppc64 iommu allocator. */
78 static long pci_arena_alloc(struct pci_iommu *iommu, unsigned long npages)
80 struct pci_iommu_arena *arena = &iommu->arena;
81 unsigned long n, i, start, end, limit;
89 n = find_next_zero_bit(arena->map, limit, start);
91 if (unlikely(end >= limit)) {
92 if (likely(pass < 1)) {
95 __iommu_flushall(iommu);
99 /* Scanned the whole thing, give up. */
104 for (i = n; i < end; i++) {
105 if (test_bit(i, arena->map)) {
111 for (i = n; i < end; i++)
112 __set_bit(i, arena->map);
119 static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages)
123 for (i = base; i < (base + npages); i++)
124 __clear_bit(i, arena->map);
127 void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask)
129 unsigned long i, tsbbase, order, sz, num_tsb_entries;
131 num_tsb_entries = tsbsize / sizeof(iopte_t);
133 /* Setup initial software IOMMU state. */
134 spin_lock_init(&iommu->lock);
135 iommu->ctx_lowest_free = 1;
136 iommu->page_table_map_base = dma_offset;
137 iommu->dma_addr_mask = dma_addr_mask;
139 /* Allocate and initialize the free area map. */
140 sz = num_tsb_entries / 8;
141 sz = (sz + 7UL) & ~7UL;
142 iommu->arena.map = kzalloc(sz, GFP_KERNEL);
143 if (!iommu->arena.map) {
144 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
147 iommu->arena.limit = num_tsb_entries;
149 /* Allocate and initialize the dummy page which we
150 * set inactive IO PTEs to point to.
152 iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
153 if (!iommu->dummy_page) {
154 prom_printf("PCI_IOMMU: Error, gfp(dummy_page) failed.\n");
157 memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
158 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
160 /* Now allocate and setup the IOMMU page table itself. */
161 order = get_order(tsbsize);
162 tsbbase = __get_free_pages(GFP_KERNEL, order);
164 prom_printf("PCI_IOMMU: Error, gfp(tsb) failed.\n");
167 iommu->page_table = (iopte_t *)tsbbase;
169 for (i = 0; i < num_tsb_entries; i++)
170 iopte_make_dummy(iommu, &iommu->page_table[i]);
173 static inline iopte_t *alloc_npages(struct pci_iommu *iommu, unsigned long npages)
177 entry = pci_arena_alloc(iommu, npages);
178 if (unlikely(entry < 0))
181 return iommu->page_table + entry;
184 static inline void free_npages(struct pci_iommu *iommu, dma_addr_t base, unsigned long npages)
186 pci_arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
189 static int iommu_alloc_ctx(struct pci_iommu *iommu)
191 int lowest = iommu->ctx_lowest_free;
192 int sz = IOMMU_NUM_CTXS - lowest;
193 int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
195 if (unlikely(n == sz)) {
196 n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
197 if (unlikely(n == lowest)) {
198 printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
203 __set_bit(n, iommu->ctx_bitmap);
208 static inline void iommu_free_ctx(struct pci_iommu *iommu, int ctx)
211 __clear_bit(ctx, iommu->ctx_bitmap);
212 if (ctx < iommu->ctx_lowest_free)
213 iommu->ctx_lowest_free = ctx;
217 /* Allocate and map kernel buffer of size SIZE using consistent mode
218 * DMA for PCI device PDEV. Return non-NULL cpu-side address if
219 * successful and set *DMA_ADDRP to the PCI side dma address.
221 static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
223 struct pci_iommu *iommu;
225 unsigned long flags, order, first_page;
229 size = IO_PAGE_ALIGN(size);
230 order = get_order(size);
234 first_page = __get_free_pages(gfp, order);
235 if (first_page == 0UL)
237 memset((char *)first_page, 0, PAGE_SIZE << order);
239 iommu = pdev->dev.archdata.iommu;
241 spin_lock_irqsave(&iommu->lock, flags);
242 iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
243 spin_unlock_irqrestore(&iommu->lock, flags);
245 if (unlikely(iopte == NULL)) {
246 free_pages(first_page, order);
250 *dma_addrp = (iommu->page_table_map_base +
251 ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
252 ret = (void *) first_page;
253 npages = size >> IO_PAGE_SHIFT;
254 first_page = __pa(first_page);
256 iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
258 (first_page & IOPTE_PAGE));
260 first_page += IO_PAGE_SIZE;
266 /* Free and unmap a consistent DMA translation. */
267 static void pci_4u_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
269 struct pci_iommu *iommu;
271 unsigned long flags, order, npages;
273 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
274 iommu = pdev->dev.archdata.iommu;
275 iopte = iommu->page_table +
276 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
278 spin_lock_irqsave(&iommu->lock, flags);
280 free_npages(iommu, dvma - iommu->page_table_map_base, npages);
282 spin_unlock_irqrestore(&iommu->lock, flags);
284 order = get_order(size);
286 free_pages((unsigned long)cpu, order);
289 /* Map a single buffer at PTR of SZ bytes for PCI DMA
292 static dma_addr_t pci_4u_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
294 struct pci_iommu *iommu;
295 struct pci_strbuf *strbuf;
297 unsigned long flags, npages, oaddr;
298 unsigned long i, base_paddr, ctx;
300 unsigned long iopte_protection;
302 iommu = pdev->dev.archdata.iommu;
303 strbuf = pdev->dev.archdata.stc;
305 if (unlikely(direction == PCI_DMA_NONE))
308 oaddr = (unsigned long)ptr;
309 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
310 npages >>= IO_PAGE_SHIFT;
312 spin_lock_irqsave(&iommu->lock, flags);
313 base = alloc_npages(iommu, npages);
315 if (iommu->iommu_ctxflush)
316 ctx = iommu_alloc_ctx(iommu);
317 spin_unlock_irqrestore(&iommu->lock, flags);
322 bus_addr = (iommu->page_table_map_base +
323 ((base - iommu->page_table) << IO_PAGE_SHIFT));
324 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
325 base_paddr = __pa(oaddr & IO_PAGE_MASK);
326 if (strbuf->strbuf_enabled)
327 iopte_protection = IOPTE_STREAMING(ctx);
329 iopte_protection = IOPTE_CONSISTENT(ctx);
330 if (direction != PCI_DMA_TODEVICE)
331 iopte_protection |= IOPTE_WRITE;
333 for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
334 iopte_val(*base) = iopte_protection | base_paddr;
339 iommu_free_ctx(iommu, ctx);
341 if (printk_ratelimit())
343 return PCI_DMA_ERROR_CODE;
346 static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages, int direction)
350 if (strbuf->strbuf_ctxflush &&
351 iommu->iommu_ctxflush) {
352 unsigned long matchreg, flushreg;
355 flushreg = strbuf->strbuf_ctxflush;
356 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
358 pci_iommu_write(flushreg, ctx);
359 val = pci_iommu_read(matchreg);
366 pci_iommu_write(flushreg, ctx);
369 val = pci_iommu_read(matchreg);
371 printk(KERN_WARNING "pci_strbuf_flush: ctx flush "
372 "timeout matchreg[%lx] ctx[%lx]\n",
380 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
381 pci_iommu_write(strbuf->strbuf_pflush, vaddr);
385 /* If the device could not have possibly put dirty data into
386 * the streaming cache, no flush-flag synchronization needs
389 if (direction == PCI_DMA_TODEVICE)
392 PCI_STC_FLUSHFLAG_INIT(strbuf);
393 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
394 (void) pci_iommu_read(iommu->write_complete_reg);
397 while (!PCI_STC_FLUSHFLAG_SET(strbuf)) {
405 printk(KERN_WARNING "pci_strbuf_flush: flushflag timeout "
406 "vaddr[%08x] ctx[%lx] npages[%ld]\n",
410 /* Unmap a single streaming mode DMA translation. */
411 static void pci_4u_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
413 struct pci_iommu *iommu;
414 struct pci_strbuf *strbuf;
416 unsigned long flags, npages, ctx, i;
418 if (unlikely(direction == PCI_DMA_NONE)) {
419 if (printk_ratelimit())
424 iommu = pdev->dev.archdata.iommu;
425 strbuf = pdev->dev.archdata.stc;
427 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
428 npages >>= IO_PAGE_SHIFT;
429 base = iommu->page_table +
430 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
431 #ifdef DEBUG_PCI_IOMMU
432 if (IOPTE_IS_DUMMY(iommu, base))
433 printk("pci_unmap_single called on non-mapped region %08x,%08x from %016lx\n",
434 bus_addr, sz, __builtin_return_address(0));
436 bus_addr &= IO_PAGE_MASK;
438 spin_lock_irqsave(&iommu->lock, flags);
440 /* Record the context, if any. */
442 if (iommu->iommu_ctxflush)
443 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
445 /* Step 1: Kick data out of streaming buffers if necessary. */
446 if (strbuf->strbuf_enabled)
447 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx,
450 /* Step 2: Clear out TSB entries. */
451 for (i = 0; i < npages; i++)
452 iopte_make_dummy(iommu, base + i);
454 free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
456 iommu_free_ctx(iommu, ctx);
458 spin_unlock_irqrestore(&iommu->lock, flags);
461 #define SG_ENT_PHYS_ADDRESS(SG) \
462 (__pa(page_address((SG)->page)) + (SG)->offset)
464 static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
465 int nused, int nelems, unsigned long iopte_protection)
467 struct scatterlist *dma_sg = sg;
468 struct scatterlist *sg_end = sg + nelems;
471 for (i = 0; i < nused; i++) {
472 unsigned long pteval = ~0UL;
475 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
477 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
479 unsigned long offset;
482 /* If we are here, we know we have at least one
483 * more page to map. So walk forward until we
484 * hit a page crossing, and begin creating new
485 * mappings from that spot.
490 tmp = SG_ENT_PHYS_ADDRESS(sg);
492 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
493 pteval = tmp & IO_PAGE_MASK;
494 offset = tmp & (IO_PAGE_SIZE - 1UL);
497 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
498 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
500 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
506 pteval = iopte_protection | (pteval & IOPTE_PAGE);
508 *iopte++ = __iopte(pteval);
509 pteval += IO_PAGE_SIZE;
510 len -= (IO_PAGE_SIZE - offset);
515 pteval = (pteval & IOPTE_PAGE) + len;
518 /* Skip over any tail mappings we've fully mapped,
519 * adjusting pteval along the way. Stop when we
520 * detect a page crossing event.
522 while (sg < sg_end &&
523 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
524 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
526 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
527 pteval += sg->length;
530 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
532 } while (dma_npages != 0);
537 /* Map a set of buffers described by SGLIST with NELEMS array
538 * elements in streaming mode for PCI DMA.
539 * When making changes here, inspect the assembly output. I was having
540 * hard time to kepp this routine out of using stack slots for holding variables.
542 static int pci_4u_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
544 struct pci_iommu *iommu;
545 struct pci_strbuf *strbuf;
546 unsigned long flags, ctx, npages, iopte_protection;
549 struct scatterlist *sgtmp;
552 /* Fast path single entry scatterlists. */
554 sglist->dma_address =
555 pci_4u_map_single(pdev,
556 (page_address(sglist->page) + sglist->offset),
557 sglist->length, direction);
558 if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
560 sglist->dma_length = sglist->length;
564 iommu = pdev->dev.archdata.iommu;
565 strbuf = pdev->dev.archdata.stc;
567 if (unlikely(direction == PCI_DMA_NONE))
570 /* Step 1: Prepare scatter list. */
572 npages = prepare_sg(sglist, nelems);
574 /* Step 2: Allocate a cluster and context, if necessary. */
576 spin_lock_irqsave(&iommu->lock, flags);
578 base = alloc_npages(iommu, npages);
580 if (iommu->iommu_ctxflush)
581 ctx = iommu_alloc_ctx(iommu);
583 spin_unlock_irqrestore(&iommu->lock, flags);
588 dma_base = iommu->page_table_map_base +
589 ((base - iommu->page_table) << IO_PAGE_SHIFT);
591 /* Step 3: Normalize DMA addresses. */
595 while (used && sgtmp->dma_length) {
596 sgtmp->dma_address += dma_base;
600 used = nelems - used;
602 /* Step 4: Create the mappings. */
603 if (strbuf->strbuf_enabled)
604 iopte_protection = IOPTE_STREAMING(ctx);
606 iopte_protection = IOPTE_CONSISTENT(ctx);
607 if (direction != PCI_DMA_TODEVICE)
608 iopte_protection |= IOPTE_WRITE;
610 fill_sg(base, sglist, used, nelems, iopte_protection);
613 verify_sglist(sglist, nelems, base, npages);
619 iommu_free_ctx(iommu, ctx);
621 if (printk_ratelimit())
626 /* Unmap a set of streaming mode DMA translations. */
627 static void pci_4u_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
629 struct pci_iommu *iommu;
630 struct pci_strbuf *strbuf;
632 unsigned long flags, ctx, i, npages;
635 if (unlikely(direction == PCI_DMA_NONE)) {
636 if (printk_ratelimit())
640 iommu = pdev->dev.archdata.iommu;
641 strbuf = pdev->dev.archdata.stc;
643 bus_addr = sglist->dma_address & IO_PAGE_MASK;
645 for (i = 1; i < nelems; i++)
646 if (sglist[i].dma_length == 0)
649 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
650 bus_addr) >> IO_PAGE_SHIFT;
652 base = iommu->page_table +
653 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
655 #ifdef DEBUG_PCI_IOMMU
656 if (IOPTE_IS_DUMMY(iommu, base))
657 printk("pci_unmap_sg called on non-mapped region %016lx,%d from %016lx\n", sglist->dma_address, nelems, __builtin_return_address(0));
660 spin_lock_irqsave(&iommu->lock, flags);
662 /* Record the context, if any. */
664 if (iommu->iommu_ctxflush)
665 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
667 /* Step 1: Kick data out of streaming buffers if necessary. */
668 if (strbuf->strbuf_enabled)
669 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
671 /* Step 2: Clear out the TSB entries. */
672 for (i = 0; i < npages; i++)
673 iopte_make_dummy(iommu, base + i);
675 free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
677 iommu_free_ctx(iommu, ctx);
679 spin_unlock_irqrestore(&iommu->lock, flags);
682 /* Make physical memory consistent for a single
683 * streaming mode DMA translation after a transfer.
685 static void pci_4u_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
687 struct pci_iommu *iommu;
688 struct pci_strbuf *strbuf;
689 unsigned long flags, ctx, npages;
691 iommu = pdev->dev.archdata.iommu;
692 strbuf = pdev->dev.archdata.stc;
694 if (!strbuf->strbuf_enabled)
697 spin_lock_irqsave(&iommu->lock, flags);
699 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
700 npages >>= IO_PAGE_SHIFT;
701 bus_addr &= IO_PAGE_MASK;
703 /* Step 1: Record the context, if any. */
705 if (iommu->iommu_ctxflush &&
706 strbuf->strbuf_ctxflush) {
709 iopte = iommu->page_table +
710 ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
711 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
714 /* Step 2: Kick data out of streaming buffers. */
715 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
717 spin_unlock_irqrestore(&iommu->lock, flags);
720 /* Make physical memory consistent for a set of streaming
721 * mode DMA translations after a transfer.
723 static void pci_4u_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
725 struct pci_iommu *iommu;
726 struct pci_strbuf *strbuf;
727 unsigned long flags, ctx, npages, i;
730 iommu = pdev->dev.archdata.iommu;
731 strbuf = pdev->dev.archdata.stc;
733 if (!strbuf->strbuf_enabled)
736 spin_lock_irqsave(&iommu->lock, flags);
738 /* Step 1: Record the context, if any. */
740 if (iommu->iommu_ctxflush &&
741 strbuf->strbuf_ctxflush) {
744 iopte = iommu->page_table +
745 ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
746 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
749 /* Step 2: Kick data out of streaming buffers. */
750 bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
751 for(i = 1; i < nelems; i++)
752 if (!sglist[i].dma_length)
755 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length)
756 - bus_addr) >> IO_PAGE_SHIFT;
757 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
759 spin_unlock_irqrestore(&iommu->lock, flags);
762 struct pci_iommu_ops pci_sun4u_iommu_ops = {
763 .alloc_consistent = pci_4u_alloc_consistent,
764 .free_consistent = pci_4u_free_consistent,
765 .map_single = pci_4u_map_single,
766 .unmap_single = pci_4u_unmap_single,
767 .map_sg = pci_4u_map_sg,
768 .unmap_sg = pci_4u_unmap_sg,
769 .dma_sync_single_for_cpu = pci_4u_dma_sync_single_for_cpu,
770 .dma_sync_sg_for_cpu = pci_4u_dma_sync_sg_for_cpu,
773 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
775 struct pci_dev *ali_isa_bridge;
778 /* ALI sound chips generate 31-bits of DMA, a special register
779 * determines what bit 31 is emitted as.
781 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
782 PCI_DEVICE_ID_AL_M1533,
785 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
790 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
791 pci_dev_put(ali_isa_bridge);
794 int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
799 dma_addr_mask = 0xffffffff;
801 struct pci_iommu *iommu = pdev->dev.archdata.iommu;
803 dma_addr_mask = iommu->dma_addr_mask;
805 if (pdev->vendor == PCI_VENDOR_ID_AL &&
806 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
807 device_mask == 0x7fffffff) {
808 ali_sound_dma_hack(pdev,
809 (dma_addr_mask & 0x80000000) != 0);
814 if (device_mask >= (1UL << 32UL))
817 return (device_mask & dma_addr_mask) == dma_addr_mask;