4 * djhr: Hacked out of irq.c into a CPU dependent version.
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
12 #include <asm/timer.h>
13 #include <asm/traps.h>
14 #include <asm/pgalloc.h>
15 #include <asm/pgtable.h>
18 #include <asm/cacheflush.h>
23 /* Sample sun4m IRQ layout:
27 * 0x26 - Lance ethernet
31 * 0x33 - Parallel port, SBUS level 1
34 * 0x39 - Audio, Graphics card, SBUS level 4
38 * Each interrupt source has a mask bit in the interrupt registers.
39 * When the mask bit is set, this blocks interrupt deliver. So you
40 * clear the bit to enable the interrupt.
42 * Interrupts numbered less than 0x10 are software triggered interrupts
43 * and unused by Linux.
45 * Interrupt level assignment on sun4m:
48 * ------------------------------------------------------------
50 * 2 softint-2, VME/SBUS level 1
51 * 3 softint-3, VME/SBUS level 2
52 * 4 softint-4, onboard SCSI
53 * 5 softint-5, VME/SBUS level 3
54 * 6 softint-6, onboard ETHERNET
55 * 7 softint-7, VME/SBUS level 4
56 * 8 softint-8, onboard VIDEO
57 * 9 softint-9, VME/SBUS level 5, Module Interrupt
58 * 10 softint-10, system counter/timer
59 * 11 softint-11, VME/SBUS level 6, Floppy
60 * 12 softint-12, Keyboard/Mouse, Serial
61 * 13 softint-13, VME/SBUS level 7, ISDN Audio
62 * 14 softint-14, per-processor counter/timer
63 * 15 softint-15, Asynchronous Errors (broadcast)
65 * Each interrupt source is masked distinctly in the sun4m interrupt
66 * registers. The PIL level alone is therefore ambiguous, since multiple
67 * interrupt sources map to a single PIL.
69 * This ambiguity is resolved in the 'intr' property for device nodes
70 * in the OF device tree. Each 'intr' property entry is composed of
71 * two 32-bit words. The first word is the IRQ priority value, which
72 * is what we're intersted in. The second word is the IRQ vector, which
75 * The low 4 bits of the IRQ priority indicate the PIL, and the upper
76 * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
77 * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
79 * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
80 * whereas a value of 0x33 is SBUS level 2. Here are some sample
81 * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
82 * Tadpole S3 GX systems.
84 * esp: 0x24 onboard ESP SCSI
85 * le: 0x26 onboard Lance ETHERNET
86 * p9100: 0x32 SBUS level 1 P9100 video
87 * bpp: 0x33 SBUS level 2 BPP parallel port device
88 * DBRI: 0x39 SBUS level 5 DBRI ISDN audio
89 * SUNW,leo: 0x39 SBUS level 5 LEO video
90 * pcmcia: 0x3b SBUS level 6 PCMCIA controller
91 * uctrl: 0x3b SBUS level 6 UCTRL device
92 * modem: 0x3d SBUS level 7 MODEM
93 * zs: 0x2c onboard keyboard/mouse/serial
94 * floppy: 0x2b onboard Floppy
95 * power: 0x22 onboard power device (XXX unknown mask bit XXX)
99 struct sun4m_irq_percpu {
105 struct sun4m_irq_global {
110 u32 interrupt_target;
113 /* Code in entry.S needs to get at these register mappings. */
114 struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
115 struct sun4m_irq_global __iomem *sun4m_irq_global;
117 /* Dave Redman (djhr@tadpole.co.uk)
118 * The sun4m interrupt registers.
120 #define SUN4M_INT_ENABLE 0x80000000
121 #define SUN4M_INT_E14 0x00000080
122 #define SUN4M_INT_E10 0x00080000
124 #define SUN4M_HARD_INT(x) (0x000000001 << (x))
125 #define SUN4M_SOFT_INT(x) (0x000010000 << (x))
127 #define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
128 #define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
129 #define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
130 #define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
131 #define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
132 #define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
133 #define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
134 #define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
135 #define SUN4M_INT_REALTIME 0x00080000 /* system timer */
136 #define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
137 #define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
138 #define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
139 #define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
140 #define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
141 #define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
142 #define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
144 #define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \
145 SUN4M_INT_M2S_WRITE_ERR | \
146 SUN4M_INT_ECC_ERR | \
149 #define SUN4M_INT_SBUS(x) (1 << (x+7))
150 #define SUN4M_INT_VME(x) (1 << (x))
152 /* Interrupt levels used by OBP */
153 #define OBP_INT_LEVEL_SOFT 0x10
154 #define OBP_INT_LEVEL_ONBOARD 0x20
155 #define OBP_INT_LEVEL_SBUS 0x30
156 #define OBP_INT_LEVEL_VME 0x40
158 static unsigned long irq_mask[0x50] = {
160 0, SUN4M_SOFT_INT(1),
161 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
162 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
163 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
164 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
165 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
166 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
167 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
169 0, SUN4M_SOFT_INT(1),
170 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
171 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
172 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
173 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
174 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
175 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
176 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
179 SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
180 SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
181 SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
182 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
183 SUN4M_INT_AUDIO, 0, SUN4M_INT_MODULE_ERR,
185 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
186 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
187 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
188 0, SUN4M_INT_SBUS(6), 0, 0,
190 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
191 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
192 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
193 0, SUN4M_INT_VME(6), 0, 0
196 static unsigned long sun4m_get_irqmask(unsigned int irq)
201 mask = irq_mask[irq];
206 printk(KERN_ERR "sun4m_get_irqmask: IRQ%d has no valid mask!\n",
212 static void sun4m_disable_irq(unsigned int irq_nr)
214 unsigned long mask, flags;
215 int cpu = smp_processor_id();
217 mask = sun4m_get_irqmask(irq_nr);
218 local_irq_save(flags);
220 sbus_writel(mask, &sun4m_irq_global->mask_set);
222 sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
223 local_irq_restore(flags);
226 static void sun4m_enable_irq(unsigned int irq_nr)
228 unsigned long mask, flags;
229 int cpu = smp_processor_id();
231 /* Dreadful floppy hack. When we use 0x2b instead of
232 * 0x0b the system blows (it starts to whistle!).
233 * So we continue to use 0x0b. Fixme ASAP. --P3
235 if (irq_nr != 0x0b) {
236 mask = sun4m_get_irqmask(irq_nr);
237 local_irq_save(flags);
239 sbus_writel(mask, &sun4m_irq_global->mask_clear);
241 sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
242 local_irq_restore(flags);
244 local_irq_save(flags);
245 sbus_writel(SUN4M_INT_FLOPPY, &sun4m_irq_global->mask_clear);
246 local_irq_restore(flags);
250 static unsigned long cpu_pil_to_imask[16] = {
253 /*2*/ SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
254 /*3*/ SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
255 /*4*/ SUN4M_INT_SCSI,
256 /*5*/ SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
257 /*6*/ SUN4M_INT_ETHERNET,
258 /*7*/ SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
259 /*8*/ SUN4M_INT_VIDEO,
260 /*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
261 /*10*/ SUN4M_INT_REALTIME,
262 /*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
263 /*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
264 /*13*/ SUN4M_INT_SBUS(6) | SUN4M_INT_VME(6) | SUN4M_INT_AUDIO,
265 /*14*/ SUN4M_INT_E14,
266 /*15*/ SUN4M_INT_ERROR,
269 /* We assume the caller has disabled local interrupts when these are called,
270 * or else very bizarre behavior will result.
272 static void sun4m_disable_pil_irq(unsigned int pil)
274 sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_set);
277 static void sun4m_enable_pil_irq(unsigned int pil)
279 sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_clear);
283 static void sun4m_send_ipi(int cpu, int level)
285 unsigned long mask = sun4m_get_irqmask(level);
287 sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
290 static void sun4m_clear_ipi(int cpu, int level)
292 unsigned long mask = sun4m_get_irqmask(level);
294 sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
297 static void sun4m_set_udt(int cpu)
299 sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
303 struct sun4m_timer_percpu {
306 u32 l14_limit_noclear;
307 u32 user_timer_start_stop;
310 static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
312 struct sun4m_timer_global {
315 u32 l10_limit_noclear;
320 static struct sun4m_timer_global __iomem *timers_global;
322 #define TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
324 unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
326 static void sun4m_clear_clock_irq(void)
328 sbus_readl(&timers_global->l10_limit);
331 void sun4m_nmi(struct pt_regs *regs)
333 unsigned long afsr, afar, si;
335 printk(KERN_ERR "Aieee: sun4m NMI received!\n");
336 /* XXX HyperSparc hack XXX */
337 __asm__ __volatile__("mov 0x500, %%g1\n\t"
338 "lda [%%g1] 0x4, %0\n\t"
339 "mov 0x600, %%g1\n\t"
340 "lda [%%g1] 0x4, %1\n\t" :
341 "=r" (afsr), "=r" (afar));
342 printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
343 si = sbus_readl(&sun4m_irq_global->pending);
344 printk(KERN_ERR "si=%08lx\n", si);
345 if (si & SUN4M_INT_MODULE_ERR)
346 printk(KERN_ERR "Module async error\n");
347 if (si & SUN4M_INT_M2S_WRITE_ERR)
348 printk(KERN_ERR "MBus/SBus async error\n");
349 if (si & SUN4M_INT_ECC_ERR)
350 printk(KERN_ERR "ECC memory error\n");
351 if (si & SUN4M_INT_VME_ERR)
352 printk(KERN_ERR "VME async error\n");
353 printk(KERN_ERR "you lose buddy boy...\n");
358 /* Exported for sun4m_smp.c */
359 void sun4m_clear_profile_irq(int cpu)
361 sbus_readl(&timers_percpu[cpu]->l14_limit);
364 static void sun4m_load_profile_irq(int cpu, unsigned int limit)
366 sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
369 static void __init sun4m_init_timers(irq_handler_t counter_fn)
371 struct device_node *dp = of_find_node_by_name(NULL, "counter");
372 int i, err, len, num_cpu_timers;
376 printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
380 addr = of_get_property(dp, "address", &len);
383 printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
387 num_cpu_timers = (len / sizeof(u32)) - 1;
388 for (i = 0; i < num_cpu_timers; i++) {
389 timers_percpu[i] = (void __iomem *)
390 (unsigned long) addr[i];
392 timers_global = (void __iomem *)
393 (unsigned long) addr[num_cpu_timers];
395 sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
397 master_l10_counter = &timers_global->l10_count;
399 err = request_irq(TIMER_IRQ, counter_fn,
400 (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
402 printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
407 for (i = 0; i < num_cpu_timers; i++)
408 sbus_writel(0, &timers_percpu[i]->l14_limit);
409 if (num_cpu_timers == 4)
410 sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
415 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
417 /* For SMP we use the level 14 ticker, however the bootup code
418 * has copied the firmware's level 14 vector into the boot cpu's
419 * trap table, we must fix this now or we get squashed.
421 local_irq_save(flags);
422 trap_table->inst_one = lvl14_save[0];
423 trap_table->inst_two = lvl14_save[1];
424 trap_table->inst_three = lvl14_save[2];
425 trap_table->inst_four = lvl14_save[3];
426 local_flush_cache_all();
427 local_irq_restore(flags);
432 void __init sun4m_init_IRQ(void)
434 struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
435 int len, i, mid, num_cpu_iregs;
439 printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
443 addr = of_get_property(dp, "address", &len);
446 printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
450 num_cpu_iregs = (len / sizeof(u32)) - 1;
451 for (i = 0; i < num_cpu_iregs; i++) {
452 sun4m_irq_percpu[i] = (void __iomem *)
453 (unsigned long) addr[i];
455 sun4m_irq_global = (void __iomem *)
456 (unsigned long) addr[num_cpu_iregs];
460 sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
461 for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
462 sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
464 if (num_cpu_iregs == 4)
465 sbus_writel(0, &sun4m_irq_global->interrupt_target);
467 BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
468 BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
469 BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
470 BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
471 BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
472 BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
473 sparc_init_timers = sun4m_init_timers;
475 BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
476 BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
477 BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
480 /* Cannot enable interrupts until OBP ticker is disabled. */