2 * arch/sh/kernel/cpu/init.c
6 * Copyright (C) 2002, 2003 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <asm/processor.h>
16 #include <asm/uaccess.h>
17 #include <asm/system.h>
18 #include <asm/cacheflush.h>
19 #include <asm/cache.h>
22 extern void detect_cpu_and_cache_system(void);
25 * Generic wrapper for command line arguments to disable on-chip
26 * peripherals (nofpu, nodsp, and so forth).
28 #define onchip_setup(x) \
29 static int x##_disabled __initdata = 0; \
31 static int __init x##_setup(char *opts) \
36 __setup("no" __stringify(x), x##_setup);
42 * Generic first-level cache init
44 static void __init cache_init(void)
46 unsigned long ccr, flags;
48 if (cpu_data->type == CPU_SH_NONE)
55 * At this point we don't know whether the cache is enabled or not - a
56 * bootloader may have enabled it. There are at least 2 things that
57 * could be dirty in the cache at this point:
58 * 1. kernel command line set up by boot loader
59 * 2. spilled registers from the prolog of this function
60 * => before re-initialising the cache, we must do a purge of the whole
61 * cache out to memory for safety. As long as nothing is spilled
62 * during the loop to lines that have already been done, this is safe.
65 if (ccr & CCR_CACHE_ENABLE) {
66 unsigned long ways, waysize, addrstart;
68 waysize = cpu_data->dcache.sets;
71 * If the OC is already in RAM mode, we only have
72 * half of the entries to flush..
74 if (ccr & CCR_CACHE_ORA)
77 waysize <<= cpu_data->dcache.entry_shift;
79 #ifdef CCR_CACHE_EMODE
80 /* If EMODE is not set, we only have 1 way to flush. */
81 if (!(ccr & CCR_CACHE_EMODE))
85 ways = cpu_data->dcache.ways;
87 addrstart = CACHE_OC_ADDRESS_ARRAY;
91 for (addr = addrstart;
92 addr < addrstart + waysize;
93 addr += cpu_data->dcache.linesz)
96 addrstart += cpu_data->dcache.way_incr;
101 * Default CCR values .. enable the caches
102 * and invalidate them immediately..
104 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
106 #ifdef CCR_CACHE_EMODE
107 /* Force EMODE if possible */
108 if (cpu_data->dcache.ways > 1)
109 flags |= CCR_CACHE_EMODE;
111 flags &= ~CCR_CACHE_EMODE;
114 #ifdef CONFIG_SH_WRITETHROUGH
115 /* Turn on Write-through caching */
116 flags |= CCR_CACHE_WT;
118 /* .. or default to Write-back */
119 flags |= CCR_CACHE_CB;
122 #ifdef CONFIG_SH_OCRAM
123 /* Turn on OCRAM -- halve the OC */
124 flags |= CCR_CACHE_ORA;
125 cpu_data->dcache.sets >>= 1;
127 cpu_data->dcache.way_size = cpu_data->dcache.sets *
128 cpu_data->dcache.linesz;
131 ctrl_outl(flags, CCR);
136 static void __init release_dsp(void)
140 /* Clear SR.DSP bit */
141 __asm__ __volatile__ (
150 static void __init dsp_init(void)
155 * Set the SR.DSP bit, wait for one instruction, and then read
158 __asm__ __volatile__ (
168 /* If the DSP bit is still set, this CPU has a DSP */
170 cpu_data->flags |= CPU_HAS_DSP;
172 /* Now that we've determined the DSP status, clear the DSP bit. */
175 #endif /* CONFIG_SH_DSP */
180 * This is our initial entry point for each CPU, and is invoked on the boot
181 * CPU prior to calling start_kernel(). For SMP, a combination of this and
182 * start_secondary() will bring up each processor to a ready state prior
183 * to hand forking the idle loop.
185 * We do all of the basic processor init here, including setting up the
186 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
187 * hit (and subsequently platform_setup()) things like determining the
188 * CPU subtype and initial configuration will all be done.
190 * Each processor family is still responsible for doing its own probing
191 * and cache configuration in detect_cpu_and_cache_system().
193 asmlinkage void __init sh_cpu_init(void)
195 /* First, probe the CPU */
196 detect_cpu_and_cache_system();
201 /* Disable the FPU */
203 printk("FPU Disabled\n");
204 cpu_data->flags &= ~CPU_HAS_FPU;
208 /* FPU initialization */
209 if ((cpu_data->flags & CPU_HAS_FPU)) {
210 clear_thread_flag(TIF_USEDFPU);
218 /* Disable the DSP */
220 printk("DSP Disabled\n");
221 cpu_data->flags &= ~CPU_HAS_DSP;
226 #ifdef CONFIG_UBC_WAKEUP
228 * Some brain-damaged loaders decided it would be a good idea to put
229 * the UBC to sleep. This causes some issues when it comes to things
230 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So ..
231 * we wake it up and hope that all is well.