2 * Low-Level PCI Support for the SH7780
4 * Dustin McIntire (dustin@sensoria.com)
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
25 #define INTC_BASE 0xffd00000
26 #define INTC_ICR0 (INTC_BASE+0x0)
27 #define INTC_ICR1 (INTC_BASE+0x1c)
28 #define INTC_INTPRI (INTC_BASE+0x10)
29 #define INTC_INTREQ (INTC_BASE+0x24)
30 #define INTC_INTMSK0 (INTC_BASE+0x44)
31 #define INTC_INTMSK1 (INTC_BASE+0x48)
32 #define INTC_INTMSK2 (INTC_BASE+0x40080)
33 #define INTC_INTMSKCLR0 (INTC_BASE+0x64)
34 #define INTC_INTMSKCLR1 (INTC_BASE+0x68)
35 #define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
36 #define INTC_INT2MSKR (INTC_BASE+0x40038)
37 #define INTC_INT2MSKCR (INTC_BASE+0x4003c)
40 * Initialization. Try all known PCI access methods. Note that we support
41 * using both PCI BIOS and direct access: in such cases, we use I/O ports
42 * to access config space.
44 * Note that the platform specific initialization (BSC registers, and memory
45 * space mapping) will be called via the platform defined function
46 * pcibios_init_platform().
48 int __init sh7780_pci_init(struct pci_channel *chan)
53 pr_debug("PCI: Starting intialization.\n");
55 chan->reg_base = 0xfe040000;
56 chan->io_base = 0xfe200000;
58 ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
60 /* check for SH7780/SH7780R hardware */
61 id = pci_read_reg(chan, SH7780_PCIVID);
62 if ((id & 0xffff) == SH7780_VENDOR_ID) {
63 switch ((id >> 16) & 0xffff) {
64 case SH7763_DEVICE_ID:
65 case SH7780_DEVICE_ID:
66 case SH7781_DEVICE_ID:
67 case SH7785_DEVICE_ID:
73 if (unlikely(!match)) {
74 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
79 if (mach_is_7780se()) {
80 /* ICR0: IRL=use separately */
81 ctrl_outl(0x00C00020, INTC_ICR0);
82 /* ICR1: detect low level(for 2ndcut) */
83 ctrl_outl(0xAAAA0000, INTC_ICR1);
84 /* INTPRI: priority=3(all) */
85 ctrl_outl(0x33333333, INTC_INTPRI);
88 if ((ret = sh4_pci_check_direct(chan)) != 0)
91 return pcibios_init_platform();
94 int __init sh7780_pcic_init(struct pci_channel *chan,
95 struct sh4_pci_address_map *map)
99 /* set the command/status bits to:
100 * Wait Cycle Control + Parity Enable + Bus Master +
103 pci_write_reg(chan, 0x00000046, SH7780_PCICMD);
105 /* define this host as the host bridge */
106 word = PCI_BASE_CLASS_BRIDGE << 24;
107 pci_write_reg(chan, word, SH7780_PCIRID);
109 /* Set IO and Mem windows to local address
110 * Make PCI and local address the same for easy 1 to 1 mapping
112 pci_write_reg(chan, map->window0.size - 0xfffff, SH4_PCILSR0);
113 pci_write_reg(chan, map->window1.size - 0xfffff, SH4_PCILSR1);
114 /* Set the values on window 0 PCI config registers */
115 pci_write_reg(chan, map->window0.base, SH4_PCILAR0);
116 pci_write_reg(chan, map->window0.base, SH7780_PCIMBAR0);
117 /* Set the values on window 1 PCI config registers */
118 pci_write_reg(chan, map->window1.base, SH4_PCILAR1);
119 pci_write_reg(chan, map->window1.base, SH7780_PCIMBAR1);
121 /* Map IO space into PCI IO window:
122 * IO addresses will be translated to the PCI IO window base address
124 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%lx\n",
125 chan->io_resource->start, chan->io_resource->end,
126 chan->io_base + chan->io_resource->start);
128 /* NOTE: I'm ignoring the PCI error IRQs for now..
129 * TODO: add support for the internal error interrupts and
133 /* Apply any last-minute PCIC fixups */
134 pci_fixup_pcic(chan);
136 /* SH7780 init done, set central function init complete */
137 /* use round robin mode to stop a device starving/overruning */
138 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
139 pci_write_reg(chan, word, SH4_PCICR);