arch/powerpc/platforms/pasemi/setup.c

   1 /*
   2  * Copyright (C) 2006-2007 PA Semi, Inc
   3  *
   4  * Authors: Kip Walker, PA Semi
   5  *          Olof Johansson, PA Semi
   6  *
   7  * Maintained by: Olof Johansson <olof@lixom.net>
   8  *
   9  * Based on arch/powerpc/platforms/maple/setup.c
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/errno.h>
  26 #include <linux/kernel.h>
  27 #include <linux/delay.h>
  28 #include <linux/console.h>
  29 #include <linux/pci.h>
  30 #include <linux/of_platform.h>
  31
  32 #include <asm/prom.h>
  33 #include <asm/system.h>
  34 #include <asm/iommu.h>
  35 #include <asm/machdep.h>
  36 #include <asm/mpic.h>
  37 #include <asm/smp.h>
  38 #include <asm/time.h>
  39 #include <asm/mmu.h>
  40
  41 #include <pcmcia/ss.h>
  42 #include <pcmcia/cistpl.h>
  43 #include <pcmcia/ds.h>
  44
  45 #include "pasemi.h"
  46
  47 #if !defined(CONFIG_SMP)
  48 static void smp_send_stop(void) {}
  49 #endif
  50
  51 /* SDC reset register, must be pre-mapped at reset time */
  52 static void __iomem *reset_reg;
  53
  54 /* Various error status registers, must be pre-mapped at MCE time */
  55
  56 #define MAX_MCE_REGS    32
  57 struct mce_regs {
  58         char *name;
  59         void __iomem *addr;
  60 };
  61
  62 static struct mce_regs mce_regs[MAX_MCE_REGS];
  63 static int num_mce_regs;
  64
  65
  66 static void pas_restart(char *cmd)
  67 {
  68         /* Need to put others cpu in hold loop so they're not sleeping */
  69         smp_send_stop();
  70         udelay(10000);
  71         printk("Restarting...\n");
  72         while (1)
  73                 out_le32(reset_reg, 0x6000000);
  74 }
  75
  76 #ifdef CONFIG_SMP
  77 static DEFINE_SPINLOCK(timebase_lock);
  78 static unsigned long timebase;
  79
  80 static void __devinit pas_give_timebase(void)
  81 {
  82         spin_lock(&timebase_lock);
  83         mtspr(SPRN_TBCTL, TBCTL_FREEZE);
  84         isync();
  85         timebase = get_tb();
  86         spin_unlock(&timebase_lock);
  87
  88         while (timebase)
  89                 barrier();
  90         mtspr(SPRN_TBCTL, TBCTL_RESTART);
  91 }
  92
  93 static void __devinit pas_take_timebase(void)
  94 {
  95         while (!timebase)
  96                 smp_rmb();
  97
  98         spin_lock(&timebase_lock);
  99         set_tb(timebase >> 32, timebase & 0xffffffff);
 100         timebase = 0;
 101         spin_unlock(&timebase_lock);
 102 }
 103
 104 struct smp_ops_t pas_smp_ops = {
 105         .probe          = smp_mpic_probe,
 106         .message_pass   = smp_mpic_message_pass,
 107         .kick_cpu       = smp_generic_kick_cpu,
 108         .setup_cpu      = smp_mpic_setup_cpu,
 109         .give_timebase  = pas_give_timebase,
 110         .take_timebase  = pas_take_timebase,
 111 };
 112 #endif /* CONFIG_SMP */
 113
 114 void __init pas_setup_arch(void)
 115 {
 116 #ifdef CONFIG_SMP
 117         /* Setup SMP callback */
 118         smp_ops = &pas_smp_ops;
 119 #endif
 120         /* Lookup PCI hosts */
 121         pas_pci_init();
 122
 123 #ifdef CONFIG_DUMMY_CONSOLE
 124         conswitchp = &dummy_con;
 125 #endif
 126
 127         /* Remap SDC register for doing reset */
 128         /* XXXOJN This should maybe come out of the device tree */
 129         reset_reg = ioremap(0xfc101100, 4);
 130 }
 131
 132 static int __init pas_setup_mce_regs(void)
 133 {
 134         struct pci_dev *dev;
 135         int reg;
 136
 137         if (!machine_is(pasemi))
 138                 return -ENODEV;
 139
 140         /* Remap various SoC status registers for use by the MCE handler */
 141
 142         reg = 0;
 143
 144         dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
 145         while (dev && reg < MAX_MCE_REGS) {
 146                 mce_regs[reg].name = kasprintf(GFP_KERNEL,
 147                                                 "mc%d_mcdebug_errsta", reg);
 148                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
 149                 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
 150                 reg++;
 151         }
 152
 153         dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
 154         if (dev && reg+4 < MAX_MCE_REGS) {
 155                 mce_regs[reg].name = "iobdbg_IntStatus1";
 156                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
 157                 reg++;
 158                 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
 159                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
 160                 reg++;
 161                 mce_regs[reg].name = "iobiom_IntStatus";
 162                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
 163                 reg++;
 164                 mce_regs[reg].name = "iobiom_IntDbgReg";
 165                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
 166                 reg++;
 167         }
 168
 169         dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
 170         if (dev && reg+2 < MAX_MCE_REGS) {
 171                 mce_regs[reg].name = "l2csts_IntStatus";
 172                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
 173                 reg++;
 174                 mce_regs[reg].name = "l2csts_Cnt";
 175                 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
 176                 reg++;
 177         }
 178
 179         num_mce_regs = reg;
 180
 181         return 0;
 182 }
 183 device_initcall(pas_setup_mce_regs);
 184
 185 static __init void pas_init_IRQ(void)
 186 {
 187         struct device_node *np;
 188         struct device_node *root, *mpic_node;
 189         unsigned long openpic_addr;
 190         const unsigned int *opprop;
 191         int naddr, opplen;
 192         struct mpic *mpic;
 193
 194         mpic_node = NULL;
 195
 196         for_each_node_by_type(np, "interrupt-controller")
 197                 if (of_device_is_compatible(np, "open-pic")) {
 198                         mpic_node = np;
 199                         break;
 200                 }
 201         if (!mpic_node)
 202                 for_each_node_by_type(np, "open-pic") {
 203                         mpic_node = np;
 204                         break;
 205                 }
 206         if (!mpic_node) {
 207                 printk(KERN_ERR
 208                         "Failed to locate the MPIC interrupt controller\n");
 209                 return;
 210         }
 211
 212         /* Find address list in /platform-open-pic */
 213         root = of_find_node_by_path("/");
 214         naddr = of_n_addr_cells(root);
 215         opprop = of_get_property(root, "platform-open-pic", &opplen);
 216         if (!opprop) {
 217                 printk(KERN_ERR "No platform-open-pic property.\n");
 218                 of_node_put(root);
 219                 return;
 220         }
 221         openpic_addr = of_read_number(opprop, naddr);
 222         printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
 223
 224         mpic = mpic_alloc(mpic_node, openpic_addr,
 225                           MPIC_PRIMARY|MPIC_LARGE_VECTORS,
 226                           0, 0, " PAS-OPIC  ");
 227         BUG_ON(!mpic);
 228
 229         mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
 230         mpic_init(mpic);
 231         of_node_put(mpic_node);
 232         of_node_put(root);
 233 }
 234
 235 static void __init pas_progress(char *s, unsigned short hex)
 236 {
 237         printk("[%04x] : %s\n", hex, s ? s : "");
 238 }
 239
 240
 241 static int pas_machine_check_handler(struct pt_regs *regs)
 242 {
 243         int cpu = smp_processor_id();
 244         unsigned long srr0, srr1, dsisr;
 245         int dump_slb = 0;
 246         int i;
 247
 248         srr0 = regs->nip;
 249         srr1 = regs->msr;
 250         dsisr = mfspr(SPRN_DSISR);
 251         printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
 252         printk(KERN_ERR "SRR0  0x%016lx SRR1 0x%016lx\n", srr0, srr1);
 253         printk(KERN_ERR "DSISR 0x%016lx DAR  0x%016lx\n", dsisr, regs->dar);
 254         printk(KERN_ERR "BER   0x%016lx MER  0x%016lx\n", mfspr(SPRN_PA6T_BER),
 255                 mfspr(SPRN_PA6T_MER));
 256         printk(KERN_ERR "IER   0x%016lx DER  0x%016lx\n", mfspr(SPRN_PA6T_IER),
 257                 mfspr(SPRN_PA6T_DER));
 258         printk(KERN_ERR "Cause:\n");
 259
 260         if (srr1 & 0x200000)
 261                 printk(KERN_ERR "Signalled by SDC\n");
 262
 263         if (srr1 & 0x100000) {
 264                 printk(KERN_ERR "Load/Store detected error:\n");
 265                 if (dsisr & 0x8000)
 266                         printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
 267                 if (dsisr & 0x4000)
 268                         printk(KERN_ERR "LSU snoop response error\n");
 269                 if (dsisr & 0x2000) {
 270                         printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
 271                         dump_slb = 1;
 272                 }
 273                 if (dsisr & 0x1000)
 274                         printk(KERN_ERR "Recoverable Duptags\n");
 275                 if (dsisr & 0x800)
 276                         printk(KERN_ERR "Recoverable D-cache parity error count overflow\n");
 277                 if (dsisr & 0x400)
 278                         printk(KERN_ERR "TLB parity error count overflow\n");
 279         }
 280
 281         if (srr1 & 0x80000)
 282                 printk(KERN_ERR "Bus Error\n");
 283
 284         if (srr1 & 0x40000) {
 285                 printk(KERN_ERR "I-side SLB multiple hit\n");
 286                 dump_slb = 1;
 287         }
 288
 289         if (srr1 & 0x20000)
 290                 printk(KERN_ERR "I-cache parity error hit\n");
 291
 292         if (num_mce_regs == 0)
 293                 printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
 294         else
 295                 printk(KERN_ERR "SoC debug registers:\n");
 296
 297         for (i = 0; i < num_mce_regs; i++)
 298                 printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
 299                         in_le32(mce_regs[i].addr));
 300
 301         if (dump_slb) {
 302                 unsigned long e, v;
 303                 int i;
 304
 305                 printk(KERN_ERR "slb contents:\n");
 306                 for (i = 0; i < mmu_slb_size; i++) {
 307                         asm volatile("slbmfee  %0,%1" : "=r" (e) : "r" (i));
 308                         asm volatile("slbmfev  %0,%1" : "=r" (v) : "r" (i));
 309                         printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
 310                 }
 311         }
 312
 313
 314         /* SRR1[62] is from MSR[62] if recoverable, so pass that back */
 315         return !!(srr1 & 0x2);
 316 }
 317
 318 static void __init pas_init_early(void)
 319 {
 320         iommu_init_early_pasemi();
 321 }
 322
 323 #ifdef CONFIG_PCMCIA
 324 static int pcmcia_notify(struct notifier_block *nb, unsigned long action,
 325                          void *data)
 326 {
 327         struct device *dev = data;
 328         struct device *parent;
 329         struct pcmcia_device *pdev = to_pcmcia_dev(dev);
 330
 331         /* We are only intereted in device addition */
 332         if (action != BUS_NOTIFY_ADD_DEVICE)
 333                 return 0;
 334
 335         parent = pdev->socket->dev.parent;
 336
 337         /* We know electra_cf devices will always have of_node set, since
 338          * electra_cf is an of_platform driver.
 339          */
 340         if (!parent->archdata.of_node)
 341                 return 0;
 342
 343         if (!of_device_is_compatible(parent->archdata.of_node, "electra-cf"))
 344                 return 0;
 345
 346         /* We use the direct ops for localbus */
 347         dev->archdata.dma_ops = &dma_direct_ops;
 348
 349         return 0;
 350 }
 351
 352 static struct notifier_block pcmcia_notifier = {
 353         .notifier_call = pcmcia_notify,
 354 };
 355
 356 static inline void pasemi_pcmcia_init(void)
 357 {
 358         extern struct bus_type pcmcia_bus_type;
 359
 360         bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier);
 361 }
 362
 363 #else
 364
 365 static inline void pasemi_pcmcia_init(void)
 366 {
 367 }
 368
 369 #endif
 370
 371
 372 static struct of_device_id pasemi_bus_ids[] = {
 373         /* Unfortunately needed for legacy firmwares */
 374         { .type = "localbus", },
 375         { .type = "sdc", },
 376         /* These are the proper entries, which newer firmware uses */
 377         { .compatible = "pasemi,localbus", },
 378         { .compatible = "pasemi,sdc", },
 379         {},
 380 };
 381
 382 static int __init pasemi_publish_devices(void)
 383 {
 384         if (!machine_is(pasemi))
 385                 return 0;
 386
 387         pasemi_pcmcia_init();
 388
 389         /* Publish OF platform devices for SDC and other non-PCI devices */
 390         of_platform_bus_probe(NULL, pasemi_bus_ids, NULL);
 391
 392         return 0;
 393 }
 394 device_initcall(pasemi_publish_devices);
 395
 396
 397 /*
 398  * Called very early, MMU is off, device-tree isn't unflattened
 399  */
 400 static int __init pas_probe(void)
 401 {
 402         unsigned long root = of_get_flat_dt_root();
 403
 404         if (!of_flat_dt_is_compatible(root, "PA6T-1682M") &&
 405             !of_flat_dt_is_compatible(root, "pasemi,pwrficient"))
 406                 return 0;
 407
 408         hpte_init_native();
 409
 410         alloc_iobmap_l2();
 411
 412         return 1;
 413 }
 414
 415 define_machine(pasemi) {
 416         .name                   = "PA Semi PWRficient",
 417         .probe                  = pas_probe,
 418         .setup_arch             = pas_setup_arch,
 419         .init_early             = pas_init_early,
 420         .init_IRQ               = pas_init_IRQ,
 421         .get_irq                = mpic_get_irq,
 422         .restart                = pas_restart,
 423         .get_boot_time          = pas_get_boot_time,
 424         .calibrate_decr         = generic_calibrate_decr,
 425         .progress               = pas_progress,
 426         .machine_check_exception = pas_machine_check_handler,
 427 };