arch/powerpc/platforms/cell/interrupt.c

   1 /*
   2  * Cell Internal Interrupt Controller
   3  *
   4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   5  *
   6  * Author: Arnd Bergmann <arndb@de.ibm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/config.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/module.h>
  27 #include <linux/percpu.h>
  28 #include <linux/types.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/prom.h>
  33 #include <asm/ptrace.h>
  34
  35 #include "interrupt.h"
  36
  37 struct iic_pending_bits {
  38         u32 data;
  39         u8 flags;
  40         u8 class;
  41         u8 source;
  42         u8 prio;
  43 };
  44
  45 enum iic_pending_flags {
  46         IIC_VALID = 0x80,
  47         IIC_IPI   = 0x40,
  48 };
  49
  50 struct iic_regs {
  51         struct iic_pending_bits pending;
  52         struct iic_pending_bits pending_destr;
  53         u64 generate;
  54         u64 prio;
  55 };
  56
  57 struct iic {
  58         struct iic_regs __iomem *regs;
  59         u8 target_id;
  60 };
  61
  62 static DEFINE_PER_CPU(struct iic, iic);
  63
  64 void iic_local_enable(void)
  65 {
  66         struct iic *iic = &__get_cpu_var(iic);
  67         u64 tmp;
  68
  69         /*
  70          * There seems to be a bug that is present in DD2.x CPUs
  71          * and still only partially fixed in DD3.1.
  72          * This bug causes a value written to the priority register
  73          * not to make it there, resulting in a system hang unless we
  74          * write it again.
  75          * Masking with 0xf0 is done because the Cell BE does not
  76          * implement the lower four bits of the interrupt priority,
  77          * they always read back as zeroes, although future CPUs
  78          * might implement different bits.
  79          */
  80         do {
  81                 out_be64(&iic->regs->prio, 0xff);
  82                 tmp = in_be64(&iic->regs->prio);
  83         } while ((tmp & 0xf0) != 0xf0);
  84 }
  85
  86 void iic_local_disable(void)
  87 {
  88         out_be64(&__get_cpu_var(iic).regs->prio, 0x0);
  89 }
  90
  91 static unsigned int iic_startup(unsigned int irq)
  92 {
  93         return 0;
  94 }
  95
  96 static void iic_enable(unsigned int irq)
  97 {
  98         iic_local_enable();
  99 }
 100
 101 static void iic_disable(unsigned int irq)
 102 {
 103 }
 104
 105 static void iic_end(unsigned int irq)
 106 {
 107         iic_local_enable();
 108 }
 109
 110 static struct hw_interrupt_type iic_pic = {
 111         .typename = " CELL-IIC ",
 112         .startup = iic_startup,
 113         .enable = iic_enable,
 114         .disable = iic_disable,
 115         .end = iic_end,
 116 };
 117
 118 static int iic_external_get_irq(struct iic_pending_bits pending)
 119 {
 120         int irq;
 121         unsigned char node, unit;
 122
 123         node = pending.source >> 4;
 124         unit = pending.source & 0xf;
 125         irq = -1;
 126
 127         /*
 128          * This mapping is specific to the Cell Broadband
 129          * Engine. We might need to get the numbers
 130          * from the device tree to support future CPUs.
 131          */
 132         switch (unit) {
 133         case 0x00:
 134         case 0x0b:
 135                 /*
 136                  * One of these units can be connected
 137                  * to an external interrupt controller.
 138                  */
 139                 if (pending.prio > 0x3f ||
 140                     pending.class != 2)
 141                         break;
 142                 irq = IIC_EXT_OFFSET
 143                         + spider_get_irq(node)
 144                         + node * IIC_NODE_STRIDE;
 145                 break;
 146         case 0x01 ... 0x04:
 147         case 0x07 ... 0x0a:
 148                 /*
 149                  * These units are connected to the SPEs
 150                  */
 151                 if (pending.class > 2)
 152                         break;
 153                 irq = IIC_SPE_OFFSET
 154                         + pending.class * IIC_CLASS_STRIDE
 155                         + node * IIC_NODE_STRIDE
 156                         + unit;
 157                 break;
 158         }
 159         if (irq == -1)
 160                 printk(KERN_WARNING "Unexpected interrupt class %02x, "
 161                         "source %02x, prio %02x, cpu %02x\n", pending.class,
 162                         pending.source, pending.prio, smp_processor_id());
 163         return irq;
 164 }
 165
 166 /* Get an IRQ number from the pending state register of the IIC */
 167 int iic_get_irq(struct pt_regs *regs)
 168 {
 169         struct iic *iic;
 170         int irq;
 171         struct iic_pending_bits pending;
 172
 173         iic = &__get_cpu_var(iic);
 174         *(unsigned long *) &pending =
 175                 in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
 176
 177         irq = -1;
 178         if (pending.flags & IIC_VALID) {
 179                 if (pending.flags & IIC_IPI) {
 180                         irq = IIC_IPI_OFFSET + (pending.prio >> 4);
 181 /*
 182                         if (irq > 0x80)
 183                                 printk(KERN_WARNING "Unexpected IPI prio %02x"
 184                                         "on CPU %02x\n", pending.prio,
 185                                                         smp_processor_id());
 186 */
 187                 } else {
 188                         irq = iic_external_get_irq(pending);
 189                 }
 190         }
 191         return irq;
 192 }
 193
 194 /* hardcoded part to be compatible with older firmware */
 195
 196 static int setup_iic_hardcoded(void)
 197 {
 198         struct device_node *np;
 199         int nodeid, cpu;
 200         unsigned long regs;
 201         struct iic *iic;
 202
 203         for_each_cpu(cpu) {
 204                 iic = &per_cpu(iic, cpu);
 205                 nodeid = cpu/2;
 206
 207                 for (np = of_find_node_by_type(NULL, "cpu");
 208                      np;
 209                      np = of_find_node_by_type(np, "cpu")) {
 210                         if (nodeid == *(int *)get_property(np, "node-id", NULL))
 211                                 break;
 212                         }
 213
 214                 if (!np) {
 215                         printk(KERN_WARNING "IIC: CPU %d not found\n", cpu);
 216                         iic->regs = NULL;
 217                         iic->target_id = 0xff;
 218                         return -ENODEV;
 219                         }
 220
 221                 regs = *(long *)get_property(np, "iic", NULL);
 222
 223                 /* hack until we have decided on the devtree info */
 224                 regs += 0x400;
 225                 if (cpu & 1)
 226                         regs += 0x20;
 227
 228                 printk(KERN_INFO "IIC for CPU %d at %lx\n", cpu, regs);
 229                 iic->regs = __ioremap(regs, sizeof(struct iic_regs),
 230                                       _PAGE_NO_CACHE);
 231
 232                 iic->target_id = (nodeid << 4) + ((cpu & 1) ? 0xf : 0xe);
 233         }
 234
 235         return 0;
 236 }
 237
 238 static int setup_iic(void)
 239 {
 240         struct device_node *dn;
 241         unsigned long *regs;
 242         char *compatible;
 243         unsigned *np, found = 0;
 244         struct iic *iic = NULL;
 245
 246         for (dn = NULL; (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
 247                 compatible = (char *)get_property(dn, "compatible", NULL);
 248
 249                 if (!compatible) {
 250                         printk(KERN_WARNING "no compatible property found !\n");
 251                         continue;
 252                 }
 253
 254                 if (strstr(compatible, "IBM,CBEA-Internal-Interrupt-Controller"))
 255                         regs = (unsigned long *)get_property(dn,"reg", NULL);
 256                 else
 257                         continue;
 258
 259                 if (!regs)
 260                         printk(KERN_WARNING "IIC: no reg property\n");
 261
 262                 np = (unsigned int *)get_property(dn, "ibm,interrupt-server-ranges", NULL);
 263
 264                 if (!np) {
 265                         printk(KERN_WARNING "IIC: CPU association not found\n");
 266                         iic->regs = NULL;
 267                         iic->target_id = 0xff;
 268                         return -ENODEV;
 269                 }
 270
 271                 iic = &per_cpu(iic, np[0]);
 272                 iic->regs = __ioremap(regs[0], sizeof(struct iic_regs),
 273                                       _PAGE_NO_CACHE);
 274                 iic->target_id = ((np[0] & 2) << 3) + ((np[0] & 1) ? 0xf : 0xe);
 275                 printk("IIC for CPU %d at %lx mapped to %p\n", np[0], regs[0], iic->regs);
 276
 277                 iic = &per_cpu(iic, np[1]);
 278                 iic->regs = __ioremap(regs[2], sizeof(struct iic_regs),
 279                                       _PAGE_NO_CACHE);
 280                 iic->target_id = ((np[1] & 2) << 3) + ((np[1] & 1) ? 0xf : 0xe);
 281                 printk("IIC for CPU %d at %lx mapped to %p\n", np[1], regs[2], iic->regs);
 282
 283                 found++;
 284         }
 285
 286         if (found)
 287                 return 0;
 288         else
 289                 return -ENODEV;
 290 }
 291
 292 #ifdef CONFIG_SMP
 293
 294 /* Use the highest interrupt priorities for IPI */
 295 static inline int iic_ipi_to_irq(int ipi)
 296 {
 297         return IIC_IPI_OFFSET + IIC_NUM_IPIS - 1 - ipi;
 298 }
 299
 300 static inline int iic_irq_to_ipi(int irq)
 301 {
 302         return IIC_NUM_IPIS - 1 - (irq - IIC_IPI_OFFSET);
 303 }
 304
 305 void iic_setup_cpu(void)
 306 {
 307         out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
 308 }
 309
 310 void iic_cause_IPI(int cpu, int mesg)
 311 {
 312         out_be64(&per_cpu(iic, cpu).regs->generate, (IIC_NUM_IPIS - 1 - mesg) << 4);
 313 }
 314
 315 u8 iic_get_target_id(int cpu)
 316 {
 317         return per_cpu(iic, cpu).target_id;
 318 }
 319 EXPORT_SYMBOL_GPL(iic_get_target_id);
 320
 321 static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
 322 {
 323         smp_message_recv(iic_irq_to_ipi(irq), regs);
 324         return IRQ_HANDLED;
 325 }
 326
 327 static void iic_request_ipi(int ipi, const char *name)
 328 {
 329         int irq;
 330
 331         irq = iic_ipi_to_irq(ipi);
 332         /* IPIs are marked SA_INTERRUPT as they must run with irqs
 333          * disabled */
 334         get_irq_desc(irq)->handler = &iic_pic;
 335         get_irq_desc(irq)->status |= IRQ_PER_CPU;
 336         request_irq(irq, iic_ipi_action, SA_INTERRUPT, name, NULL);
 337 }
 338
 339 void iic_request_IPIs(void)
 340 {
 341         iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
 342         iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
 343 #ifdef CONFIG_DEBUGGER
 344         iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
 345 #endif /* CONFIG_DEBUGGER */
 346 }
 347 #endif /* CONFIG_SMP */
 348
 349 static void iic_setup_spe_handlers(void)
 350 {
 351         int be, isrc;
 352
 353         /* Assume two threads per BE are present */
 354         for (be=0; be < num_present_cpus() / 2; be++) {
 355                 for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) {
 356                         int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc;
 357                         get_irq_desc(irq)->handler = &iic_pic;
 358                 }
 359         }
 360 }
 361
 362 void iic_init_IRQ(void)
 363 {
 364         int cpu, irq_offset;
 365         struct iic *iic;
 366
 367         if (setup_iic() < 0)
 368                 setup_iic_hardcoded();
 369
 370         irq_offset = 0;
 371         for_each_cpu(cpu) {
 372                 iic = &per_cpu(iic, cpu);
 373                 if (iic->regs)
 374                         out_be64(&iic->regs->prio, 0xff);
 375         }
 376         iic_setup_spe_handlers();
 377 }