2 * Copyright (C) 2006-2010, 2012 Freescale Semiconductor, Inc.
5 * Author: Andy Fleming <afleming@freescale.com>
7 * Based on 83xx/mpc8360e_pb.c by:
8 * Li Yang <LeoLi@freescale.com>
9 * Yin Olivia <Hong-hua.Yin@freescale.com>
12 * MPC85xx MDS board specific routines.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
20 #include <linux/stddef.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/reboot.h>
25 #include <linux/pci.h>
26 #include <linux/kdev_t.h>
27 #include <linux/major.h>
28 #include <linux/console.h>
29 #include <linux/delay.h>
30 #include <linux/seq_file.h>
31 #include <linux/initrd.h>
32 #include <linux/fsl_devices.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_device.h>
35 #include <linux/phy.h>
36 #include <linux/memblock.h>
38 #include <linux/atomic.h>
41 #include <asm/machdep.h>
42 #include <asm/pci-bridge.h>
44 #include <mm/mmu_decl.h>
47 #include <sysdev/fsl_soc.h>
48 #include <sysdev/fsl_pci.h>
49 #include <sysdev/simple_gpio.h>
51 #include <asm/qe_ic.h>
53 #include <asm/swiotlb.h>
54 #include <asm/fsl_guts.h>
61 #define DBG(fmt...) udbg_printf(fmt)
66 #define MV88E1111_SCR 0x10
67 #define MV88E1111_SCR_125CLK 0x0010
68 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
73 /* Workaround for the 125 CLK Toggle */
74 scr = phy_read(phydev, MV88E1111_SCR);
79 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
84 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
89 scr = phy_read(phydev, MV88E1111_SCR);
94 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
99 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
105 err = phy_write(phydev,29, 0x0006);
110 temp = phy_read(phydev, 30);
115 temp = (temp & (~0x8000)) | 0x4000;
116 err = phy_write(phydev,30, temp);
121 err = phy_write(phydev,29, 0x000a);
126 temp = phy_read(phydev, 30);
131 temp = phy_read(phydev, 30);
138 err = phy_write(phydev,30,temp);
143 /* Disable automatic MDI/MDIX selection */
144 temp = phy_read(phydev, 16);
150 err = phy_write(phydev,16,temp);
155 /* ************************************************************************
157 * Setup the architecture
160 #ifdef CONFIG_QUICC_ENGINE
161 static void __init mpc85xx_mds_reset_ucc_phys(void)
163 struct device_node *np;
164 static u8 __iomem *bcsr_regs;
167 np = of_find_node_by_name(NULL, "bcsr");
171 bcsr_regs = of_iomap(np, 0);
176 if (machine_is(mpc8568_mds)) {
177 #define BCSR_UCC1_GETH_EN (0x1 << 7)
178 #define BCSR_UCC2_GETH_EN (0x1 << 7)
179 #define BCSR_UCC1_MODE_MSK (0x3 << 4)
180 #define BCSR_UCC2_MODE_MSK (0x3 << 0)
182 /* Turn off UCC1 & UCC2 */
183 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
184 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
186 /* Mode is RGMII, all bits clear */
187 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
190 /* Turn UCC1 & UCC2 on */
191 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
192 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
193 } else if (machine_is(mpc8569_mds)) {
194 #define BCSR7_UCC12_GETHnRST (0x1 << 2)
195 #define BCSR8_UEM_MARVELL_RST (0x1 << 1)
196 #define BCSR_UCC_RGMII (0x1 << 6)
197 #define BCSR_UCC_RTBI (0x1 << 5)
199 * U-Boot mangles interrupt polarity for Marvell PHYs,
200 * so reset built-in and UEM Marvell PHYs, this puts
201 * the PHYs into their normal state.
203 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
204 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
206 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
207 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
209 for (np = NULL; (np = of_find_compatible_node(np,
211 "ucc_geth")) != NULL;) {
212 const unsigned int *prop;
215 prop = of_get_property(np, "cell-index", NULL);
221 prop = of_get_property(np, "phy-connection-type", NULL);
225 if (strcmp("rtbi", (const char *)prop) == 0)
226 clrsetbits_8(&bcsr_regs[7 + ucc_num],
227 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
229 } else if (machine_is(p1021_mds)) {
230 #define BCSR11_ENET_MICRST (0x1 << 5)
231 /* Reset Micrel PHY */
232 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
233 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
239 static void __init mpc85xx_mds_qe_init(void)
241 struct device_node *np;
243 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
245 np = of_find_node_by_name(NULL, "qe");
250 if (!of_device_is_available(np)) {
258 np = of_find_node_by_name(NULL, "par_io");
260 struct device_node *ucc;
265 for_each_node_by_name(ucc, "ucc")
266 par_io_of_config(ucc);
269 mpc85xx_mds_reset_ucc_phys();
271 if (machine_is(p1021_mds)) {
273 struct ccsr_guts __iomem *guts;
275 np = of_find_node_by_name(NULL, "global-utilities");
277 guts = of_iomap(np, 0);
279 pr_err("mpc85xx-rdb: could not map global utilities register\n");
281 /* P1021 has pins muxed for QE and other functions. To
282 * enable QE UEC mode, we need to set bit QE0 for UCC1
283 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
284 * and QE12 for QE MII management signals in PMUXCR
287 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
288 MPC85xx_PMUXCR_QE(3) |
289 MPC85xx_PMUXCR_QE(9) |
290 MPC85xx_PMUXCR_QE(12));
299 static void __init mpc85xx_mds_qeic_init(void)
301 struct device_node *np;
303 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
304 if (!of_device_is_available(np)) {
309 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
311 np = of_find_node_by_type(NULL, "qeic");
316 if (machine_is(p1021_mds))
317 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
318 qe_ic_cascade_high_mpic);
320 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
324 static void __init mpc85xx_mds_qe_init(void) { }
325 static void __init mpc85xx_mds_qeic_init(void) { }
326 #endif /* CONFIG_QUICC_ENGINE */
328 static void __init mpc85xx_mds_setup_arch(void)
331 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
335 mpc85xx_mds_qe_init();
337 fsl_pci_assign_primary();
343 static int __init board_fixups(void)
346 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
347 struct device_node *mdio;
351 for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
352 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
354 of_address_to_resource(mdio, 0, &res);
355 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
356 (unsigned long long)res.start, 1);
358 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
359 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
361 /* Register a workaround for errata */
362 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
363 (unsigned long long)res.start, 7);
364 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
371 machine_arch_initcall(mpc8568_mds, board_fixups);
372 machine_arch_initcall(mpc8569_mds, board_fixups);
374 static int __init mpc85xx_publish_devices(void)
376 if (machine_is(mpc8568_mds))
377 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
378 if (machine_is(mpc8569_mds))
379 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
381 return mpc85xx_common_publish_devices();
384 machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
385 machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
386 machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
388 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
389 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
390 machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
392 static void __init mpc85xx_mds_pic_init(void)
394 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
395 MPIC_SINGLE_DEST_CPU,
396 0, 256, " OpenPIC ");
397 BUG_ON(mpic == NULL);
400 mpc85xx_mds_qeic_init();
403 static int __init mpc85xx_mds_probe(void)
405 unsigned long root = of_get_flat_dt_root();
407 return of_flat_dt_is_compatible(root, "MPC85xxMDS");
410 define_machine(mpc8568_mds) {
411 .name = "MPC8568 MDS",
412 .probe = mpc85xx_mds_probe,
413 .setup_arch = mpc85xx_mds_setup_arch,
414 .init_IRQ = mpc85xx_mds_pic_init,
415 .get_irq = mpic_get_irq,
416 .restart = fsl_rstcr_restart,
417 .calibrate_decr = generic_calibrate_decr,
418 .progress = udbg_progress,
420 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
424 static int __init mpc8569_mds_probe(void)
426 unsigned long root = of_get_flat_dt_root();
428 return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
431 define_machine(mpc8569_mds) {
432 .name = "MPC8569 MDS",
433 .probe = mpc8569_mds_probe,
434 .setup_arch = mpc85xx_mds_setup_arch,
435 .init_IRQ = mpc85xx_mds_pic_init,
436 .get_irq = mpic_get_irq,
437 .restart = fsl_rstcr_restart,
438 .calibrate_decr = generic_calibrate_decr,
439 .progress = udbg_progress,
441 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
445 static int __init p1021_mds_probe(void)
447 unsigned long root = of_get_flat_dt_root();
449 return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
453 define_machine(p1021_mds) {
455 .probe = p1021_mds_probe,
456 .setup_arch = mpc85xx_mds_setup_arch,
457 .init_IRQ = mpc85xx_mds_pic_init,
458 .get_irq = mpic_get_irq,
459 .restart = fsl_rstcr_restart,
460 .calibrate_decr = generic_calibrate_decr,
461 .progress = udbg_progress,
463 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,