2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
33 #include <asm/firmware.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only = 1;
43 int pci_assign_all_buses = 0;
45 static void fixup_resource(struct resource *res, struct pci_dev *dev);
46 static void do_bus_setup(struct pci_bus *bus);
47 static void phbs_remap_io(void);
49 /* pci_io_base -- the base address from which io bars are offsets.
50 * This is the lowest I/O base address (so bar values are always positive),
51 * and it *must* be the start of ISA space if an ISA bus exists because
52 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
53 * page is mapped and isa_io_limit prevents access to it.
55 unsigned long isa_io_base; /* NULL if no ISA bus */
56 EXPORT_SYMBOL(isa_io_base);
57 unsigned long pci_io_base;
58 EXPORT_SYMBOL(pci_io_base);
60 void iSeries_pcibios_init(void);
64 struct dma_mapping_ops *pci_dma_ops;
65 EXPORT_SYMBOL(pci_dma_ops);
67 int global_phb_number; /* Global phb counter */
69 /* Cached ISA bridge dev. */
70 struct pci_dev *ppc64_isabridge_dev = NULL;
71 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev);
73 void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
75 pci_dma_ops = dma_ops;
78 static void fixup_broken_pcnet32(struct pci_dev* dev)
80 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
81 dev->vendor = PCI_VENDOR_ID_AMD;
82 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
85 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
87 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
90 unsigned long offset = 0;
91 struct pci_controller *hose = pci_bus_to_host(dev->bus);
96 if (res->flags & IORESOURCE_IO)
97 offset = (unsigned long)hose->io_base_virt - pci_io_base;
99 if (res->flags & IORESOURCE_MEM)
100 offset = hose->pci_mem_offset;
102 region->start = res->start - offset;
103 region->end = res->end - offset;
106 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
107 struct pci_bus_region *region)
109 unsigned long offset = 0;
110 struct pci_controller *hose = pci_bus_to_host(dev->bus);
115 if (res->flags & IORESOURCE_IO)
116 offset = (unsigned long)hose->io_base_virt - pci_io_base;
118 if (res->flags & IORESOURCE_MEM)
119 offset = hose->pci_mem_offset;
121 res->start = region->start + offset;
122 res->end = region->end + offset;
125 #ifdef CONFIG_HOTPLUG
126 EXPORT_SYMBOL(pcibios_resource_to_bus);
127 EXPORT_SYMBOL(pcibios_bus_to_resource);
131 * We need to avoid collisions with `mirrored' VGA ports
132 * and other strange ISA hardware, so we always want the
133 * addresses to be allocated in the 0x000-0x0ff region
136 * Why? Because some silly external IO cards only decode
137 * the low 10 bits of the IO address. The 0x00-0xff region
138 * is reserved for motherboard devices that decode all 16
139 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
140 * but we want to try to avoid allocating at 0x2900-0x2bff
141 * which might have be mirrored at 0x0100-0x03ff..
143 void pcibios_align_resource(void *data, struct resource *res,
144 resource_size_t size, resource_size_t align)
146 struct pci_dev *dev = data;
147 struct pci_controller *hose = pci_bus_to_host(dev->bus);
148 resource_size_t start = res->start;
149 unsigned long alignto;
151 if (res->flags & IORESOURCE_IO) {
152 unsigned long offset = (unsigned long)hose->io_base_virt -
154 /* Make sure we start at our min on all hoses */
155 if (start - offset < PCIBIOS_MIN_IO)
156 start = PCIBIOS_MIN_IO + offset;
159 * Put everything into 0x00-0xff region modulo 0x400
162 start = (start + 0x3ff) & ~0x3ff;
164 } else if (res->flags & IORESOURCE_MEM) {
165 /* Make sure we start at our min on all hoses */
166 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
167 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
169 /* Align to multiple of size of minimum base. */
170 alignto = max(0x1000UL, align);
171 start = ALIGN(start, alignto);
177 static DEFINE_SPINLOCK(hose_spinlock);
180 * pci_controller(phb) initialized common variables.
182 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
184 memset(hose, 0, sizeof(struct pci_controller));
186 spin_lock(&hose_spinlock);
187 hose->global_number = global_phb_number++;
188 list_add_tail(&hose->list_node, &hose_list);
189 spin_unlock(&hose_spinlock);
192 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
194 struct pci_controller *phb;
197 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
199 phb = alloc_bootmem(sizeof (struct pci_controller));
202 pci_setup_pci_controller(phb);
203 phb->arch_data = dev;
204 phb->is_dynamic = mem_init_done;
206 int nid = of_node_to_nid(dev);
208 if (nid < 0 || !node_online(nid))
211 PHB_SET_NODE(phb, nid);
216 void pcibios_free_controller(struct pci_controller *phb)
218 spin_lock(&hose_spinlock);
219 list_del(&phb->list_node);
220 spin_unlock(&hose_spinlock);
226 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
229 struct pci_bus *child_bus;
231 list_for_each_entry(dev, &b->devices, bus_list) {
234 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
235 struct resource *r = &dev->resource[i];
237 if (r->parent || !r->start || !r->flags)
239 pci_claim_resource(dev, i);
243 list_for_each_entry(child_bus, &b->children, node)
244 pcibios_claim_one_bus(child_bus);
246 #ifdef CONFIG_HOTPLUG
247 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
250 static void __init pcibios_claim_of_setup(void)
254 if (firmware_has_feature(FW_FEATURE_ISERIES))
257 list_for_each_entry(b, &pci_root_buses, node)
258 pcibios_claim_one_bus(b);
261 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
266 prop = get_property(np, name, &len);
267 if (prop && len >= 4)
272 static unsigned int pci_parse_of_flags(u32 addr0)
274 unsigned int flags = 0;
276 if (addr0 & 0x02000000) {
277 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
278 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
279 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
280 if (addr0 & 0x40000000)
281 flags |= IORESOURCE_PREFETCH
282 | PCI_BASE_ADDRESS_MEM_PREFETCH;
283 } else if (addr0 & 0x01000000)
284 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
288 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
290 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
294 struct resource *res;
299 addrs = get_property(node, "assigned-addresses", &proplen);
302 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
303 for (; proplen >= 20; proplen -= 20, addrs += 5) {
304 flags = pci_parse_of_flags(addrs[0]);
307 base = GET_64BIT(addrs, 1);
308 size = GET_64BIT(addrs, 3);
312 DBG(" base: %llx, size: %llx, i: %x\n",
313 (unsigned long long)base, (unsigned long long)size, i);
315 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
316 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
317 } else if (i == dev->rom_base_reg) {
318 res = &dev->resource[PCI_ROM_RESOURCE];
319 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
321 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
325 res->end = base + size - 1;
327 res->name = pci_name(dev);
328 fixup_resource(res, dev);
332 struct pci_dev *of_create_pci_dev(struct device_node *node,
333 struct pci_bus *bus, int devfn)
338 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
341 type = get_property(node, "device_type", NULL);
345 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
349 dev->dev.parent = bus->bridge;
350 dev->dev.bus = &pci_bus_type;
352 dev->multifunction = 0; /* maybe a lie? */
354 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
355 dev->device = get_int_prop(node, "device-id", 0xffff);
356 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
357 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
359 dev->cfg_size = pci_cfg_space_size(dev);
361 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
362 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
363 dev->class = get_int_prop(node, "class-code", 0);
365 DBG(" class: 0x%x\n", dev->class);
367 dev->current_state = 4; /* unknown power state */
368 dev->error_state = pci_channel_io_normal;
370 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
371 /* a PCI-PCI bridge */
372 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
373 dev->rom_base_reg = PCI_ROM_ADDRESS1;
374 } else if (!strcmp(type, "cardbus")) {
375 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
377 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
378 dev->rom_base_reg = PCI_ROM_ADDRESS;
379 /* Maybe do a default OF mapping here */
383 pci_parse_of_addrs(node, dev);
385 DBG(" adding to system ...\n");
387 pci_device_add(dev, bus);
391 EXPORT_SYMBOL(of_create_pci_dev);
393 void __devinit of_scan_bus(struct device_node *node,
396 struct device_node *child = NULL;
401 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
403 while ((child = of_get_next_child(node, child)) != NULL) {
404 DBG(" * %s\n", child->full_name);
405 reg = get_property(child, "reg", ®len);
406 if (reg == NULL || reglen < 20)
408 devfn = (reg[0] >> 8) & 0xff;
410 /* create a new pci_dev for this device */
411 dev = of_create_pci_dev(child, bus, devfn);
414 DBG("dev header type: %x\n", dev->hdr_type);
416 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
417 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
418 of_scan_pci_bridge(child, dev);
423 EXPORT_SYMBOL(of_scan_bus);
425 void __devinit of_scan_pci_bridge(struct device_node *node,
429 const u32 *busrange, *ranges;
431 struct resource *res;
435 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
437 /* parse bus-range property */
438 busrange = get_property(node, "bus-range", &len);
439 if (busrange == NULL || len != 8) {
440 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
444 ranges = get_property(node, "ranges", &len);
445 if (ranges == NULL) {
446 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
451 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
453 printk(KERN_ERR "Failed to create pci bus for %s\n",
458 bus->primary = dev->bus->number;
459 bus->subordinate = busrange[1];
463 /* parse ranges property */
464 /* PCI #address-cells == 3 and #size-cells == 2 always */
465 res = &dev->resource[PCI_BRIDGE_RESOURCES];
466 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
468 bus->resource[i] = res;
472 for (; len >= 32; len -= 32, ranges += 8) {
473 flags = pci_parse_of_flags(ranges[0]);
474 size = GET_64BIT(ranges, 6);
475 if (flags == 0 || size == 0)
477 if (flags & IORESOURCE_IO) {
478 res = bus->resource[0];
480 printk(KERN_ERR "PCI: ignoring extra I/O range"
481 " for bridge %s\n", node->full_name);
485 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
486 printk(KERN_ERR "PCI: too many memory ranges"
487 " for bridge %s\n", node->full_name);
490 res = bus->resource[i];
493 res->start = GET_64BIT(ranges, 1);
494 res->end = res->start + size - 1;
496 fixup_resource(res, dev);
498 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
500 DBG(" bus name: %s\n", bus->name);
502 mode = PCI_PROBE_NORMAL;
503 if (ppc_md.pci_probe_mode)
504 mode = ppc_md.pci_probe_mode(bus);
505 DBG(" probe mode: %d\n", mode);
507 if (mode == PCI_PROBE_DEVTREE)
508 of_scan_bus(node, bus);
509 else if (mode == PCI_PROBE_NORMAL)
510 pci_scan_child_bus(bus);
512 EXPORT_SYMBOL(of_scan_pci_bridge);
514 void __devinit scan_phb(struct pci_controller *hose)
517 struct device_node *node = hose->arch_data;
519 struct resource *res;
521 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
523 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
525 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
526 hose->global_number);
529 bus->secondary = hose->first_busno;
532 bus->resource[0] = res = &hose->io_resource;
533 if (res->flags && request_resource(&ioport_resource, res))
534 printk(KERN_ERR "Failed to request PCI IO region "
535 "on PCI domain %04x\n", hose->global_number);
537 for (i = 0; i < 3; ++i) {
538 res = &hose->mem_resources[i];
539 bus->resource[i+1] = res;
540 if (res->flags && request_resource(&iomem_resource, res))
541 printk(KERN_ERR "Failed to request PCI memory region "
542 "on PCI domain %04x\n", hose->global_number);
545 mode = PCI_PROBE_NORMAL;
547 if (node && ppc_md.pci_probe_mode)
548 mode = ppc_md.pci_probe_mode(bus);
549 DBG(" probe mode: %d\n", mode);
550 if (mode == PCI_PROBE_DEVTREE) {
551 bus->subordinate = hose->last_busno;
552 of_scan_bus(node, bus);
555 if (mode == PCI_PROBE_NORMAL)
556 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
559 static int __init pcibios_init(void)
561 struct pci_controller *hose, *tmp;
563 /* For now, override phys_mem_access_prot. If we need it,
564 * later, we may move that initialization to each ppc_md
566 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
568 if (firmware_has_feature(FW_FEATURE_ISERIES))
569 iSeries_pcibios_init();
571 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
573 /* Scan all of the recorded PCI controllers. */
574 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
576 pci_bus_add_devices(hose->bus);
579 if (!firmware_has_feature(FW_FEATURE_ISERIES)) {
581 pcibios_claim_of_setup();
583 /* FIXME: `else' will be removed when
584 pci_assign_unassigned_resources() is able to work
585 correctly with [partially] allocated PCI tree. */
586 pci_assign_unassigned_resources();
589 /* Call machine dependent final fixup */
590 if (ppc_md.pcibios_fixup)
591 ppc_md.pcibios_fixup();
593 /* Cache the location of the ISA bridge (if we have one) */
594 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
595 if (ppc64_isabridge_dev != NULL)
596 printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
598 if (!firmware_has_feature(FW_FEATURE_ISERIES))
599 /* map in PCI I/O space */
602 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
607 subsys_initcall(pcibios_init);
609 char __init *pcibios_setup(char *str)
614 int pcibios_enable_device(struct pci_dev *dev, int mask)
619 pci_read_config_word(dev, PCI_COMMAND, &cmd);
622 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
623 struct resource *res = &dev->resource[i];
625 /* Only set up the requested stuff */
626 if (!(mask & (1<<i)))
629 if (res->flags & IORESOURCE_IO)
630 cmd |= PCI_COMMAND_IO;
631 if (res->flags & IORESOURCE_MEM)
632 cmd |= PCI_COMMAND_MEMORY;
636 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
638 /* Enable the appropriate bits in the PCI command register. */
639 pci_write_config_word(dev, PCI_COMMAND, cmd);
645 * Return the domain number for this bus.
647 int pci_domain_nr(struct pci_bus *bus)
649 if (firmware_has_feature(FW_FEATURE_ISERIES))
652 struct pci_controller *hose = pci_bus_to_host(bus);
654 return hose->global_number;
658 EXPORT_SYMBOL(pci_domain_nr);
660 /* Decide whether to display the domain number in /proc */
661 int pci_proc_domain(struct pci_bus *bus)
663 if (firmware_has_feature(FW_FEATURE_ISERIES))
666 struct pci_controller *hose = pci_bus_to_host(bus);
672 * Platform support for /proc/bus/pci/X/Y mmap()s,
673 * modelled on the sparc64 implementation by Dave Miller.
678 * Adjust vm_pgoff of VMA such that it is the physical page offset
679 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
681 * Basically, the user finds the base address for his device which he wishes
682 * to mmap. They read the 32-bit value from the config space base register,
683 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
684 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
686 * Returns negative error code on failure, zero on success.
688 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
689 resource_size_t *offset,
690 enum pci_mmap_state mmap_state)
692 struct pci_controller *hose = pci_bus_to_host(dev->bus);
693 unsigned long io_offset = 0;
697 return NULL; /* should never happen */
699 /* If memory, add on the PCI bridge address offset */
700 if (mmap_state == pci_mmap_mem) {
701 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
702 *offset += hose->pci_mem_offset;
704 res_bit = IORESOURCE_MEM;
706 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
707 *offset += io_offset;
708 res_bit = IORESOURCE_IO;
712 * Check that the offset requested corresponds to one of the
713 * resources of the device.
715 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
716 struct resource *rp = &dev->resource[i];
717 int flags = rp->flags;
719 /* treat ROM as memory (should be already) */
720 if (i == PCI_ROM_RESOURCE)
721 flags |= IORESOURCE_MEM;
723 /* Active and same type? */
724 if ((flags & res_bit) == 0)
727 /* In the range of this resource? */
728 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
731 /* found it! construct the final physical address */
732 if (mmap_state == pci_mmap_io)
733 *offset += hose->io_base_phys - io_offset;
741 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
744 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
746 enum pci_mmap_state mmap_state,
749 unsigned long prot = pgprot_val(protection);
751 /* Write combine is always 0 on non-memory space mappings. On
752 * memory space, if the user didn't pass 1, we check for a
753 * "prefetchable" resource. This is a bit hackish, but we use
754 * this to workaround the inability of /sysfs to provide a write
757 if (mmap_state != pci_mmap_mem)
759 else if (write_combine == 0) {
760 if (rp->flags & IORESOURCE_PREFETCH)
764 /* XXX would be nice to have a way to ask for write-through */
765 prot |= _PAGE_NO_CACHE;
767 prot &= ~_PAGE_GUARDED;
769 prot |= _PAGE_GUARDED;
771 return __pgprot(prot);
775 * This one is used by /dev/mem and fbdev who have no clue about the
776 * PCI device, it tries to find the PCI device first and calls the
779 pgprot_t pci_phys_mem_access_prot(struct file *file,
784 struct pci_dev *pdev = NULL;
785 struct resource *found = NULL;
786 unsigned long prot = pgprot_val(protection);
787 unsigned long offset = pfn << PAGE_SHIFT;
790 if (page_is_ram(pfn))
791 return __pgprot(prot);
793 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
795 for_each_pci_dev(pdev) {
796 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
797 struct resource *rp = &pdev->resource[i];
798 int flags = rp->flags;
800 /* Active and same type? */
801 if ((flags & IORESOURCE_MEM) == 0)
803 /* In the range of this resource? */
804 if (offset < (rp->start & PAGE_MASK) ||
814 if (found->flags & IORESOURCE_PREFETCH)
815 prot &= ~_PAGE_GUARDED;
819 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
821 return __pgprot(prot);
826 * Perform the actual remap of the pages for a PCI device mapping, as
827 * appropriate for this architecture. The region in the process to map
828 * is described by vm_start and vm_end members of VMA, the base physical
829 * address is found in vm_pgoff.
830 * The pci device structure is provided so that architectures may make mapping
831 * decisions on a per-device or per-bus basis.
833 * Returns a negative error code on failure, zero on success.
835 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
836 enum pci_mmap_state mmap_state, int write_combine)
838 resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT;
842 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
846 vma->vm_pgoff = offset >> PAGE_SHIFT;
847 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
849 mmap_state, write_combine);
851 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
852 vma->vm_end - vma->vm_start, vma->vm_page_prot);
857 static ssize_t pci_show_devspec(struct device *dev,
858 struct device_attribute *attr, char *buf)
860 struct pci_dev *pdev;
861 struct device_node *np;
863 pdev = to_pci_dev (dev);
864 np = pci_device_to_OF_node(pdev);
865 if (np == NULL || np->full_name == NULL)
867 return sprintf(buf, "%s", np->full_name);
869 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
871 void pcibios_add_platform_entries(struct pci_dev *pdev)
873 device_create_file(&pdev->dev, &dev_attr_devspec);
876 #define ISA_SPACE_MASK 0x1
877 #define ISA_SPACE_IO 0x1
879 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
880 unsigned long phb_io_base_phys,
881 void __iomem * phb_io_base_virt)
883 /* Remove these asap */
897 struct isa_address isa_addr;
898 struct pci_address pci_addr;
902 const struct isa_range *range;
903 unsigned long pci_addr;
904 unsigned int isa_addr;
908 range = get_property(isa_node, "ranges", &rlen);
909 if (range == NULL || (rlen < sizeof(struct isa_range))) {
910 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
912 __ioremap_explicit(phb_io_base_phys,
913 (unsigned long)phb_io_base_virt,
914 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
918 /* From "ISA Binding to 1275"
919 * The ranges property is laid out as an array of elements,
920 * each of which comprises:
921 * cells 0 - 1: an ISA address
922 * cells 2 - 4: a PCI address
923 * (size depending on dev->n_addr_cells)
924 * cell 5: the size of the range
926 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
927 isa_addr = range->isa_addr.a_lo;
928 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
929 range->pci_addr.a_lo;
931 /* Assume these are both zero */
932 if ((pci_addr != 0) || (isa_addr != 0)) {
933 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
938 size = PAGE_ALIGN(range->size);
940 __ioremap_explicit(phb_io_base_phys,
941 (unsigned long) phb_io_base_virt,
942 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
946 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
947 struct device_node *dev, int prim)
949 const unsigned int *ranges;
950 unsigned int pci_space;
954 struct resource *res;
955 int np, na = prom_n_addr_cells(dev);
956 unsigned long pci_addr, cpu_phys_addr;
960 /* From "PCI Binding to 1275"
961 * The ranges property is laid out as an array of elements,
962 * each of which comprises:
963 * cells 0 - 2: a PCI address
964 * cells 3 or 3+4: a CPU physical address
965 * (size depending on dev->n_addr_cells)
966 * cells 4+5 or 5+6: the size of the range
968 ranges = get_property(dev, "ranges", &rlen);
971 hose->io_base_phys = 0;
972 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
974 pci_space = ranges[0];
975 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
976 cpu_phys_addr = of_translate_address(dev, &ranges[3]);
977 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
982 /* Now consume following elements while they are contiguous */
983 while (rlen >= np * sizeof(unsigned int)) {
984 unsigned long addr, phys;
986 if (ranges[0] != pci_space)
988 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
991 phys = (phys << 32) | ranges[4];
992 if (addr != pci_addr + size ||
993 phys != cpu_phys_addr + size)
996 size += ((unsigned long)ranges[na+3] << 32)
999 rlen -= np * sizeof(unsigned int);
1002 switch ((pci_space >> 24) & 0x3) {
1003 case 1: /* I/O space */
1004 hose->io_base_phys = cpu_phys_addr;
1005 hose->pci_io_size = size;
1007 res = &hose->io_resource;
1008 res->flags = IORESOURCE_IO;
1009 res->start = pci_addr;
1010 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1011 res->start, res->start + size - 1);
1013 case 2: /* memory space */
1015 while (memno < 3 && hose->mem_resources[memno].flags)
1019 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1021 res = &hose->mem_resources[memno];
1022 res->flags = IORESOURCE_MEM;
1023 res->start = cpu_phys_addr;
1024 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1025 res->start, res->start + size - 1);
1030 res->name = dev->full_name;
1031 res->end = res->start + size - 1;
1033 res->sibling = NULL;
1039 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1041 unsigned long size = hose->pci_io_size;
1042 unsigned long io_virt_offset;
1043 struct resource *res;
1044 struct device_node *isa_dn;
1046 hose->io_base_virt = reserve_phb_iospace(size);
1047 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1048 hose->global_number, hose->io_base_phys,
1049 (unsigned long) hose->io_base_virt);
1052 pci_io_base = (unsigned long)hose->io_base_virt;
1053 isa_dn = of_find_node_by_type(NULL, "isa");
1055 isa_io_base = pci_io_base;
1056 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1057 hose->io_base_virt);
1058 of_node_put(isa_dn);
1062 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1063 res = &hose->io_resource;
1064 res->start += io_virt_offset;
1065 res->end += io_virt_offset;
1068 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1071 unsigned long size = hose->pci_io_size;
1072 unsigned long io_virt_offset;
1073 struct resource *res;
1075 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
1076 _PAGE_NO_CACHE | _PAGE_GUARDED);
1077 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1078 hose->global_number, hose->io_base_phys,
1079 (unsigned long) hose->io_base_virt);
1082 pci_io_base = (unsigned long)hose->io_base_virt;
1084 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1085 res = &hose->io_resource;
1086 res->start += io_virt_offset;
1087 res->end += io_virt_offset;
1091 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1092 unsigned long *start_virt, unsigned long *size)
1094 struct pci_controller *hose = pci_bus_to_host(bus);
1095 struct pci_bus_region region;
1096 struct resource *res;
1099 res = bus->resource[0];
1100 pcibios_resource_to_bus(bus->self, ®ion, res);
1101 *start_phys = hose->io_base_phys + region.start;
1102 *start_virt = (unsigned long) hose->io_base_virt +
1104 if (region.end > region.start)
1105 *size = region.end - region.start + 1;
1107 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1108 __FUNCTION__, region.start, region.end);
1114 res = &hose->io_resource;
1115 *start_phys = hose->io_base_phys;
1116 *start_virt = (unsigned long) hose->io_base_virt;
1117 if (res->end > res->start)
1118 *size = res->end - res->start + 1;
1120 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1121 __FUNCTION__, res->start, res->end);
1129 int unmap_bus_range(struct pci_bus *bus)
1131 unsigned long start_phys;
1132 unsigned long start_virt;
1136 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1140 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1142 if (__iounmap_explicit((void __iomem *) start_virt, size))
1147 EXPORT_SYMBOL(unmap_bus_range);
1149 int remap_bus_range(struct pci_bus *bus)
1151 unsigned long start_phys;
1152 unsigned long start_virt;
1156 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1161 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1163 if (start_phys == 0)
1165 printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1166 if (__ioremap_explicit(start_phys, start_virt, size,
1167 _PAGE_NO_CACHE | _PAGE_GUARDED))
1172 EXPORT_SYMBOL(remap_bus_range);
1174 static void phbs_remap_io(void)
1176 struct pci_controller *hose, *tmp;
1178 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1179 remap_bus_range(hose->bus);
1182 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1184 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1185 unsigned long offset;
1187 if (res->flags & IORESOURCE_IO) {
1188 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1190 res->start += offset;
1192 } else if (res->flags & IORESOURCE_MEM) {
1193 res->start += hose->pci_mem_offset;
1194 res->end += hose->pci_mem_offset;
1198 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1199 struct pci_bus *bus)
1201 /* Update device resources. */
1204 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1205 if (dev->resource[i].flags)
1206 fixup_resource(&dev->resource[i], dev);
1208 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1210 void __devinit pcibios_setup_new_device(struct pci_dev *dev)
1212 struct dev_archdata *sd = &dev->dev.archdata;
1214 sd->of_node = pci_device_to_OF_node(dev);
1216 DBG("PCI device %s OF node: %s\n", pci_name(dev),
1217 sd->of_node ? sd->of_node->full_name : "<none>");
1219 sd->dma_ops = pci_dma_ops;
1221 sd->numa_node = pcibus_to_node(dev->bus);
1225 if (ppc_md.pci_dma_dev_setup)
1226 ppc_md.pci_dma_dev_setup(dev);
1228 EXPORT_SYMBOL(pcibios_setup_new_device);
1230 static void __devinit do_bus_setup(struct pci_bus *bus)
1232 struct pci_dev *dev;
1234 if (ppc_md.pci_dma_bus_setup)
1235 ppc_md.pci_dma_bus_setup(bus);
1237 list_for_each_entry(dev, &bus->devices, bus_list)
1238 pcibios_setup_new_device(dev);
1240 /* Read default IRQs and fixup if necessary */
1241 list_for_each_entry(dev, &bus->devices, bus_list) {
1242 pci_read_irq_line(dev);
1243 if (ppc_md.pci_irq_fixup)
1244 ppc_md.pci_irq_fixup(dev);
1248 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1250 struct pci_dev *dev = bus->self;
1251 struct device_node *np;
1253 np = pci_bus_to_OF_node(bus);
1255 DBG("pcibios_fixup_bus(%s)\n", np ? np->full_name : "<???>");
1257 if (dev && pci_probe_only &&
1258 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1259 /* This is a subordinate bridge */
1261 pci_read_bridge_bases(bus);
1262 pcibios_fixup_device_resources(dev, bus);
1267 if (!pci_probe_only)
1270 list_for_each_entry(dev, &bus->devices, bus_list)
1271 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1272 pcibios_fixup_device_resources(dev, bus);
1274 EXPORT_SYMBOL(pcibios_fixup_bus);
1277 * Reads the interrupt pin to determine if interrupt is use by card.
1278 * If the interrupt is used, then gets the interrupt line from the
1279 * openfirmware and sets it in the pci_dev and pci_config line.
1281 int pci_read_irq_line(struct pci_dev *pci_dev)
1286 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1289 memset(&oirq, 0xff, sizeof(oirq));
1291 /* Try to get a mapping from the device-tree */
1292 if (of_irq_map_pci(pci_dev, &oirq)) {
1295 /* If that fails, lets fallback to what is in the config
1296 * space and map that through the default controller. We
1297 * also set the type to level low since that's what PCI
1298 * interrupts are. If your platform does differently, then
1299 * either provide a proper interrupt tree or don't use this
1302 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
1306 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
1310 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
1312 virq = irq_create_mapping(NULL, line);
1314 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1316 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1317 oirq.size, oirq.specifier[0], oirq.specifier[1],
1318 oirq.controller->full_name);
1320 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1323 if(virq == NO_IRQ) {
1324 DBG(" -> failed to map !\n");
1328 DBG(" -> mapped to linux irq %d\n", virq);
1330 pci_dev->irq = virq;
1334 EXPORT_SYMBOL(pci_read_irq_line);
1336 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1337 const struct resource *rsrc,
1338 resource_size_t *start, resource_size_t *end)
1340 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1341 resource_size_t offset = 0;
1346 if (rsrc->flags & IORESOURCE_IO)
1347 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1349 /* We pass a fully fixed up address to userland for MMIO instead of
1350 * a BAR value because X is lame and expects to be able to use that
1351 * to pass to /dev/mem !
1353 * That means that we'll have potentially 64 bits values where some
1354 * userland apps only expect 32 (like X itself since it thinks only
1355 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
1358 * Hopefully, the sysfs insterface is immune to that gunk. Once X
1359 * has been fixed (and the fix spread enough), we can re-enable the
1360 * 2 lines below and pass down a BAR value to userland. In that case
1361 * we'll also have to re-enable the matching code in
1362 * __pci_mmap_make_offset().
1367 else if (rsrc->flags & IORESOURCE_MEM)
1368 offset = hose->pci_mem_offset;
1371 *start = rsrc->start - offset;
1372 *end = rsrc->end - offset;
1375 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
1380 struct pci_controller *hose, *tmp;
1381 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1382 if (hose->arch_data == node)
1384 node = node->parent;
1389 unsigned long pci_address_to_pio(phys_addr_t address)
1391 struct pci_controller *hose, *tmp;
1393 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1394 if (address >= hose->io_base_phys &&
1395 address < (hose->io_base_phys + hose->pci_io_size)) {
1396 unsigned long base =
1397 (unsigned long)hose->io_base_virt - pci_io_base;
1398 return base + (address - hose->io_base_phys);
1401 return (unsigned int)-1;
1403 EXPORT_SYMBOL_GPL(pci_address_to_pio);
1406 #define IOBASE_BRIDGE_NUMBER 0
1407 #define IOBASE_MEMORY 1
1409 #define IOBASE_ISA_IO 3
1410 #define IOBASE_ISA_MEM 4
1412 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1413 unsigned long in_devfn)
1415 struct pci_controller* hose;
1416 struct list_head *ln;
1417 struct pci_bus *bus = NULL;
1418 struct device_node *hose_node;
1420 /* Argh ! Please forgive me for that hack, but that's the
1421 * simplest way to get existing XFree to not lockup on some
1422 * G5 machines... So when something asks for bus 0 io base
1423 * (bus 0 is HT root), we return the AGP one instead.
1425 if (machine_is_compatible("MacRISC4"))
1429 /* That syscall isn't quite compatible with PCI domains, but it's
1430 * used on pre-domains setup. We return the first match
1433 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1434 bus = pci_bus_b(ln);
1435 if (in_bus >= bus->number && in_bus <= bus->subordinate)
1439 if (bus == NULL || bus->sysdata == NULL)
1442 hose_node = (struct device_node *)bus->sysdata;
1443 hose = PCI_DN(hose_node)->phb;
1446 case IOBASE_BRIDGE_NUMBER:
1447 return (long)hose->first_busno;
1449 return (long)hose->pci_mem_offset;
1451 return (long)hose->io_base_phys;
1453 return (long)isa_io_base;
1454 case IOBASE_ISA_MEM:
1462 int pcibus_to_node(struct pci_bus *bus)
1464 struct pci_controller *phb = pci_bus_to_host(bus);
1467 EXPORT_SYMBOL(pcibus_to_node);