3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
24 #include <linux/threads.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
37 #include <asm/page_64.h>
38 #include <asm/exception.h>
39 #include <asm/irqflags.h>
42 * We layout physical memory as follows:
43 * 0x0000 - 0x00ff : Secondary processor spin code
44 * 0x0100 - 0x2fff : pSeries Interrupt prologs
45 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
46 * 0x6000 - 0x6fff : Initial (CPU0) segment table
47 * 0x7000 - 0x7fff : FWNMI data area
48 * 0x8000 - : Early init and support code
56 * SPRG0 reserved for hypervisor
57 * SPRG1 temp - used to save gpr
58 * SPRG2 temp - used to save gpr
59 * SPRG3 virt addr of paca
63 * Entering into this code we make the following assumptions:
65 * 1. The MMU is off & open firmware is running in real mode.
66 * 2. The kernel is entered at __start
69 * 1. The MMU is on (as it always is for iSeries)
70 * 2. The kernel is entered at system_reset_iSeries
77 /* NOP this out unconditionally */
79 b .__start_initialization_multiplatform
82 /* Catch branch to 0 in real mode */
85 /* Secondary processors spin on this value until it goes to 1. */
86 .globl __secondary_hold_spinloop
87 __secondary_hold_spinloop:
90 /* Secondary processors write this value with their cpu # */
91 /* after they enter the spin loop immediately below. */
92 .globl __secondary_hold_acknowledge
93 __secondary_hold_acknowledge:
96 #ifdef CONFIG_PPC_ISERIES
98 * At offset 0x20, there is a pointer to iSeries LPAR data.
99 * This is required by the hypervisor
102 .llong hvReleaseData-KERNELBASE
103 #endif /* CONFIG_PPC_ISERIES */
107 * The following code is used to hold secondary processors
108 * in a spin loop after they have entered the kernel, but
109 * before the bulk of the kernel has been relocated. This code
110 * is relocated to physical address 0x60 before prom_init is run.
111 * All of it must fit below the first exception vector at 0x100.
113 _GLOBAL(__secondary_hold)
116 mtmsrd r24 /* RI on */
118 /* Grab our physical cpu number */
121 /* Tell the master cpu we're here */
122 /* Relocation is off & we are located at an address less */
123 /* than 0x100, so only need to grab low order offset. */
124 std r24,__secondary_hold_acknowledge@l(0)
127 /* All secondary cpus wait here until told to start. */
128 100: ld r4,__secondary_hold_spinloop@l(0)
132 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
133 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
141 /* This value is used to mark exception frames on the stack. */
144 .tc ID_72656773_68657265[TC],0x7265677368657265
148 * This is the start of the interrupt handlers for pSeries
149 * This code runs with relocation off.
152 .globl __start_interrupts
155 STD_EXCEPTION_PSERIES(0x100, system_reset)
158 _machine_check_pSeries:
160 mtspr SPRN_SPRG1,r13 /* save r13 */
161 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
164 .globl data_access_pSeries
173 rlwimi r13,r12,16,0x20
176 beq do_stab_bolted_pSeries
179 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
180 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
183 .globl data_access_slb_pSeries
184 data_access_slb_pSeries:
187 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
188 std r3,PACA_EXSLB+EX_R3(r13)
190 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
193 /* Keep that around for when we re-implement dynamic VSIDs */
195 bge slb_miss_user_pseries
196 #endif /* __DISABLED__ */
197 std r10,PACA_EXSLB+EX_R10(r13)
198 std r11,PACA_EXSLB+EX_R11(r13)
199 std r12,PACA_EXSLB+EX_R12(r13)
201 std r10,PACA_EXSLB+EX_R13(r13)
202 mfspr r12,SPRN_SRR1 /* and SRR1 */
203 b .slb_miss_realmode /* Rel. branch works in real mode */
205 STD_EXCEPTION_PSERIES(0x400, instruction_access)
208 .globl instruction_access_slb_pSeries
209 instruction_access_slb_pSeries:
212 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
213 std r3,PACA_EXSLB+EX_R3(r13)
214 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
215 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
218 /* Keep that around for when we re-implement dynamic VSIDs */
220 bge slb_miss_user_pseries
221 #endif /* __DISABLED__ */
222 std r10,PACA_EXSLB+EX_R10(r13)
223 std r11,PACA_EXSLB+EX_R11(r13)
224 std r12,PACA_EXSLB+EX_R12(r13)
226 std r10,PACA_EXSLB+EX_R13(r13)
227 mfspr r12,SPRN_SRR1 /* and SRR1 */
228 b .slb_miss_realmode /* Rel. branch works in real mode */
230 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
231 STD_EXCEPTION_PSERIES(0x600, alignment)
232 STD_EXCEPTION_PSERIES(0x700, program_check)
233 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
234 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
235 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
236 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
239 .globl system_call_pSeries
245 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
251 oris r12,r12,system_call_common@h
252 ori r12,r12,system_call_common@l
254 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
258 b . /* prevent speculative execution */
260 /* Fast LE/BE switch system call */
261 1: mfspr r12,SPRN_SRR1
264 rfid /* return to userspace */
267 STD_EXCEPTION_PSERIES(0xd00, single_step)
268 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
270 /* We need to deal with the Altivec unavailable exception
271 * here which is at 0xf20, thus in the middle of the
272 * prolog code of the PerformanceMonitor one. A little
273 * trickery is thus necessary
276 b performance_monitor_pSeries
278 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
280 #ifdef CONFIG_CBE_RAS
281 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
282 #endif /* CONFIG_CBE_RAS */
283 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
284 #ifdef CONFIG_CBE_RAS
285 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
286 #endif /* CONFIG_CBE_RAS */
287 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
288 #ifdef CONFIG_CBE_RAS
289 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
290 #endif /* CONFIG_CBE_RAS */
294 /*** pSeries interrupt support ***/
296 /* moved from 0xf00 */
297 STD_EXCEPTION_PSERIES(., performance_monitor)
300 * An interrupt came in while soft-disabled; clear EE in SRR1,
301 * clear paca->hard_enabled and return.
304 stb r10,PACAHARDIRQEN(r13)
306 ld r9,PACA_EXGEN+EX_R9(r13)
308 rldicl r10,r10,48,1 /* clear MSR_EE */
311 ld r10,PACA_EXGEN+EX_R10(r13)
317 do_stab_bolted_pSeries:
320 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
323 * We have some room here we use that to put
324 * the peries slb miss user trampoline code so it's reasonably
325 * away from slb_miss_user_common to avoid problems with rfid
327 * This is used for when the SLB miss handler has to go virtual,
328 * which doesn't happen for now anymore but will once we re-implement
329 * dynamic VSIDs for shared page tables
332 slb_miss_user_pseries:
333 std r10,PACA_EXGEN+EX_R10(r13)
334 std r11,PACA_EXGEN+EX_R11(r13)
335 std r12,PACA_EXGEN+EX_R12(r13)
337 ld r11,PACA_EXSLB+EX_R9(r13)
338 ld r12,PACA_EXSLB+EX_R3(r13)
339 std r10,PACA_EXGEN+EX_R13(r13)
340 std r11,PACA_EXGEN+EX_R9(r13)
341 std r12,PACA_EXGEN+EX_R3(r13)
344 mfspr r11,SRR0 /* save SRR0 */
345 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
346 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
348 mfspr r12,SRR1 /* and SRR1 */
351 b . /* prevent spec. execution */
352 #endif /* __DISABLED__ */
354 #ifdef CONFIG_PPC_PSERIES
356 * Vectors for the FWNMI option. Share common code.
358 .globl system_reset_fwnmi
362 mtspr SPRN_SPRG1,r13 /* save r13 */
363 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
365 .globl machine_check_fwnmi
369 mtspr SPRN_SPRG1,r13 /* save r13 */
370 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
372 #endif /* CONFIG_PPC_PSERIES */
374 /*** Common interrupt handlers ***/
376 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
379 * Machine check is different because we use a different
380 * save area: PACA_EXMC instead of PACA_EXGEN.
383 .globl machine_check_common
384 machine_check_common:
385 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
389 addi r3,r1,STACK_FRAME_OVERHEAD
390 bl .machine_check_exception
393 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
394 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
395 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
396 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
397 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
398 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
399 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
400 #ifdef CONFIG_ALTIVEC
401 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
403 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
405 #ifdef CONFIG_CBE_RAS
406 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
407 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
408 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
409 #endif /* CONFIG_CBE_RAS */
412 * Here we have detected that the kernel stack pointer is bad.
413 * R9 contains the saved CR, r13 points to the paca,
414 * r10 contains the (bad) kernel stack pointer,
415 * r11 and r12 contain the saved SRR0 and SRR1.
416 * We switch to using an emergency stack, save the registers there,
417 * and call kernel_bad_stack(), which panics.
420 ld r1,PACAEMERGSP(r13)
421 subi r1,r1,64+INT_FRAME_SIZE
442 lhz r12,PACA_TRAP_SAVE(r13)
444 addi r11,r1,INT_FRAME_SIZE
449 1: addi r3,r1,STACK_FRAME_OVERHEAD
454 * Return from an exception with minimal checks.
455 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
456 * If interrupts have been enabled, or anything has been
457 * done that might have changed the scheduling status of
458 * any task or sent any task a signal, you should use
459 * ret_from_except or ret_from_except_lite instead of this.
461 fast_exc_return_irq: /* restores irq state too */
463 TRACE_AND_RESTORE_IRQ(r3);
465 rldicl r4,r12,49,63 /* get MSR_EE to LSB */
466 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
469 .globl fast_exception_return
470 fast_exception_return:
473 andi. r3,r12,MSR_RI /* check if RI is set */
476 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
479 ACCOUNT_CPU_USER_EXIT(r3, r4)
495 rldicl r10,r10,48,1 /* clear EE */
496 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
504 b . /* prevent speculative execution */
508 1: addi r3,r1,STACK_FRAME_OVERHEAD
509 bl .unrecoverable_exception
513 * Here r13 points to the paca, r9 contains the saved CR,
514 * SRR0 and SRR1 are saved in r11 and r12,
515 * r9 - r13 are saved in paca->exgen.
518 .globl data_access_common
521 std r10,PACA_EXGEN+EX_DAR(r13)
523 stw r10,PACA_EXGEN+EX_DSISR(r13)
524 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
525 ld r3,PACA_EXGEN+EX_DAR(r13)
526 lwz r4,PACA_EXGEN+EX_DSISR(r13)
528 b .do_hash_page /* Try to handle as hpte fault */
531 .globl instruction_access_common
532 instruction_access_common:
533 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
537 b .do_hash_page /* Try to handle as hpte fault */
540 * Here is the common SLB miss user that is used when going to virtual
541 * mode for SLB misses, that is currently not used
545 .globl slb_miss_user_common
546 slb_miss_user_common:
548 std r3,PACA_EXGEN+EX_DAR(r13)
549 stw r9,PACA_EXGEN+EX_CCR(r13)
550 std r10,PACA_EXGEN+EX_LR(r13)
551 std r11,PACA_EXGEN+EX_SRR0(r13)
552 bl .slb_allocate_user
554 ld r10,PACA_EXGEN+EX_LR(r13)
555 ld r3,PACA_EXGEN+EX_R3(r13)
556 lwz r9,PACA_EXGEN+EX_CCR(r13)
557 ld r11,PACA_EXGEN+EX_SRR0(r13)
561 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
562 beq- unrecov_user_slb
570 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
576 ld r9,PACA_EXGEN+EX_R9(r13)
577 ld r10,PACA_EXGEN+EX_R10(r13)
578 ld r11,PACA_EXGEN+EX_R11(r13)
579 ld r12,PACA_EXGEN+EX_R12(r13)
580 ld r13,PACA_EXGEN+EX_R13(r13)
585 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
586 ld r4,PACA_EXGEN+EX_DAR(r13)
593 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
596 1: addi r3,r1,STACK_FRAME_OVERHEAD
597 bl .unrecoverable_exception
600 #endif /* __DISABLED__ */
604 * r13 points to the PACA, r9 contains the saved CR,
605 * r12 contain the saved SRR1, SRR0 is still ready for return
606 * r3 has the faulting address
607 * r9 - r13 are saved in paca->exslb.
608 * r3 is saved in paca->slb_r3
609 * We assume we aren't going to take any exceptions during this procedure.
611 _GLOBAL(slb_miss_realmode)
614 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
615 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
617 bl .slb_allocate_realmode
619 /* All done -- return from exception. */
621 ld r10,PACA_EXSLB+EX_LR(r13)
622 ld r3,PACA_EXSLB+EX_R3(r13)
623 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
624 #ifdef CONFIG_PPC_ISERIES
626 ld r11,PACALPPACAPTR(r13)
627 ld r11,LPPACASRR0(r11) /* get SRR0 value */
628 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
629 #endif /* CONFIG_PPC_ISERIES */
633 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
639 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
642 #ifdef CONFIG_PPC_ISERIES
646 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
647 #endif /* CONFIG_PPC_ISERIES */
648 ld r9,PACA_EXSLB+EX_R9(r13)
649 ld r10,PACA_EXSLB+EX_R10(r13)
650 ld r11,PACA_EXSLB+EX_R11(r13)
651 ld r12,PACA_EXSLB+EX_R12(r13)
652 ld r13,PACA_EXSLB+EX_R13(r13)
654 b . /* prevent speculative execution */
657 #ifdef CONFIG_PPC_ISERIES
660 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
661 #endif /* CONFIG_PPC_ISERIES */
664 LOAD_HANDLER(r10,unrecov_slb)
667 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
673 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
676 1: addi r3,r1,STACK_FRAME_OVERHEAD
677 bl .unrecoverable_exception
681 .globl hardware_interrupt_common
682 .globl hardware_interrupt_entry
683 hardware_interrupt_common:
684 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
686 hardware_interrupt_entry:
689 bl .ppc64_runlatch_on
690 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
691 addi r3,r1,STACK_FRAME_OVERHEAD
693 b .ret_from_except_lite
695 #ifdef CONFIG_PPC_970_NAP
698 std r9,TI_LOCAL_FLAGS(r11)
699 ld r10,_LINK(r1) /* make idle task do the */
700 std r10,_NIP(r1) /* equivalent of a blr */
705 .globl alignment_common
708 std r10,PACA_EXGEN+EX_DAR(r13)
710 stw r10,PACA_EXGEN+EX_DSISR(r13)
711 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
712 ld r3,PACA_EXGEN+EX_DAR(r13)
713 lwz r4,PACA_EXGEN+EX_DSISR(r13)
717 addi r3,r1,STACK_FRAME_OVERHEAD
719 bl .alignment_exception
723 .globl program_check_common
724 program_check_common:
725 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
727 addi r3,r1,STACK_FRAME_OVERHEAD
729 bl .program_check_exception
733 .globl fp_unavailable_common
734 fp_unavailable_common:
735 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
736 bne 1f /* if from user, just load it up */
738 addi r3,r1,STACK_FRAME_OVERHEAD
740 bl .kernel_fp_unavailable_exception
745 .globl altivec_unavailable_common
746 altivec_unavailable_common:
747 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
748 #ifdef CONFIG_ALTIVEC
750 bne .load_up_altivec /* if from user, just load it up */
751 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
754 addi r3,r1,STACK_FRAME_OVERHEAD
756 bl .altivec_unavailable_exception
759 #ifdef CONFIG_ALTIVEC
761 * load_up_altivec(unused, unused, tsk)
762 * Disable VMX for the task which had it previously,
763 * and save its vector registers in its thread_struct.
764 * Enables the VMX for use in the kernel on return.
765 * On SMP we know the VMX is free, since we give it up every
766 * switch (ie, no lazy save of the vector registers).
767 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
769 _STATIC(load_up_altivec)
770 mfmsr r5 /* grab the current MSR */
772 mtmsrd r5 /* enable use of VMX now */
776 * For SMP, we don't do lazy VMX switching because it just gets too
777 * horrendously complex, especially when a task switches from one CPU
778 * to another. Instead we call giveup_altvec in switch_to.
779 * VRSAVE isn't dealt with here, that is done in the normal context
780 * switch code. Note that we could rely on vrsave value to eventually
781 * avoid saving all of the VREGs here...
784 ld r3,last_task_used_altivec@got(r2)
788 /* Save VMX state to last_task_used_altivec's THREAD struct */
794 /* Disable VMX for last_task_used_altivec */
796 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
799 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
801 #endif /* CONFIG_SMP */
802 /* Hack: if we get an altivec unavailable trap with VRSAVE
803 * set to all zeros, we assume this is a broken application
804 * that fails to set it properly, and thus we switch it to
813 /* enable use of VMX after return */
814 ld r4,PACACURRENT(r13)
815 addi r5,r4,THREAD /* Get THREAD */
816 oris r12,r12,MSR_VEC@h
820 stw r4,THREAD_USED_VR(r5)
825 /* Update last_task_used_math to 'current' */
826 subi r4,r5,THREAD /* Back to 'current' */
828 #endif /* CONFIG_SMP */
829 /* restore registers and return */
830 b fast_exception_return
831 #endif /* CONFIG_ALTIVEC */
837 _STATIC(do_hash_page)
841 andis. r0,r4,0xa450 /* weird error? */
842 bne- handle_page_fault /* if not, try to insert a HPTE */
844 andis. r0,r4,0x0020 /* Is it a segment table fault? */
845 bne- do_ste_alloc /* If so handle it */
846 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
849 * On iSeries, we soft-disable interrupts here, then
850 * hard-enable interrupts so that the hash_page code can spin on
851 * the hash_table_lock without problems on a shared processor.
856 * Currently, trace_hardirqs_off() will be called by DISABLE_INTS
857 * and will clobber volatile registers when irq tracing is enabled
858 * so we need to reload them. It may be possible to be smarter here
859 * and move the irq tracing elsewhere but let's keep it simple for
862 #ifdef CONFIG_TRACE_IRQFLAGS
868 #endif /* CONFIG_TRACE_IRQFLAGS */
870 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
871 * accessing a userspace segment (even from the kernel). We assume
872 * kernel addresses always have the high bit set.
874 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
875 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
876 orc r0,r12,r0 /* MSR_PR | ~high_bit */
877 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
878 ori r4,r4,1 /* add _PAGE_PRESENT */
879 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
882 * r3 contains the faulting address
883 * r4 contains the required access permissions
884 * r5 contains the trap number
886 * at return r3 = 0 for success
888 bl .hash_page /* build HPTE if possible */
889 cmpdi r3,0 /* see if hash_page succeeded */
893 * If we had interrupts soft-enabled at the point where the
894 * DSI/ISI occurred, and an interrupt came in during hash_page,
896 * We jump to ret_from_except_lite rather than fast_exception_return
897 * because ret_from_except_lite will check for and handle pending
898 * interrupts if necessary.
901 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
905 * Here we have interrupts hard-disabled, so it is sufficient
906 * to restore paca->{soft,hard}_enable and get out.
908 beq fast_exc_return_irq /* Return from exception on success */
909 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
911 /* For a hash failure, we don't bother re-enabling interrupts */
915 * hash_page couldn't handle it, set soft interrupt enable back
916 * to what it was before the trap. Note that .raw_local_irq_restore
917 * handles any interrupts pending at this point.
920 TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
921 bl .raw_local_irq_restore
924 /* Here we have a page fault that hash_page can't handle. */
929 addi r3,r1,STACK_FRAME_OVERHEAD
935 addi r3,r1,STACK_FRAME_OVERHEAD
940 13: b .ret_from_except_lite
942 /* We have a page fault that hash_page could handle but HV refused
947 addi r3,r1,STACK_FRAME_OVERHEAD
952 /* here we have a segment miss */
954 bl .ste_allocate /* try to insert stab entry */
956 bne- handle_page_fault
957 b fast_exception_return
960 * r13 points to the PACA, r9 contains the saved CR,
961 * r11 and r12 contain the saved SRR0 and SRR1.
962 * r9 - r13 are saved in paca->exslb.
963 * We assume we aren't going to take any exceptions during this procedure.
964 * We assume (DAR >> 60) == 0xc.
967 _GLOBAL(do_stab_bolted)
968 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
969 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
971 /* Hash to the primary group */
972 ld r10,PACASTABVIRT(r13)
975 rldimi r10,r11,7,52 /* r10 = first ste of the group */
978 /* This is a kernel address, so protovsid = ESID */
979 ASM_VSID_SCRAMBLE(r11, r9, 256M)
980 rldic r9,r11,12,16 /* r9 = vsid << 12 */
982 /* Search the primary group for a free entry */
983 1: ld r11,0(r10) /* Test valid bit of the current ste */
990 /* Stick for only searching the primary group for now. */
991 /* At least for now, we use a very simple random castout scheme */
992 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
994 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
997 /* r10 currently points to an ste one past the group of interest */
998 /* make it point to the randomly selected entry */
1000 or r10,r10,r11 /* r10 is the entry to invalidate */
1002 isync /* mark the entry invalid */
1004 rldicl r11,r11,56,1 /* clear the valid bit */
1009 clrrdi r11,r11,28 /* Get the esid part of the ste */
1012 2: std r9,8(r10) /* Store the vsid part of the ste */
1015 mfspr r11,SPRN_DAR /* Get the new esid */
1016 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1017 ori r11,r11,0x90 /* Turn on valid and kp */
1018 std r11,0(r10) /* Put new entry back into the stab */
1022 /* All done -- return from exception. */
1023 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1024 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1026 andi. r10,r12,MSR_RI
1029 mtcrf 0x80,r9 /* restore CR */
1037 ld r9,PACA_EXSLB+EX_R9(r13)
1038 ld r10,PACA_EXSLB+EX_R10(r13)
1039 ld r11,PACA_EXSLB+EX_R11(r13)
1040 ld r12,PACA_EXSLB+EX_R12(r13)
1041 ld r13,PACA_EXSLB+EX_R13(r13)
1043 b . /* prevent speculative execution */
1046 * Space for CPU0's segment table.
1048 * On iSeries, the hypervisor must fill in at least one entry before
1049 * we get control (with relocate on). The address is given to the hv
1050 * as a page number (see xLparMap below), so this must be at a
1051 * fixed address (the linker can't compute (u64)&initial_stab >>
1054 . = STAB0_OFFSET /* 0x6000 */
1059 #ifdef CONFIG_PPC_PSERIES
1061 * Data area reserved for FWNMI option.
1062 * This address (0x7000) is fixed by the RPA.
1065 .globl fwnmi_data_area
1067 #endif /* CONFIG_PPC_PSERIES */
1069 /* iSeries does not use the FWNMI stuff, so it is safe to put
1070 * this here, even if we later allow kernels that will boot on
1071 * both pSeries and iSeries */
1072 #ifdef CONFIG_PPC_ISERIES
1076 .quad HvEsidsToMap /* xNumberEsids */
1077 .quad HvRangesToMap /* xNumberRanges */
1078 .quad STAB0_PAGE /* xSegmentTableOffs */
1079 .zero 40 /* xRsvd */
1080 /* xEsids (HvEsidsToMap entries of 2 quads) */
1081 .quad PAGE_OFFSET_ESID /* xKernelEsid */
1082 .quad PAGE_OFFSET_VSID /* xKernelVsid */
1083 .quad VMALLOC_START_ESID /* xKernelEsid */
1084 .quad VMALLOC_START_VSID /* xKernelVsid */
1085 /* xRanges (HvRangesToMap entries of 3 quads) */
1086 .quad HvPagesToMap /* xPages */
1087 .quad 0 /* xOffset */
1088 .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
1090 #endif /* CONFIG_PPC_ISERIES */
1092 #ifdef CONFIG_PPC_PSERIES
1094 #endif /* CONFIG_PPC_PSERIES */
1097 * On pSeries and most other platforms, secondary processors spin
1098 * in the following code.
1099 * At entry, r3 = this processor's number (physical cpu id)
1101 _GLOBAL(generic_secondary_smp_init)
1104 /* turn on 64-bit mode */
1107 /* Set up a paca value for this processor. Since we have the
1108 * physical cpu id in r24, we need to search the pacas to find
1109 * which logical id maps to our physical one.
1111 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1112 li r5,0 /* logical cpu id */
1113 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1114 cmpw r6,r24 /* Compare to our id */
1116 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1121 mr r3,r24 /* not found, copy phys to r3 */
1122 b .kexec_wait /* next kernel might do better */
1124 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1125 /* From now on, r24 is expected to be logical cpuid */
1128 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1133 b 3b /* Never go on non-SMP */
1136 beq 3b /* Loop until told to go */
1138 /* See if we need to call a cpu state restore handler */
1139 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1141 ld r23,CPU_SPEC_RESTORE(r23)
1148 4: /* Create a temp kernel stack for use before relocation is on. */
1149 ld r1,PACAEMERGSP(r13)
1150 subi r1,r1,STACK_FRAME_OVERHEAD
1157 andi. r0,r3,MSR_IR|MSR_DR
1164 b . /* prevent speculative execution */
1168 * Here is our main kernel entry point. We support currently 2 kind of entries
1169 * depending on the value of r5.
1171 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1174 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1175 * DT block, r4 is a physical pointer to the kernel itself
1178 _GLOBAL(__start_initialization_multiplatform)
1180 * Are we booted from a PROM Of-type client-interface ?
1184 b .__boot_from_prom /* yes -> prom */
1186 /* Save parameters */
1190 /* Make sure we are running in 64 bits mode */
1193 /* Setup some critical 970 SPRs before switching MMU off */
1196 cmpwi r0,0x39 /* 970 */
1198 cmpwi r0,0x3c /* 970FX */
1200 cmpwi r0,0x44 /* 970MP */
1202 cmpwi r0,0x45 /* 970GX */
1204 1: bl .__cpu_preinit_ppc970
1207 /* Switch off MMU if not already */
1208 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1211 b .__after_prom_start
1213 _INIT_STATIC(__boot_from_prom)
1214 /* Save parameters */
1222 * Align the stack to 16-byte boundary
1223 * Depending on the size and layout of the ELF sections in the initial
1224 * boot binary, the stack pointer will be unalignet on PowerMac
1228 /* Make sure we are running in 64 bits mode */
1231 /* put a relocation offset into r3 */
1234 LOAD_REG_IMMEDIATE(r2,__toc_start)
1238 /* Relocate the TOC from a virt addr to a real addr */
1241 /* Restore parameters */
1248 /* Do all of the interaction with OF client interface */
1250 /* We never return */
1253 _STATIC(__after_prom_start)
1256 * We need to run with __start at physical address PHYSICAL_START.
1257 * This will leave some code in the first 256B of
1258 * real memory, which are reserved for software use.
1259 * The remainder of the first page is loaded with the fixed
1260 * interrupt vectors. The next two pages are filled with
1261 * unknown exception placeholders.
1263 * Note: This process overwrites the OF exception vectors.
1264 * r26 == relocation offset
1269 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1271 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1273 // XXX FIXME: Use phys returned by OF (r30)
1274 add r4,r27,r26 /* source addr */
1275 /* current address of _start */
1276 /* i.e. where we are running */
1277 /* the source addr */
1279 cmpdi r4,0 /* In some cases the loader may */
1281 b .start_here_multiplatform /* have already put us at zero */
1282 /* so we can skip the copy. */
1283 1: LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1286 li r6,0x100 /* Start offset, the first 0x100 */
1287 /* bytes were copied earlier. */
1289 bl .copy_and_flush /* copy the first n bytes */
1290 /* this includes the code being */
1291 /* executed here. */
1293 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1294 mtctr r0 /* that we just made/relocated */
1297 4: LOAD_REG_IMMEDIATE(r5,klimit)
1299 ld r5,0(r5) /* get the value of klimit */
1301 bl .copy_and_flush /* copy the rest */
1302 b .start_here_multiplatform
1305 * Copy routine used to copy the kernel to start at physical address 0
1306 * and flush and invalidate the caches as needed.
1307 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1308 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1310 * Note: this routine *only* clobbers r0, r6 and lr
1312 _GLOBAL(copy_and_flush)
1315 4: li r0,8 /* Use the smallest common */
1316 /* denominator cache line */
1317 /* size. This results in */
1318 /* extra cache line flushes */
1319 /* but operation is correct. */
1320 /* Can't get cache line size */
1321 /* from NACA as it is being */
1324 mtctr r0 /* put # words/line in ctr */
1325 3: addi r6,r6,8 /* copy a cache line */
1329 dcbst r6,r3 /* write it to memory */
1331 icbi r6,r3 /* flush the icache line */
1343 #ifdef CONFIG_PPC_PMAC
1345 * On PowerMac, secondary processors starts from the reset vector, which
1346 * is temporarily turned into a call to one of the functions below.
1351 .globl __secondary_start_pmac_0
1352 __secondary_start_pmac_0:
1353 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1363 _GLOBAL(pmac_secondary_start)
1364 /* turn on 64-bit mode */
1367 /* Copy some CPU settings from CPU 0 */
1368 bl .__restore_cpu_ppc970
1370 /* pSeries do that early though I don't think we really need it */
1373 mtmsrd r3 /* RI on */
1375 /* Set up a paca value for this processor. */
1376 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1377 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1378 add r13,r13,r4 /* for this processor. */
1379 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1381 /* Create a temp kernel stack for use before relocation is on. */
1382 ld r1,PACAEMERGSP(r13)
1383 subi r1,r1,STACK_FRAME_OVERHEAD
1387 #endif /* CONFIG_PPC_PMAC */
1390 * This function is called after the master CPU has released the
1391 * secondary processors. The execution environment is relocation off.
1392 * The paca for this processor has the following fields initialized at
1394 * 1. Processor number
1395 * 2. Segment table pointer (virtual address)
1396 * On entry the following are set:
1397 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1398 * r24 = cpu# (in Linux terms)
1399 * r13 = paca virtual address
1400 * SPRG3 = paca virtual address
1402 .globl __secondary_start
1404 /* Set thread priority to MEDIUM */
1410 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1411 bl .early_setup_secondary
1413 /* Initialize the kernel stack. Just a repeat for iSeries. */
1414 LOAD_REG_ADDR(r3, current_set)
1415 sldi r28,r24,3 /* get current_set[cpu#] */
1417 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1418 std r1,PACAKSAVE(r13)
1420 /* Clear backchain so we get nice backtraces */
1424 /* enable MMU and jump to start_secondary */
1425 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1426 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1427 #ifdef CONFIG_PPC_ISERIES
1428 BEGIN_FW_FTR_SECTION
1431 stb r8,PACAHARDIRQEN(r13)
1432 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1434 BEGIN_FW_FTR_SECTION
1435 stb r7,PACAHARDIRQEN(r13)
1436 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1437 stb r7,PACASOFTIRQEN(r13)
1442 b . /* prevent speculative execution */
1445 * Running with relocation on at this point. All we want to do is
1446 * zero the stack back-chain pointer before going into C code.
1448 _GLOBAL(start_secondary_prolog)
1450 std r3,0(r1) /* Zero the stack frame pointer */
1456 * This subroutine clobbers r11 and r12
1458 _GLOBAL(enable_64b_mode)
1459 mfmsr r11 /* grab the current MSR */
1461 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1464 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1471 * This is where the main kernel code starts.
1473 _INIT_STATIC(start_here_multiplatform)
1474 /* get a new offset, now that the kernel has moved. */
1478 /* Clear out the BSS. It may have been done in prom_init,
1479 * already but that's irrelevant since prom_init will soon
1480 * be detached from the kernel completely. Besides, we need
1481 * to clear it now for kexec-style entry.
1483 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1484 LOAD_REG_IMMEDIATE(r8,__bss_start)
1485 sub r11,r11,r8 /* bss size */
1486 addi r11,r11,7 /* round up to an even double word */
1487 rldicl. r11,r11,61,3 /* shift right by 3 */
1491 mtctr r11 /* zero this many doublewords */
1498 mtmsrd r6 /* RI on */
1500 /* The following gets the stack and TOC set up with the regs */
1501 /* pointing to the real addr of the kernel stack. This is */
1502 /* all done to support the C function call below which sets */
1503 /* up the htab. This is done because we have relocated the */
1504 /* kernel but are still running in real mode. */
1506 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1509 /* set up a stack pointer (physical address) */
1510 addi r1,r3,THREAD_SIZE
1512 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1514 /* set up the TOC (physical address) */
1515 LOAD_REG_IMMEDIATE(r2,__toc_start)
1520 /* Set initial ptr to current */
1521 LOAD_REG_IMMEDIATE(r4, init_task)
1522 std r4,PACACURRENT(r13)
1524 /* Do very early kernel initializations, including initial hash table,
1525 * stab and slb setup before we turn on relocation. */
1527 /* Restore parameters passed from prom_init/kexec */
1531 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1532 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1536 b . /* prevent speculative execution */
1538 /* This is where all platforms converge execution */
1539 _INIT_GLOBAL(start_here_common)
1540 /* relocation is on at this point */
1542 /* The following code sets up the SP and TOC now that we are */
1543 /* running with translation enabled. */
1545 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1547 /* set up the stack */
1548 addi r1,r3,THREAD_SIZE
1550 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1554 std r1,PACAKSAVE(r13)
1558 /* Load up the kernel context */
1561 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
1562 #ifdef CONFIG_PPC_ISERIES
1563 BEGIN_FW_FTR_SECTION
1565 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/
1568 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1570 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */
1578 * We put a few things here that have to be page-aligned.
1579 * This stuff goes at the beginning of the bss, which is page-aligned.
1585 .globl empty_zero_page
1589 .globl swapper_pg_dir
1591 .space PGD_TABLE_SIZE