1 #ifndef _ASM_POWERPC_PTE_BOOK3E_H
2 #define _ASM_POWERPC_PTE_BOOK3E_H
5 /* PTE bit definitions for processors compliant to the Book3E
6 * architecture 2.06 or later. The position of the PTE bits
7 * matches the HW definition of the optional Embedded Page Table
11 /* Architected bits */
12 #define _PAGE_PRESENT 0x000001 /* software: pte contains a translation */
13 #define _PAGE_FILE 0x000002 /* (!present only) software: pte holds file offset */
14 #define _PAGE_SW1 0x000002
15 #define _PAGE_BAP_SR 0x000004
16 #define _PAGE_BAP_UR 0x000008
17 #define _PAGE_BAP_SW 0x000010
18 #define _PAGE_BAP_UW 0x000020
19 #define _PAGE_BAP_SX 0x000040
20 #define _PAGE_BAP_UX 0x000080
21 #define _PAGE_PSIZE_MSK 0x000f00
22 #define _PAGE_PSIZE_4K 0x000200
23 #define _PAGE_PSIZE_64K 0x000600
24 #define _PAGE_PSIZE_1M 0x000a00
25 #define _PAGE_PSIZE_16M 0x000e00
26 #define _PAGE_DIRTY 0x001000 /* C: page changed */
27 #define _PAGE_SW0 0x002000
28 #define _PAGE_U3 0x004000
29 #define _PAGE_U2 0x008000
30 #define _PAGE_U1 0x010000
31 #define _PAGE_U0 0x020000
32 #define _PAGE_ACCESSED 0x040000
33 #define _PAGE_LENDIAN 0x080000
34 #define _PAGE_GUARDED 0x100000
35 #define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */
36 #define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */
37 #define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
39 /* "Higher level" linux bit combinations */
40 #define _PAGE_EXEC _PAGE_BAP_UX /* .. and was cache cleaned */
41 #define _PAGE_RW (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
42 #define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
43 #define _PAGE_KERNEL_RO (_PAGE_BAP_SR)
44 #define _PAGE_KERNEL_RWX (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
45 #define _PAGE_KERNEL_ROX (_PAGE_BAP_SR | _PAGE_BAP_SX)
46 #define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
48 #define _PAGE_HASHPTE 0
51 #define _PAGE_SPECIAL _PAGE_SW0
53 /* Flags to be preserved on PTE modifications */
54 #define _PAGE_HPTEFLAGS _PAGE_BUSY
57 #ifdef CONFIG_PPC_64K_PAGES
58 #define _PAGE_PSIZE _PAGE_PSIZE_64K
59 #define PTE_RPN_SHIFT (28)
61 #define _PAGE_PSIZE _PAGE_PSIZE_4K
62 #define PTE_RPN_SHIFT (24)
65 /* On 32-bit, we never clear the top part of the PTE */
67 #define _PTE_NONE_MASK 0xffffffff00000000ULL
70 #endif /* __KERNEL__ */
71 #endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */