2 * P2020 RDB Core1 Device Tree Source in CAMP mode.
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, dma2, eth0, pci1, msi.
8 * Please note to add "-b 1" for core1's dts compiling.
10 * Copyright 2009-2011 Freescale Semiconductor Inc.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
38 next-level-cache = <&L2>;
43 device_type = "memory";
50 compatible = "fsl,p2020-immr", "simple-bus";
51 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 bus-frequency = <0>; // Filled out by uboot.
54 serial0: serial@4600 {
56 device_type = "serial";
57 compatible = "ns16550";
59 clock-frequency = <0>;
65 compatible = "fsl,eloplus-dma";
67 ranges = <0x0 0xc100 0x200>;
70 compatible = "fsl,eloplus-dma-channel";
73 interrupt-parent = <&mpic>;
77 compatible = "fsl,eloplus-dma-channel";
80 interrupt-parent = <&mpic>;
84 compatible = "fsl,eloplus-dma-channel";
87 interrupt-parent = <&mpic>;
91 compatible = "fsl,eloplus-dma-channel";
94 interrupt-parent = <&mpic>;
99 L2: l2-cache-controller@20000 {
100 compatible = "fsl,p2020-l2-cache-controller";
101 reg = <0x20000 0x1000>;
102 cache-line-size = <32>; // 32 bytes
103 cache-size = <0x80000>; // L2,512K
104 interrupt-parent = <&mpic>;
108 enet0: ethernet@24000 {
109 #address-cells = <1>;
112 device_type = "network";
114 compatible = "gianfar";
115 reg = <0x24000 0x1000>;
116 ranges = <0x0 0x24000 0x1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <29 2 30 2 34 2>;
119 interrupt-parent = <&mpic>;
120 fixed-link = <1 1 1000 0 0>;
121 phy-connection-type = "rgmii-id";
126 interrupt-controller;
127 #address-cells = <0>;
128 #interrupt-cells = <2>;
129 reg = <0x40000 0x40000>;
130 compatible = "chrp,open-pic";
131 device_type = "open-pic";
132 protected-sources = <
133 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
134 16 20 21 22 23 28 /* L2, dma1, USB */
135 03 35 36 40 31 32 33 /* mdio, enet1, enet2 */
136 72 45 58 25 /* sdhci, crypto , pci */
141 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
142 reg = <0x41600 0x80>;
143 msi-available-ranges = <0 0x100>;
153 interrupt-parent = <&mpic>;
157 pci1: pcie@ffe0a000 {
158 compatible = "fsl,mpc8548-pcie";
160 #interrupt-cells = <1>;
162 #address-cells = <3>;
163 reg = <0 0xffe0a000 0 0x1000>;
165 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
166 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
167 clock-frequency = <33333333>;
168 interrupt-parent = <&mpic>;
171 reg = <0x0 0x0 0x0 0x0 0x0>;
173 #address-cells = <3>;
175 ranges = <0x2000000 0x0 0x80000000
176 0x2000000 0x0 0x80000000