arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8568EMDS";
  16         compatible = "MPC8568EMDS", "MPC85xxMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 ethernet3 = &enet3;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 pci0 = &pci0;
  28                 pci1 = &pci1;
  29                 rapidio0 = &rio0;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 PowerPC,8568@0 {
  37                         device_type = "cpu";
  38                         reg = <0x0>;
  39                         d-cache-line-size = <32>;       // 32 bytes
  40                         i-cache-line-size = <32>;       // 32 bytes
  41                         d-cache-size = <0x8000>;                // L1, 32K
  42                         i-cache-size = <0x8000>;                // L1, 32K
  43                         sleep = <&pmc 0x00008000        // core
  44                                  &pmc 0x00004000>;      // timebase
  45                         timebase-frequency = <0>;
  46                         bus-frequency = <0>;
  47                         clock-frequency = <0>;
  48                         next-level-cache = <&L2>;
  49                 };
  50         };
  51
  52         memory {
  53                 device_type = "memory";
  54                 reg = <0x0 0x10000000>;
  55         };
  56
  57         bcsr@f8000000 {
  58                 compatible = "fsl,mpc8568mds-bcsr";
  59                 reg = <0xf8000000 0x8000>;
  60         };
  61
  62         soc8568@e0000000 {
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 device_type = "soc";
  66                 compatible = "simple-bus";
  67                 ranges = <0x0 0xe0000000 0x100000>;
  68                 bus-frequency = <0>;
  69
  70                 ecm-law@0 {
  71                         compatible = "fsl,ecm-law";
  72                         reg = <0x0 0x1000>;
  73                         fsl,num-laws = <10>;
  74                 };
  75
  76                 ecm@1000 {
  77                         compatible = "fsl,mpc8568-ecm", "fsl,ecm";
  78                         reg = <0x1000 0x1000>;
  79                         interrupts = <17 2>;
  80                         interrupt-parent = <&mpic>;
  81                 };
  82
  83                 memory-controller@2000 {
  84                         compatible = "fsl,8568-memory-controller";
  85                         reg = <0x2000 0x1000>;
  86                         interrupt-parent = <&mpic>;
  87                         interrupts = <18 2>;
  88                 };
  89
  90                 L2: l2-cache-controller@20000 {
  91                         compatible = "fsl,8568-l2-cache-controller";
  92                         reg = <0x20000 0x1000>;
  93                         cache-line-size = <32>; // 32 bytes
  94                         cache-size = <0x80000>; // L2, 512K
  95                         interrupt-parent = <&mpic>;
  96                         interrupts = <16 2>;
  97                 };
  98
  99                 i2c-sleep-nexus {
 100                         #address-cells = <1>;
 101                         #size-cells = <1>;
 102                         compatible = "simple-bus";
 103                         sleep = <&pmc 0x00000004>;
 104                         ranges;
 105
 106                         i2c@3000 {
 107                                 #address-cells = <1>;
 108                                 #size-cells = <0>;
 109                                 cell-index = <0>;
 110                                 compatible = "fsl-i2c";
 111                                 reg = <0x3000 0x100>;
 112                                 interrupts = <43 2>;
 113                                 interrupt-parent = <&mpic>;
 114                                 dfsrr;
 115
 116                                 rtc@68 {
 117                                         compatible = "dallas,ds1374";
 118                                         reg = <0x68>;
 119                                         interrupts = <3 1>;
 120                                         interrupt-parent = <&mpic>;
 121                                 };
 122                         };
 123
 124                         i2c@3100 {
 125                                 #address-cells = <1>;
 126                                 #size-cells = <0>;
 127                                 cell-index = <1>;
 128                                 compatible = "fsl-i2c";
 129                                 reg = <0x3100 0x100>;
 130                                 interrupts = <43 2>;
 131                                 interrupt-parent = <&mpic>;
 132                                 dfsrr;
 133                         };
 134                 };
 135
 136                 dma@21300 {
 137                         #address-cells = <1>;
 138                         #size-cells = <1>;
 139                         compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
 140                         reg = <0x21300 0x4>;
 141                         ranges = <0x0 0x21100 0x200>;
 142                         cell-index = <0>;
 143                         sleep = <&pmc 0x00000400>;
 144
 145                         dma-channel@0 {
 146                                 compatible = "fsl,mpc8568-dma-channel",
 147                                                 "fsl,eloplus-dma-channel";
 148                                 reg = <0x0 0x80>;
 149                                 cell-index = <0>;
 150                                 interrupt-parent = <&mpic>;
 151                                 interrupts = <20 2>;
 152                         };
 153                         dma-channel@80 {
 154                                 compatible = "fsl,mpc8568-dma-channel",
 155                                                 "fsl,eloplus-dma-channel";
 156                                 reg = <0x80 0x80>;
 157                                 cell-index = <1>;
 158                                 interrupt-parent = <&mpic>;
 159                                 interrupts = <21 2>;
 160                         };
 161                         dma-channel@100 {
 162                                 compatible = "fsl,mpc8568-dma-channel",
 163                                                 "fsl,eloplus-dma-channel";
 164                                 reg = <0x100 0x80>;
 165                                 cell-index = <2>;
 166                                 interrupt-parent = <&mpic>;
 167                                 interrupts = <22 2>;
 168                         };
 169                         dma-channel@180 {
 170                                 compatible = "fsl,mpc8568-dma-channel",
 171                                                 "fsl,eloplus-dma-channel";
 172                                 reg = <0x180 0x80>;
 173                                 cell-index = <3>;
 174                                 interrupt-parent = <&mpic>;
 175                                 interrupts = <23 2>;
 176                         };
 177                 };
 178
 179                 enet0: ethernet@24000 {
 180                         #address-cells = <1>;
 181                         #size-cells = <1>;
 182                         cell-index = <0>;
 183                         device_type = "network";
 184                         model = "eTSEC";
 185                         compatible = "gianfar";
 186                         reg = <0x24000 0x1000>;
 187                         ranges = <0x0 0x24000 0x1000>;
 188                         local-mac-address = [ 00 00 00 00 00 00 ];
 189                         interrupts = <29 2 30 2 34 2>;
 190                         interrupt-parent = <&mpic>;
 191                         tbi-handle = <&tbi0>;
 192                         phy-handle = <&phy2>;
 193                         sleep = <&pmc 0x00000080>;
 194
 195                         mdio@520 {
 196                                 #address-cells = <1>;
 197                                 #size-cells = <0>;
 198                                 compatible = "fsl,gianfar-mdio";
 199                                 reg = <0x520 0x20>;
 200
 201                                 phy0: ethernet-phy@7 {
 202                                         interrupt-parent = <&mpic>;
 203                                         interrupts = <1 1>;
 204                                         reg = <0x7>;
 205                                         device_type = "ethernet-phy";
 206                                 };
 207                                 phy1: ethernet-phy@1 {
 208                                         interrupt-parent = <&mpic>;
 209                                         interrupts = <2 1>;
 210                                         reg = <0x1>;
 211                                         device_type = "ethernet-phy";
 212                                 };
 213                                 phy2: ethernet-phy@2 {
 214                                         interrupt-parent = <&mpic>;
 215                                         interrupts = <1 1>;
 216                                         reg = <0x2>;
 217                                         device_type = "ethernet-phy";
 218                                 };
 219                                 phy3: ethernet-phy@3 {
 220                                         interrupt-parent = <&mpic>;
 221                                         interrupts = <2 1>;
 222                                         reg = <0x3>;
 223                                         device_type = "ethernet-phy";
 224                                 };
 225                                 tbi0: tbi-phy@11 {
 226                                         reg = <0x11>;
 227                                         device_type = "tbi-phy";
 228                                 };
 229                         };
 230                 };
 231
 232                 enet1: ethernet@25000 {
 233                         #address-cells = <1>;
 234                         #size-cells = <1>;
 235                         cell-index = <1>;
 236                         device_type = "network";
 237                         model = "eTSEC";
 238                         compatible = "gianfar";
 239                         reg = <0x25000 0x1000>;
 240                         ranges = <0x0 0x25000 0x1000>;
 241                         local-mac-address = [ 00 00 00 00 00 00 ];
 242                         interrupts = <35 2 36 2 40 2>;
 243                         interrupt-parent = <&mpic>;
 244                         tbi-handle = <&tbi1>;
 245                         phy-handle = <&phy3>;
 246                         sleep = <&pmc 0x00000040>;
 247
 248                         mdio@520 {
 249                                 #address-cells = <1>;
 250                                 #size-cells = <0>;
 251                                 compatible = "fsl,gianfar-tbi";
 252                                 reg = <0x520 0x20>;
 253
 254                                 tbi1: tbi-phy@11 {
 255                                         reg = <0x11>;
 256                                         device_type = "tbi-phy";
 257                                 };
 258                         };
 259                 };
 260
 261                 duart-sleep-nexus {
 262                         #address-cells = <1>;
 263                         #size-cells = <1>;
 264                         compatible = "simple-bus";
 265                         sleep = <&pmc 0x00000002>;
 266                         ranges;
 267
 268                         serial0: serial@4500 {
 269                                 cell-index = <0>;
 270                                 device_type = "serial";
 271                                 compatible = "ns16550";
 272                                 reg = <0x4500 0x100>;
 273                                 clock-frequency = <0>;
 274                                 interrupts = <42 2>;
 275                                 interrupt-parent = <&mpic>;
 276                         };
 277
 278                         serial1: serial@4600 {
 279                                 cell-index = <1>;
 280                                 device_type = "serial";
 281                                 compatible = "ns16550";
 282                                 reg = <0x4600 0x100>;
 283                                 clock-frequency = <0>;
 284                                 interrupts = <42 2>;
 285                                 interrupt-parent = <&mpic>;
 286                         };
 287                 };
 288
 289                 global-utilities@e0000 {
 290                         #address-cells = <1>;
 291                         #size-cells = <1>;
 292                         compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
 293                         reg = <0xe0000 0x1000>;
 294                         ranges = <0 0xe0000 0x1000>;
 295                         fsl,has-rstcr;
 296
 297                         pmc: power@70 {
 298                                 compatible = "fsl,mpc8568-pmc",
 299                                              "fsl,mpc8548-pmc";
 300                                 reg = <0x70 0x20>;
 301                         };
 302                 };
 303
 304                 crypto@30000 {
 305                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 306                         reg = <0x30000 0x10000>;
 307                         interrupts = <45 2>;
 308                         interrupt-parent = <&mpic>;
 309                         fsl,num-channels = <4>;
 310                         fsl,channel-fifo-len = <24>;
 311                         fsl,exec-units-mask = <0xfe>;
 312                         fsl,descriptor-types-mask = <0x12b0ebf>;
 313                         sleep = <&pmc 0x01000000>;
 314                 };
 315
 316                 mpic: pic@40000 {
 317                         interrupt-controller;
 318                         #address-cells = <0>;
 319                         #interrupt-cells = <2>;
 320                         reg = <0x40000 0x40000>;
 321                         compatible = "chrp,open-pic";
 322                         device_type = "open-pic";
 323                 };
 324
 325                 msi@41600 {
 326                         compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
 327                         reg = <0x41600 0x80>;
 328                         msi-available-ranges = <0 0x100>;
 329                         interrupts = <
 330                                 0xe0 0
 331                                 0xe1 0
 332                                 0xe2 0
 333                                 0xe3 0
 334                                 0xe4 0
 335                                 0xe5 0
 336                                 0xe6 0
 337                                 0xe7 0>;
 338                         interrupt-parent = <&mpic>;
 339                 };
 340
 341                 par_io@e0100 {
 342                         reg = <0xe0100 0x100>;
 343                         device_type = "par_io";
 344                         num-ports = <7>;
 345
 346                         pio1: ucc_pin@01 {
 347                                 pio-map = <
 348                         /* port  pin  dir  open_drain  assignment  has_irq */
 349                                         0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
 350                                         0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
 351                                         0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
 352                                         0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
 353                                         0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
 354                                         0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
 355                                         0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
 356                                         0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
 357                                         0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
 358                                         0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
 359                                         0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
 360                                         0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
 361                                         0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
 362                                         0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
 363                                         0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
 364                                         0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
 365                                         0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
 366                                         0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
 367                                         0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
 368                                         0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
 369                                         0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
 370                                         0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
 371                                         0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
 372                         };
 373
 374                         pio2: ucc_pin@02 {
 375                                 pio-map = <
 376                         /* port  pin  dir  open_drain  assignment  has_irq */
 377                                         0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
 378                                         0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
 379                                         0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
 380                                         0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
 381                                         0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
 382                                         0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
 383                                         0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
 384                                         0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
 385                                         0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
 386                                         0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
 387                                         0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
 388                                         0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
 389                                         0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
 390                                         0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
 391                                         0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
 392                                         0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
 393                                         0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
 394                                         0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
 395                                         0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
 396                                         0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
 397                                         0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
 398                                         0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
 399                                         0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
 400                                         0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
 401                                         0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
 402                         };
 403                 };
 404         };
 405
 406         qe@e0080000 {
 407                 #address-cells = <1>;
 408                 #size-cells = <1>;
 409                 device_type = "qe";
 410                 compatible = "fsl,qe";
 411                 ranges = <0x0 0xe0080000 0x40000>;
 412                 reg = <0xe0080000 0x480>;
 413                 sleep = <&pmc 0x00000800>;
 414                 brg-frequency = <0>;
 415                 bus-frequency = <396000000>;
 416                 fsl,qe-num-riscs = <2>;
 417                 fsl,qe-num-snums = <28>;
 418
 419                 muram@10000 {
 420                         #address-cells = <1>;
 421                         #size-cells = <1>;
 422                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 423                         ranges = <0x0 0x10000 0x10000>;
 424
 425                         data-only@0 {
 426                                 compatible = "fsl,qe-muram-data",
 427                                              "fsl,cpm-muram-data";
 428                                 reg = <0x0 0x10000>;
 429                         };
 430                 };
 431
 432                 spi@4c0 {
 433                         cell-index = <0>;
 434                         compatible = "fsl,spi";
 435                         reg = <0x4c0 0x40>;
 436                         interrupts = <2>;
 437                         interrupt-parent = <&qeic>;
 438                         mode = "cpu";
 439                 };
 440
 441                 spi@500 {
 442                         cell-index = <1>;
 443                         compatible = "fsl,spi";
 444                         reg = <0x500 0x40>;
 445                         interrupts = <1>;
 446                         interrupt-parent = <&qeic>;
 447                         mode = "cpu";
 448                 };
 449
 450                 enet2: ucc@2000 {
 451                         device_type = "network";
 452                         compatible = "ucc_geth";
 453                         cell-index = <1>;
 454                         reg = <0x2000 0x200>;
 455                         interrupts = <32>;
 456                         interrupt-parent = <&qeic>;
 457                         local-mac-address = [ 00 00 00 00 00 00 ];
 458                         rx-clock-name = "none";
 459                         tx-clock-name = "clk16";
 460                         pio-handle = <&pio1>;
 461                         phy-handle = <&phy0>;
 462                         phy-connection-type = "rgmii-id";
 463                 };
 464
 465                 enet3: ucc@3000 {
 466                         device_type = "network";
 467                         compatible = "ucc_geth";
 468                         cell-index = <2>;
 469                         reg = <0x3000 0x200>;
 470                         interrupts = <33>;
 471                         interrupt-parent = <&qeic>;
 472                         local-mac-address = [ 00 00 00 00 00 00 ];
 473                         rx-clock-name = "none";
 474                         tx-clock-name = "clk16";
 475                         pio-handle = <&pio2>;
 476                         phy-handle = <&phy1>;
 477                         phy-connection-type = "rgmii-id";
 478                 };
 479
 480                 mdio@2120 {
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                         reg = <0x2120 0x18>;
 484                         compatible = "fsl,ucc-mdio";
 485
 486                         /* These are the same PHYs as on
 487                          * gianfar's MDIO bus */
 488                         qe_phy0: ethernet-phy@07 {
 489                                 interrupt-parent = <&mpic>;
 490                                 interrupts = <1 1>;
 491                                 reg = <0x7>;
 492                                 device_type = "ethernet-phy";
 493                         };
 494                         qe_phy1: ethernet-phy@01 {
 495                                 interrupt-parent = <&mpic>;
 496                                 interrupts = <2 1>;
 497                                 reg = <0x1>;
 498                                 device_type = "ethernet-phy";
 499                         };
 500                         qe_phy2: ethernet-phy@02 {
 501                                 interrupt-parent = <&mpic>;
 502                                 interrupts = <1 1>;
 503                                 reg = <0x2>;
 504                                 device_type = "ethernet-phy";
 505                         };
 506                         qe_phy3: ethernet-phy@03 {
 507                                 interrupt-parent = <&mpic>;
 508                                 interrupts = <2 1>;
 509                                 reg = <0x3>;
 510                                 device_type = "ethernet-phy";
 511                         };
 512                 };
 513
 514                 qeic: interrupt-controller@80 {
 515                         interrupt-controller;
 516                         compatible = "fsl,qe-ic";
 517                         #address-cells = <0>;
 518                         #interrupt-cells = <1>;
 519                         reg = <0x80 0x80>;
 520                         big-endian;
 521                         interrupts = <46 2 46 2>; //high:30 low:30
 522                         interrupt-parent = <&mpic>;
 523                 };
 524
 525         };
 526
 527         pci0: pci@e0008000 {
 528                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 529                 interrupt-map = <
 530                         /* IDSEL 0x12 AD18 */
 531                         0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
 532                         0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
 533                         0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
 534                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 535
 536                         /* IDSEL 0x13 AD19 */
 537                         0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
 538                         0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
 539                         0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
 540                         0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 541
 542                 interrupt-parent = <&mpic>;
 543                 interrupts = <24 2>;
 544                 bus-range = <0 255>;
 545                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 546                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 547                 sleep = <&pmc 0x80000000>;
 548                 clock-frequency = <66666666>;
 549                 #interrupt-cells = <1>;
 550                 #size-cells = <2>;
 551                 #address-cells = <3>;
 552                 reg = <0xe0008000 0x1000>;
 553                 compatible = "fsl,mpc8540-pci";
 554                 device_type = "pci";
 555         };
 556
 557         /* PCI Express */
 558         pci1: pcie@e000a000 {
 559                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 560                 interrupt-map = <
 561
 562                         /* IDSEL 0x0 (PEX) */
 563                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 564                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 565                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 566                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 567
 568                 interrupt-parent = <&mpic>;
 569                 interrupts = <26 2>;
 570                 bus-range = <0 255>;
 571                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 572                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 573                 sleep = <&pmc 0x20000000>;
 574                 clock-frequency = <33333333>;
 575                 #interrupt-cells = <1>;
 576                 #size-cells = <2>;
 577                 #address-cells = <3>;
 578                 reg = <0xe000a000 0x1000>;
 579                 compatible = "fsl,mpc8548-pcie";
 580                 device_type = "pci";
 581                 pcie@0 {
 582                         reg = <0x0 0x0 0x0 0x0 0x0>;
 583                         #size-cells = <2>;
 584                         #address-cells = <3>;
 585                         device_type = "pci";
 586                         ranges = <0x2000000 0x0 0xa0000000
 587                                   0x2000000 0x0 0xa0000000
 588                                   0x0 0x10000000
 589
 590                                   0x1000000 0x0 0x0
 591                                   0x1000000 0x0 0x0
 592                                   0x0 0x800000>;
 593                 };
 594         };
 595
 596         rio0: rapidio@e00c00000 {
 597                 #address-cells = <2>;
 598                 #size-cells = <2>;
 599                 compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta";
 600                 reg = <0xe00c0000 0x20000>;
 601                 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
 602                 interrupts = <48 2 /* error     */
 603                               49 2 /* bell_outb */
 604                               50 2 /* bell_inb  */
 605                               53 2 /* msg1_tx   */
 606                               54 2 /* msg1_rx   */
 607                               55 2 /* msg2_tx   */
 608                               56 2 /* msg2_rx   */>;
 609                 interrupt-parent = <&mpic>;
 610                 sleep = <&pmc 0x00080000   /* controller */
 611                          &pmc 0x00040000>; /* message unit */
 612         };
 613 };