arch/powerpc/boot/dts/canyonlands.dts

   1 /*
   2  * Device Tree Source for AMCC Canyonlands (460EX)
   3  *
   4  * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without
   8  * any warranty of any kind, whether express or implied.
   9  */
  10
  11 /dts-v1/;
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <1>;
  16         model = "amcc,canyonlands";
  17         compatible = "amcc,canyonlands";
  18         dcr-parent = <&{/cpus/cpu@0}>;
  19
  20         aliases {
  21                 ethernet0 = &EMAC0;
  22                 ethernet1 = &EMAC1;
  23                 serial0 = &UART0;
  24                 serial1 = &UART1;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         model = "PowerPC,460EX";
  34                         reg = <0x00000000>;
  35                         clock-frequency = <0>; /* Filled in by U-Boot */
  36                         timebase-frequency = <0>; /* Filled in by U-Boot */
  37                         i-cache-line-size = <32>;
  38                         d-cache-line-size = <32>;
  39                         i-cache-size = <32768>;
  40                         d-cache-size = <32768>;
  41                         dcr-controller;
  42                         dcr-access-method = "native";
  43                         next-level-cache = <&L2C0>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
  50         };
  51
  52         UIC0: interrupt-controller0 {
  53                 compatible = "ibm,uic-460ex","ibm,uic";
  54                 interrupt-controller;
  55                 cell-index = <0>;
  56                 dcr-reg = <0x0c0 0x009>;
  57                 #address-cells = <0>;
  58                 #size-cells = <0>;
  59                 #interrupt-cells = <2>;
  60         };
  61
  62         UIC1: interrupt-controller1 {
  63                 compatible = "ibm,uic-460ex","ibm,uic";
  64                 interrupt-controller;
  65                 cell-index = <1>;
  66                 dcr-reg = <0x0d0 0x009>;
  67                 #address-cells = <0>;
  68                 #size-cells = <0>;
  69                 #interrupt-cells = <2>;
  70                 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  71                 interrupt-parent = <&UIC0>;
  72         };
  73
  74         UIC2: interrupt-controller2 {
  75                 compatible = "ibm,uic-460ex","ibm,uic";
  76                 interrupt-controller;
  77                 cell-index = <2>;
  78                 dcr-reg = <0x0e0 0x009>;
  79                 #address-cells = <0>;
  80                 #size-cells = <0>;
  81                 #interrupt-cells = <2>;
  82                 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
  83                 interrupt-parent = <&UIC0>;
  84         };
  85
  86         UIC3: interrupt-controller3 {
  87                 compatible = "ibm,uic-460ex","ibm,uic";
  88                 interrupt-controller;
  89                 cell-index = <3>;
  90                 dcr-reg = <0x0f0 0x009>;
  91                 #address-cells = <0>;
  92                 #size-cells = <0>;
  93                 #interrupt-cells = <2>;
  94                 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
  95                 interrupt-parent = <&UIC0>;
  96         };
  97
  98         SDR0: sdr {
  99                 compatible = "ibm,sdr-460ex";
 100                 dcr-reg = <0x00e 0x002>;
 101         };
 102
 103         CPR0: cpr {
 104                 compatible = "ibm,cpr-460ex";
 105                 dcr-reg = <0x00c 0x002>;
 106         };
 107
 108         L2C0: l2c {
 109                 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
 110                 dcr-reg = <0x020 0x008          /* Internal SRAM DCR's */
 111                            0x030 0x008>;        /* L2 cache DCR's */
 112                 cache-line-size = <32>;         /* 32 bytes */
 113                 cache-size = <262144>;          /* L2, 256K */
 114                 interrupt-parent = <&UIC1>;
 115                 interrupts = <11 1>;
 116         };
 117
 118         plb {
 119                 compatible = "ibm,plb-460ex", "ibm,plb4";
 120                 #address-cells = <2>;
 121                 #size-cells = <1>;
 122                 ranges;
 123                 clock-frequency = <0>; /* Filled in by U-Boot */
 124
 125                 SDRAM0: sdram {
 126                         compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
 127                         dcr-reg = <0x010 0x002>;
 128                 };
 129
 130                 CRYPTO: crypto@180000 {
 131                         compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
 132                         reg = <4 0x00180000 0x80400>;
 133                         interrupt-parent = <&UIC0>;
 134                         interrupts = <0x1d 0x4>;
 135                 };
 136
 137                 MAL0: mcmal {
 138                         compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
 139                         dcr-reg = <0x180 0x062>;
 140                         num-tx-chans = <2>;
 141                         num-rx-chans = <16>;
 142                         #address-cells = <0>;
 143                         #size-cells = <0>;
 144                         interrupt-parent = <&UIC2>;
 145                         interrupts = <  /*TXEOB*/ 0x6 0x4
 146                                         /*RXEOB*/ 0x7 0x4
 147                                         /*SERR*/  0x3 0x4
 148                                         /*TXDE*/  0x4 0x4
 149                                         /*RXDE*/  0x5 0x4>;
 150                 };
 151
 152                 POB0: opb {
 153                         compatible = "ibm,opb-460ex", "ibm,opb";
 154                         #address-cells = <1>;
 155                         #size-cells = <1>;
 156                         ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
 157                         clock-frequency = <0>; /* Filled in by U-Boot */
 158
 159                         EBC0: ebc {
 160                                 compatible = "ibm,ebc-460ex", "ibm,ebc";
 161                                 dcr-reg = <0x012 0x002>;
 162                                 #address-cells = <2>;
 163                                 #size-cells = <1>;
 164                                 clock-frequency = <0>; /* Filled in by U-Boot */
 165                                 /* ranges property is supplied by U-Boot */
 166                                 interrupts = <0x6 0x4>;
 167                                 interrupt-parent = <&UIC1>;
 168
 169                                 nor_flash@0,0 {
 170                                         compatible = "amd,s29gl512n", "cfi-flash";
 171                                         bank-width = <2>;
 172                                         reg = <0x00000000 0x00000000 0x04000000>;
 173                                         #address-cells = <1>;
 174                                         #size-cells = <1>;
 175                                         partition@0 {
 176                                                 label = "kernel";
 177                                                 reg = <0x00000000 0x001e0000>;
 178                                         };
 179                                         partition@1e0000 {
 180                                                 label = "dtb";
 181                                                 reg = <0x001e0000 0x00020000>;
 182                                         };
 183                                         partition@200000 {
 184                                                 label = "ramdisk";
 185                                                 reg = <0x00200000 0x01400000>;
 186                                         };
 187                                         partition@1600000 {
 188                                                 label = "jffs2";
 189                                                 reg = <0x01600000 0x00400000>;
 190                                         };
 191                                         partition@1a00000 {
 192                                                 label = "user";
 193                                                 reg = <0x01a00000 0x02560000>;
 194                                         };
 195                                         partition@3f60000 {
 196                                                 label = "env";
 197                                                 reg = <0x03f60000 0x00040000>;
 198                                         };
 199                                         partition@3fa0000 {
 200                                                 label = "u-boot";
 201                                                 reg = <0x03fa0000 0x00060000>;
 202                                         };
 203                                 };
 204                         };
 205
 206                         UART0: serial@ef600300 {
 207                                 device_type = "serial";
 208                                 compatible = "ns16550";
 209                                 reg = <0xef600300 0x00000008>;
 210                                 virtual-reg = <0xef600300>;
 211                                 clock-frequency = <0>; /* Filled in by U-Boot */
 212                                 current-speed = <0>; /* Filled in by U-Boot */
 213                                 interrupt-parent = <&UIC1>;
 214                                 interrupts = <0x1 0x4>;
 215                         };
 216
 217                         UART1: serial@ef600400 {
 218                                 device_type = "serial";
 219                                 compatible = "ns16550";
 220                                 reg = <0xef600400 0x00000008>;
 221                                 virtual-reg = <0xef600400>;
 222                                 clock-frequency = <0>; /* Filled in by U-Boot */
 223                                 current-speed = <0>; /* Filled in by U-Boot */
 224                                 interrupt-parent = <&UIC0>;
 225                                 interrupts = <0x1 0x4>;
 226                         };
 227
 228                         UART2: serial@ef600500 {
 229                                 device_type = "serial";
 230                                 compatible = "ns16550";
 231                                 reg = <0xef600500 0x00000008>;
 232                                 virtual-reg = <0xef600500>;
 233                                 clock-frequency = <0>; /* Filled in by U-Boot */
 234                                 current-speed = <0>; /* Filled in by U-Boot */
 235                                 interrupt-parent = <&UIC1>;
 236                                 interrupts = <0x1d 0x4>;
 237                         };
 238
 239                         UART3: serial@ef600600 {
 240                                 device_type = "serial";
 241                                 compatible = "ns16550";
 242                                 reg = <0xef600600 0x00000008>;
 243                                 virtual-reg = <0xef600600>;
 244                                 clock-frequency = <0>; /* Filled in by U-Boot */
 245                                 current-speed = <0>; /* Filled in by U-Boot */
 246                                 interrupt-parent = <&UIC1>;
 247                                 interrupts = <0x1e 0x4>;
 248                         };
 249
 250                         IIC0: i2c@ef600700 {
 251                                 compatible = "ibm,iic-460ex", "ibm,iic";
 252                                 reg = <0xef600700 0x00000014>;
 253                                 interrupt-parent = <&UIC0>;
 254                                 interrupts = <0x2 0x4>;
 255                         };
 256
 257                         IIC1: i2c@ef600800 {
 258                                 compatible = "ibm,iic-460ex", "ibm,iic";
 259                                 reg = <0xef600800 0x00000014>;
 260                                 interrupt-parent = <&UIC0>;
 261                                 interrupts = <0x3 0x4>;
 262                         };
 263
 264                         ZMII0: emac-zmii@ef600d00 {
 265                                 compatible = "ibm,zmii-460ex", "ibm,zmii";
 266                                 reg = <0xef600d00 0x0000000c>;
 267                         };
 268
 269                         RGMII0: emac-rgmii@ef601500 {
 270                                 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
 271                                 reg = <0xef601500 0x00000008>;
 272                                 has-mdio;
 273                         };
 274
 275                         TAH0: emac-tah@ef601350 {
 276                                 compatible = "ibm,tah-460ex", "ibm,tah";
 277                                 reg = <0xef601350 0x00000030>;
 278                         };
 279
 280                         TAH1: emac-tah@ef601450 {
 281                                 compatible = "ibm,tah-460ex", "ibm,tah";
 282                                 reg = <0xef601450 0x00000030>;
 283                         };
 284
 285                         EMAC0: ethernet@ef600e00 {
 286                                 device_type = "network";
 287                                 compatible = "ibm,emac-460ex", "ibm,emac4sync";
 288                                 interrupt-parent = <&EMAC0>;
 289                                 interrupts = <0x0 0x1>;
 290                                 #interrupt-cells = <1>;
 291                                 #address-cells = <0>;
 292                                 #size-cells = <0>;
 293                                 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
 294                                                  /*Wake*/   0x1 &UIC2 0x14 0x4>;
 295                                 reg = <0xef600e00 0x000000c4>;
 296                                 local-mac-address = [000000000000]; /* Filled in by U-Boot */
 297                                 mal-device = <&MAL0>;
 298                                 mal-tx-channel = <0>;
 299                                 mal-rx-channel = <0>;
 300                                 cell-index = <0>;
 301                                 max-frame-size = <9000>;
 302                                 rx-fifo-size = <4096>;
 303                                 tx-fifo-size = <2048>;
 304                                 phy-mode = "rgmii";
 305                                 phy-map = <0x00000000>;
 306                                 rgmii-device = <&RGMII0>;
 307                                 rgmii-channel = <0>;
 308                                 tah-device = <&TAH0>;
 309                                 tah-channel = <0>;
 310                                 has-inverted-stacr-oc;
 311                                 has-new-stacr-staopc;
 312                         };
 313
 314                         EMAC1: ethernet@ef600f00 {
 315                                 device_type = "network";
 316                                 compatible = "ibm,emac-460ex", "ibm,emac4sync";
 317                                 interrupt-parent = <&EMAC1>;
 318                                 interrupts = <0x0 0x1>;
 319                                 #interrupt-cells = <1>;
 320                                 #address-cells = <0>;
 321                                 #size-cells = <0>;
 322                                 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
 323                                                  /*Wake*/   0x1 &UIC2 0x15 0x4>;
 324                                 reg = <0xef600f00 0x000000c4>;
 325                                 local-mac-address = [000000000000]; /* Filled in by U-Boot */
 326                                 mal-device = <&MAL0>;
 327                                 mal-tx-channel = <1>;
 328                                 mal-rx-channel = <8>;
 329                                 cell-index = <1>;
 330                                 max-frame-size = <9000>;
 331                                 rx-fifo-size = <4096>;
 332                                 tx-fifo-size = <2048>;
 333                                 phy-mode = "rgmii";
 334                                 phy-map = <0x00000000>;
 335                                 rgmii-device = <&RGMII0>;
 336                                 rgmii-channel = <1>;
 337                                 tah-device = <&TAH1>;
 338                                 tah-channel = <1>;
 339                                 has-inverted-stacr-oc;
 340                                 has-new-stacr-staopc;
 341                                 mdio-device = <&EMAC0>;
 342                         };
 343                 };
 344
 345                 PCIX0: pci@c0ec00000 {
 346                         device_type = "pci";
 347                         #interrupt-cells = <1>;
 348                         #size-cells = <2>;
 349                         #address-cells = <3>;
 350                         compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
 351                         primary;
 352                         large-inbound-windows;
 353                         enable-msi-hole;
 354                         reg = <0x0000000c 0x0ec00000   0x00000008       /* Config space access */
 355                                0x00000000 0x00000000 0x00000000         /* no IACK cycles */
 356                                0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
 357                                0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
 358                                0x0000000c 0x0ec80100  0x000000fc>;      /* Internal messaging registers */
 359
 360                         /* Outbound ranges, one memory and one IO,
 361                          * later cannot be changed
 362                          */
 363                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
 364                                   0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
 365                                   0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
 366
 367                         /* Inbound 2GB range starting at 0 */
 368                         dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
 369
 370                         /* This drives busses 0 to 0x3f */
 371                         bus-range = <0x0 0x3f>;
 372
 373                         /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
 374                         interrupt-map-mask = <0x0 0x0 0x0 0x0>;
 375                         interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
 376                 };
 377
 378                 PCIE0: pciex@d00000000 {
 379                         device_type = "pci";
 380                         #interrupt-cells = <1>;
 381                         #size-cells = <2>;
 382                         #address-cells = <3>;
 383                         compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
 384                         primary;
 385                         port = <0x0>; /* port number */
 386                         reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
 387                                0x0000000c 0x08010000 0x00001000>;       /* Registers */
 388                         dcr-reg = <0x100 0x020>;
 389                         sdr-base = <0x300>;
 390
 391                         /* Outbound ranges, one memory and one IO,
 392                          * later cannot be changed
 393                          */
 394                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
 395                                   0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
 396                                   0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
 397
 398                         /* Inbound 2GB range starting at 0 */
 399                         dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
 400
 401                         /* This drives busses 40 to 0x7f */
 402                         bus-range = <0x40 0x7f>;
 403
 404                         /* Legacy interrupts (note the weird polarity, the bridge seems
 405                          * to invert PCIe legacy interrupts).
 406                          * We are de-swizzling here because the numbers are actually for
 407                          * port of the root complex virtual P2P bridge. But I want
 408                          * to avoid putting a node for it in the tree, so the numbers
 409                          * below are basically de-swizzled numbers.
 410                          * The real slot is on idsel 0, so the swizzling is 1:1
 411                          */
 412                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 413                         interrupt-map = <
 414                                 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
 415                                 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
 416                                 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
 417                                 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
 418                 };
 419
 420                 PCIE1: pciex@d20000000 {
 421                         device_type = "pci";
 422                         #interrupt-cells = <1>;
 423                         #size-cells = <2>;
 424                         #address-cells = <3>;
 425                         compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
 426                         primary;
 427                         port = <0x1>; /* port number */
 428                         reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
 429                                0x0000000c 0x08011000 0x00001000>;       /* Registers */
 430                         dcr-reg = <0x120 0x020>;
 431                         sdr-base = <0x340>;
 432
 433                         /* Outbound ranges, one memory and one IO,
 434                          * later cannot be changed
 435                          */
 436                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
 437                                   0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
 438                                   0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
 439
 440                         /* Inbound 2GB range starting at 0 */
 441                         dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
 442
 443                         /* This drives busses 80 to 0xbf */
 444                         bus-range = <0x80 0xbf>;
 445
 446                         /* Legacy interrupts (note the weird polarity, the bridge seems
 447                          * to invert PCIe legacy interrupts).
 448                          * We are de-swizzling here because the numbers are actually for
 449                          * port of the root complex virtual P2P bridge. But I want
 450                          * to avoid putting a node for it in the tree, so the numbers
 451                          * below are basically de-swizzled numbers.
 452                          * The real slot is on idsel 0, so the swizzling is 1:1
 453                          */
 454                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 455                         interrupt-map = <
 456                                 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
 457                                 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
 458                                 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
 459                                 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
 460                 };
 461         };
 462 };