arch/mips/sibyte/sb1250/bcm1250_tbprof.c

   1 /*
   2  * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 #define SBPROF_TB_DEBUG 0
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/fs.h>
  29 #include <linux/errno.h>
  30 #include <linux/reboot.h>
  31 #include <linux/wait.h>
  32 #include <asm/uaccess.h>
  33 #include <asm/io.h>
  34 #include <asm/sibyte/sb1250.h>
  35 #include <asm/sibyte/sb1250_regs.h>
  36 #include <asm/sibyte/sb1250_scd.h>
  37 #include <asm/sibyte/sb1250_int.h>
  38 #include <asm/sibyte/trace_prof.h>
  39
  40 #define DEVNAME "bcm1250_tbprof"
  41
  42 static struct sbprof_tb sbp;
  43
  44 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
  45
  46 /************************************************************************
  47  * Support for ZBbus sampling using the trace buffer
  48  *
  49  * We use the SCD performance counter interrupt, caused by a Zclk counter
  50  * overflow, to trigger the start of tracing.
  51  *
  52  * We set the trace buffer to sample everything and freeze on
  53  * overflow.
  54  *
  55  * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
  56  *
  57  ************************************************************************/
  58
  59 static u_int64_t tb_period;
  60
  61 static void arm_tb(void)
  62 {
  63         u_int64_t scdperfcnt;
  64         u_int64_t next = (1ULL << 40) - tb_period;
  65         u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
  66         /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
  67            trigger start of trace.  XXX vary sampling period */
  68         __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
  69         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
  70         /* Unfortunately, in Pass 2 we must clear all counters to knock down
  71            a previous interrupt request.  This means that bus profiling
  72            requires ALL of the SCD perf counters. */
  73         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
  74                                                 // keep counters 0,2,3 as is
  75                      M_SPC_CFG_ENABLE |         // enable counting
  76                      M_SPC_CFG_CLEAR |          // clear all counters
  77                      V_SPC_CFG_SRC1(1),         // counter 1 counts cycles
  78                      IOADDR(A_SCD_PERF_CNT_CFG));
  79         __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
  80         /* Reset the trace buffer */
  81         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
  82 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
  83         /* XXXKW may want to expose control to the data-collector */
  84         tb_options |= M_SCD_TRACE_CFG_FORCECNT;
  85 #endif
  86         __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
  87         sbp.tb_armed = 1;
  88 }
  89
  90 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
  91 {
  92         int i;
  93         DBG(printk(DEVNAME ": tb_intr\n"));
  94         if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
  95                 /* XXX should use XKPHYS to make writes bypass L2 */
  96                 u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
  97                 /* Read out trace */
  98                 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
  99                              IOADDR(A_SCD_TRACE_CFG));
 100                 __asm__ __volatile__ ("sync" : : : "memory");
 101                 /* Loop runs backwards because bundles are read out in reverse order */
 102                 for (i = 256 * 6; i > 0; i -= 6) {
 103                         // Subscripts decrease to put bundle in the order
 104                         //   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
 105                         p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 106                                                                 // read t2 hi
 107                         p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 108                                                                 // read t2 lo
 109                         p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 110                                                                 // read t1 hi
 111                         p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 112                                                                 // read t1 lo
 113                         p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 114                                                                 // read t0 hi
 115                         p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 116                                                                 // read t0 lo
 117                 }
 118                 if (!sbp.tb_enable) {
 119                         DBG(printk(DEVNAME ": tb_intr shutdown\n"));
 120                         __raw_writeq(M_SCD_TRACE_CFG_RESET,
 121                                      IOADDR(A_SCD_TRACE_CFG));
 122                         sbp.tb_armed = 0;
 123                         wake_up(&sbp.tb_sync);
 124                 } else {
 125                         arm_tb();       // knock down current interrupt and get another one later
 126                 }
 127         } else {
 128                 /* No more trace buffer samples */
 129                 DBG(printk(DEVNAME ": tb_intr full\n"));
 130                 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 131                 sbp.tb_armed = 0;
 132                 if (!sbp.tb_enable) {
 133                         wake_up(&sbp.tb_sync);
 134                 }
 135                 wake_up(&sbp.tb_read);
 136         }
 137         return IRQ_HANDLED;
 138 }
 139
 140 static irqreturn_t sbprof_pc_intr(int irq, void *dev_id, struct pt_regs *regs)
 141 {
 142         printk(DEVNAME ": unexpected pc_intr");
 143         return IRQ_NONE;
 144 }
 145
 146 int sbprof_zbprof_start(struct file *filp)
 147 {
 148         u_int64_t scdperfcnt;
 149
 150         if (sbp.tb_enable)
 151                 return -EBUSY;
 152
 153         DBG(printk(DEVNAME ": starting\n"));
 154
 155         sbp.tb_enable = 1;
 156         sbp.next_tb_sample = 0;
 157         filp->f_pos = 0;
 158
 159         if (request_irq
 160             (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) {
 161                 return -EBUSY;
 162         }
 163         /* Make sure there isn't a perf-cnt interrupt waiting */
 164         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 165         /* Disable and clear counters, override SRC_1 */
 166         __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
 167                      M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
 168                      IOADDR(A_SCD_PERF_CNT_CFG));
 169
 170         /* We grab this interrupt to prevent others from trying to use
 171            it, even though we don't want to service the interrupts
 172            (they only feed into the trace-on-interrupt mechanism) */
 173         if (request_irq
 174             (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
 175                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 176                 return -EBUSY;
 177         }
 178
 179         /* I need the core to mask these, but the interrupt mapper to
 180            pass them through.  I am exploiting my knowledge that
 181            cp0_status masks out IP[5]. krw */
 182         __raw_writeq(K_INT_MAP_I3,
 183                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 184                             (K_INT_PERF_CNT << 3)));
 185
 186         /* Initialize address traps */
 187         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
 188         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
 189         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
 190         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
 191
 192         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
 193         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
 194         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
 195         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
 196
 197         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
 198         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
 199         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
 200         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 201
 202         /* Initialize Trace Event 0-7 */
 203         //                              when interrupt
 204         __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
 205         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
 206         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
 207         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
 208         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
 209         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
 210         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
 211         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
 212
 213         /* Initialize Trace Sequence 0-7 */
 214         //                                   Start on event 0 (interrupt)
 215         __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
 216                      IOADDR(A_SCD_TRACE_SEQUENCE_0));
 217         //                        dsamp when d used | asamp when a used
 218         __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
 219                      K_SCD_TRSEQ_TRIGGER_ALL,
 220                      IOADDR(A_SCD_TRACE_SEQUENCE_1));
 221         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
 222         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
 223         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
 224         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
 225         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
 226         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
 227
 228         /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
 229         __raw_writeq(1ULL << K_INT_PERF_CNT,
 230                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
 231
 232         arm_tb();
 233
 234         DBG(printk(DEVNAME ": done starting\n"));
 235
 236         return 0;
 237 }
 238
 239 int sbprof_zbprof_stop(void)
 240 {
 241         DEFINE_WAIT(wait);
 242         DBG(printk(DEVNAME ": stopping\n"));
 243
 244         if (sbp.tb_enable) {
 245                 sbp.tb_enable = 0;
 246                 /* XXXKW there is a window here where the intr handler
 247                    may run, see the disable, and do the wake_up before
 248                    this sleep happens. */
 249                 if (sbp.tb_armed) {
 250                         DBG(printk(DEVNAME ": wait for disarm\n"));
 251                         prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE);
 252                         schedule();
 253                         finish_wait(&sbp.tb_sync, &wait);
 254                         DBG(printk(DEVNAME ": disarm complete\n"));
 255                 }
 256                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 257                 free_irq(K_INT_PERF_CNT, &sbp);
 258         }
 259
 260         DBG(printk(DEVNAME ": done stopping\n"));
 261
 262         return 0;
 263 }
 264
 265 static int sbprof_tb_open(struct inode *inode, struct file *filp)
 266 {
 267         int minor;
 268
 269         minor = iminor(inode);
 270         if (minor != 0) {
 271                 return -ENODEV;
 272         }
 273         if (sbp.open) {
 274                 return -EBUSY;
 275         }
 276
 277         memset(&sbp, 0, sizeof(struct sbprof_tb));
 278         sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
 279         if (!sbp.sbprof_tbbuf) {
 280                 return -ENOMEM;
 281         }
 282         memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
 283         init_waitqueue_head(&sbp.tb_sync);
 284         init_waitqueue_head(&sbp.tb_read);
 285         sbp.open = 1;
 286
 287         return 0;
 288 }
 289
 290 static int sbprof_tb_release(struct inode *inode, struct file *filp)
 291 {
 292         int minor;
 293
 294         minor = iminor(inode);
 295         if (minor != 0 || !sbp.open) {
 296                 return -ENODEV;
 297         }
 298
 299         if (sbp.tb_armed || sbp.tb_enable) {
 300                 sbprof_zbprof_stop();
 301         }
 302
 303         vfree(sbp.sbprof_tbbuf);
 304         sbp.open = 0;
 305
 306         return 0;
 307 }
 308
 309 static ssize_t sbprof_tb_read(struct file *filp, char *buf,
 310                               size_t size, loff_t *offp)
 311 {
 312         int cur_sample, sample_off, cur_count, sample_left;
 313         char *src;
 314         int   count   =  0;
 315         char *dest    =  buf;
 316         long  cur_off = *offp;
 317
 318         count = 0;
 319         cur_sample = cur_off / TB_SAMPLE_SIZE;
 320         sample_off = cur_off % TB_SAMPLE_SIZE;
 321         sample_left = TB_SAMPLE_SIZE - sample_off;
 322         while (size && (cur_sample < sbp.next_tb_sample)) {
 323                 cur_count = size < sample_left ? size : sample_left;
 324                 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
 325                 copy_to_user(dest, src, cur_count);
 326                 DBG(printk(DEVNAME ": read from sample %d, %d bytes\n",
 327                            cur_sample, cur_count));
 328                 size -= cur_count;
 329                 sample_left -= cur_count;
 330                 if (!sample_left) {
 331                         cur_sample++;
 332                         sample_off = 0;
 333                         sample_left = TB_SAMPLE_SIZE;
 334                 } else {
 335                         sample_off += cur_count;
 336                 }
 337                 cur_off += cur_count;
 338                 dest += cur_count;
 339                 count += cur_count;
 340         }
 341         *offp = cur_off;
 342
 343         return count;
 344 }
 345
 346 static int sbprof_tb_ioctl(struct inode *inode,
 347                            struct file *filp,
 348                            unsigned int command,
 349                            unsigned long arg)
 350 {
 351         int error = 0;
 352
 353         switch (command) {
 354         case SBPROF_ZBSTART:
 355                 error = sbprof_zbprof_start(filp);
 356                 break;
 357         case SBPROF_ZBSTOP:
 358                 error = sbprof_zbprof_stop();
 359                 break;
 360         case SBPROF_ZBWAITFULL:
 361                 DEFINE_WAIT(wait);
 362                 prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE);
 363                 schedule();
 364                 finish_wait(&sbp.tb_read, &wait);
 365                 /* XXXKW check if interrupted? */
 366                 return put_user(TB_FULL, (int *) arg);
 367         default:
 368                 error = -EINVAL;
 369                 break;
 370         }
 371
 372         return error;
 373 }
 374
 375 static struct file_operations sbprof_tb_fops = {
 376         .owner          = THIS_MODULE,
 377         .open           = sbprof_tb_open,
 378         .release        = sbprof_tb_release,
 379         .read           = sbprof_tb_read,
 380         .ioctl          = sbprof_tb_ioctl,
 381         .mmap           = NULL,
 382 };
 383
 384 static int __init sbprof_tb_init(void)
 385 {
 386         if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
 387                 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
 388                        SBPROF_TB_MAJOR);
 389                 return -EIO;
 390         }
 391         sbp.open = 0;
 392         tb_period = zbbus_mhz * 10000LL;
 393         printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period);
 394         return 0;
 395 }
 396
 397 static void __exit sbprof_tb_cleanup(void)
 398 {
 399         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 400 }
 401
 402 module_init(sbprof_tb_init);
 403 module_exit(sbprof_tb_cleanup);