arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware fpu at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an fpu, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/percpu-defs.h>
  39 #include <linux/perf_event.h>
  40
  41 #include <asm/branch.h>
  42 #include <asm/inst.h>
  43 #include <asm/ptrace.h>
  44 #include <asm/signal.h>
  45 #include <asm/uaccess.h>
  46
  47 #include <asm/processor.h>
  48 #include <asm/fpu_emulator.h>
  49 #include <asm/fpu.h>
  50
  51 #include "ieee754.h"
  52
  53 /* Strap kernel emulator for full MIPS IV emulation */
  54
  55 #ifdef __mips
  56 #undef __mips
  57 #endif
  58 #define __mips 4
  59
  60 /* Function which emulates a floating point instruction. */
  61
  62 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  63         mips_instruction);
  64
  65 #if __mips >= 4 && __mips != 32
  66 static int fpux_emu(struct pt_regs *,
  67         struct mips_fpu_struct *, mips_instruction, void *__user *);
  68 #endif
  69
  70 /* Control registers */
  71
  72 #define FPCREG_RID      0       /* $0  = revision id */
  73 #define FPCREG_CSR      31      /* $31 = csr */
  74
  75 /* Determine rounding mode from the RM bits of the FCSR */
  76 #define modeindex(v) ((v) & FPU_CSR_RM)
  77
  78 /* microMIPS bitfields */
  79 #define MM_POOL32A_MINOR_MASK   0x3f
  80 #define MM_POOL32A_MINOR_SHIFT  0x6
  81 #define MM_MIPS32_COND_FC       0x30
  82
  83 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
  84 static const unsigned char ieee_rm[4] = {
  85         [FPU_CSR_RN] = IEEE754_RN,
  86         [FPU_CSR_RZ] = IEEE754_RZ,
  87         [FPU_CSR_RU] = IEEE754_RU,
  88         [FPU_CSR_RD] = IEEE754_RD,
  89 };
  90 /* Convert IEEE library modes to Mips rounding mode (0..3). */
  91 static const unsigned char mips_rm[4] = {
  92         [IEEE754_RN] = FPU_CSR_RN,
  93         [IEEE754_RZ] = FPU_CSR_RZ,
  94         [IEEE754_RD] = FPU_CSR_RD,
  95         [IEEE754_RU] = FPU_CSR_RU,
  96 };
  97
  98 #if __mips >= 4
  99 /* convert condition code register number to csr bit */
 100 static const unsigned int fpucondbit[8] = {
 101         FPU_CSR_COND0,
 102         FPU_CSR_COND1,
 103         FPU_CSR_COND2,
 104         FPU_CSR_COND3,
 105         FPU_CSR_COND4,
 106         FPU_CSR_COND5,
 107         FPU_CSR_COND6,
 108         FPU_CSR_COND7
 109 };
 110 #endif
 111
 112 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
 113 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
 114
 115 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
 116 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
 117 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
 118 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
 119 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
 120
 121 /*
 122  * This functions translates a 32-bit microMIPS instruction
 123  * into a 32-bit MIPS32 instruction. Returns 0 on success
 124  * and SIGILL otherwise.
 125  */
 126 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
 127 {
 128         union mips_instruction insn = *insn_ptr;
 129         union mips_instruction mips32_insn = insn;
 130         int func, fmt, op;
 131
 132         switch (insn.mm_i_format.opcode) {
 133         case mm_ldc132_op:
 134                 mips32_insn.mm_i_format.opcode = ldc1_op;
 135                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 136                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 137                 break;
 138         case mm_lwc132_op:
 139                 mips32_insn.mm_i_format.opcode = lwc1_op;
 140                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 141                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 142                 break;
 143         case mm_sdc132_op:
 144                 mips32_insn.mm_i_format.opcode = sdc1_op;
 145                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 146                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 147                 break;
 148         case mm_swc132_op:
 149                 mips32_insn.mm_i_format.opcode = swc1_op;
 150                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 151                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 152                 break;
 153         case mm_pool32i_op:
 154                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 155                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 156                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 157                         mips32_insn.fb_format.opcode = cop1_op;
 158                         mips32_insn.fb_format.bc = bc_op;
 159                         mips32_insn.fb_format.flag =
 160                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 161                 } else
 162                         return SIGILL;
 163                 break;
 164         case mm_pool32f_op:
 165                 switch (insn.mm_fp0_format.func) {
 166                 case mm_32f_01_op:
 167                 case mm_32f_11_op:
 168                 case mm_32f_02_op:
 169                 case mm_32f_12_op:
 170                 case mm_32f_41_op:
 171                 case mm_32f_51_op:
 172                 case mm_32f_42_op:
 173                 case mm_32f_52_op:
 174                         op = insn.mm_fp0_format.func;
 175                         if (op == mm_32f_01_op)
 176                                 func = madd_s_op;
 177                         else if (op == mm_32f_11_op)
 178                                 func = madd_d_op;
 179                         else if (op == mm_32f_02_op)
 180                                 func = nmadd_s_op;
 181                         else if (op == mm_32f_12_op)
 182                                 func = nmadd_d_op;
 183                         else if (op == mm_32f_41_op)
 184                                 func = msub_s_op;
 185                         else if (op == mm_32f_51_op)
 186                                 func = msub_d_op;
 187                         else if (op == mm_32f_42_op)
 188                                 func = nmsub_s_op;
 189                         else
 190                                 func = nmsub_d_op;
 191                         mips32_insn.fp6_format.opcode = cop1x_op;
 192                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 193                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 194                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 195                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 196                         mips32_insn.fp6_format.func = func;
 197                         break;
 198                 case mm_32f_10_op:
 199                         func = -1;      /* Invalid */
 200                         op = insn.mm_fp5_format.op & 0x7;
 201                         if (op == mm_ldxc1_op)
 202                                 func = ldxc1_op;
 203                         else if (op == mm_sdxc1_op)
 204                                 func = sdxc1_op;
 205                         else if (op == mm_lwxc1_op)
 206                                 func = lwxc1_op;
 207                         else if (op == mm_swxc1_op)
 208                                 func = swxc1_op;
 209
 210                         if (func != -1) {
 211                                 mips32_insn.r_format.opcode = cop1x_op;
 212                                 mips32_insn.r_format.rs =
 213                                         insn.mm_fp5_format.base;
 214                                 mips32_insn.r_format.rt =
 215                                         insn.mm_fp5_format.index;
 216                                 mips32_insn.r_format.rd = 0;
 217                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 218                                 mips32_insn.r_format.func = func;
 219                         } else
 220                                 return SIGILL;
 221                         break;
 222                 case mm_32f_40_op:
 223                         op = -1;        /* Invalid */
 224                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 225                                 op = 1;
 226                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 227                                 op = 0;
 228                         if (op != -1) {
 229                                 mips32_insn.fp0_format.opcode = cop1_op;
 230                                 mips32_insn.fp0_format.fmt =
 231                                         sdps_format[insn.mm_fp2_format.fmt];
 232                                 mips32_insn.fp0_format.ft =
 233                                         (insn.mm_fp2_format.cc<<2) + op;
 234                                 mips32_insn.fp0_format.fs =
 235                                         insn.mm_fp2_format.fs;
 236                                 mips32_insn.fp0_format.fd =
 237                                         insn.mm_fp2_format.fd;
 238                                 mips32_insn.fp0_format.func = fmovc_op;
 239                         } else
 240                                 return SIGILL;
 241                         break;
 242                 case mm_32f_60_op:
 243                         func = -1;      /* Invalid */
 244                         if (insn.mm_fp0_format.op == mm_fadd_op)
 245                                 func = fadd_op;
 246                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 247                                 func = fsub_op;
 248                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 249                                 func = fmul_op;
 250                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 251                                 func = fdiv_op;
 252                         if (func != -1) {
 253                                 mips32_insn.fp0_format.opcode = cop1_op;
 254                                 mips32_insn.fp0_format.fmt =
 255                                         sdps_format[insn.mm_fp0_format.fmt];
 256                                 mips32_insn.fp0_format.ft =
 257                                         insn.mm_fp0_format.ft;
 258                                 mips32_insn.fp0_format.fs =
 259                                         insn.mm_fp0_format.fs;
 260                                 mips32_insn.fp0_format.fd =
 261                                         insn.mm_fp0_format.fd;
 262                                 mips32_insn.fp0_format.func = func;
 263                         } else
 264                                 return SIGILL;
 265                         break;
 266                 case mm_32f_70_op:
 267                         func = -1;      /* Invalid */
 268                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 269                                 func = fmovn_op;
 270                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 271                                 func = fmovz_op;
 272                         if (func != -1) {
 273                                 mips32_insn.fp0_format.opcode = cop1_op;
 274                                 mips32_insn.fp0_format.fmt =
 275                                         sdps_format[insn.mm_fp0_format.fmt];
 276                                 mips32_insn.fp0_format.ft =
 277                                         insn.mm_fp0_format.ft;
 278                                 mips32_insn.fp0_format.fs =
 279                                         insn.mm_fp0_format.fs;
 280                                 mips32_insn.fp0_format.fd =
 281                                         insn.mm_fp0_format.fd;
 282                                 mips32_insn.fp0_format.func = func;
 283                         } else
 284                                 return SIGILL;
 285                         break;
 286                 case mm_32f_73_op:    /* POOL32FXF */
 287                         switch (insn.mm_fp1_format.op) {
 288                         case mm_movf0_op:
 289                         case mm_movf1_op:
 290                         case mm_movt0_op:
 291                         case mm_movt1_op:
 292                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 293                                     mm_movf0_op)
 294                                         op = 0;
 295                                 else
 296                                         op = 1;
 297                                 mips32_insn.r_format.opcode = spec_op;
 298                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 299                                 mips32_insn.r_format.rt =
 300                                         (insn.mm_fp4_format.cc << 2) + op;
 301                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 302                                 mips32_insn.r_format.re = 0;
 303                                 mips32_insn.r_format.func = movc_op;
 304                                 break;
 305                         case mm_fcvtd0_op:
 306                         case mm_fcvtd1_op:
 307                         case mm_fcvts0_op:
 308                         case mm_fcvts1_op:
 309                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 310                                     mm_fcvtd0_op) {
 311                                         func = fcvtd_op;
 312                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 313                                 } else {
 314                                         func = fcvts_op;
 315                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 316                                 }
 317                                 mips32_insn.fp0_format.opcode = cop1_op;
 318                                 mips32_insn.fp0_format.fmt = fmt;
 319                                 mips32_insn.fp0_format.ft = 0;
 320                                 mips32_insn.fp0_format.fs =
 321                                         insn.mm_fp3_format.fs;
 322                                 mips32_insn.fp0_format.fd =
 323                                         insn.mm_fp3_format.rt;
 324                                 mips32_insn.fp0_format.func = func;
 325                                 break;
 326                         case mm_fmov0_op:
 327                         case mm_fmov1_op:
 328                         case mm_fabs0_op:
 329                         case mm_fabs1_op:
 330                         case mm_fneg0_op:
 331                         case mm_fneg1_op:
 332                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 333                                     mm_fmov0_op)
 334                                         func = fmov_op;
 335                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 336                                          mm_fabs0_op)
 337                                         func = fabs_op;
 338                                 else
 339                                         func = fneg_op;
 340                                 mips32_insn.fp0_format.opcode = cop1_op;
 341                                 mips32_insn.fp0_format.fmt =
 342                                         sdps_format[insn.mm_fp3_format.fmt];
 343                                 mips32_insn.fp0_format.ft = 0;
 344                                 mips32_insn.fp0_format.fs =
 345                                         insn.mm_fp3_format.fs;
 346                                 mips32_insn.fp0_format.fd =
 347                                         insn.mm_fp3_format.rt;
 348                                 mips32_insn.fp0_format.func = func;
 349                                 break;
 350                         case mm_ffloorl_op:
 351                         case mm_ffloorw_op:
 352                         case mm_fceill_op:
 353                         case mm_fceilw_op:
 354                         case mm_ftruncl_op:
 355                         case mm_ftruncw_op:
 356                         case mm_froundl_op:
 357                         case mm_froundw_op:
 358                         case mm_fcvtl_op:
 359                         case mm_fcvtw_op:
 360                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 361                                         func = ffloorl_op;
 362                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 363                                         func = ffloor_op;
 364                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 365                                         func = fceill_op;
 366                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 367                                         func = fceil_op;
 368                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 369                                         func = ftruncl_op;
 370                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 371                                         func = ftrunc_op;
 372                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 373                                         func = froundl_op;
 374                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 375                                         func = fround_op;
 376                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 377                                         func = fcvtl_op;
 378                                 else
 379                                         func = fcvtw_op;
 380                                 mips32_insn.fp0_format.opcode = cop1_op;
 381                                 mips32_insn.fp0_format.fmt =
 382                                         sd_format[insn.mm_fp1_format.fmt];
 383                                 mips32_insn.fp0_format.ft = 0;
 384                                 mips32_insn.fp0_format.fs =
 385                                         insn.mm_fp1_format.fs;
 386                                 mips32_insn.fp0_format.fd =
 387                                         insn.mm_fp1_format.rt;
 388                                 mips32_insn.fp0_format.func = func;
 389                                 break;
 390                         case mm_frsqrt_op:
 391                         case mm_fsqrt_op:
 392                         case mm_frecip_op:
 393                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 394                                         func = frsqrt_op;
 395                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 396                                         func = fsqrt_op;
 397                                 else
 398                                         func = frecip_op;
 399                                 mips32_insn.fp0_format.opcode = cop1_op;
 400                                 mips32_insn.fp0_format.fmt =
 401                                         sdps_format[insn.mm_fp1_format.fmt];
 402                                 mips32_insn.fp0_format.ft = 0;
 403                                 mips32_insn.fp0_format.fs =
 404                                         insn.mm_fp1_format.fs;
 405                                 mips32_insn.fp0_format.fd =
 406                                         insn.mm_fp1_format.rt;
 407                                 mips32_insn.fp0_format.func = func;
 408                                 break;
 409                         case mm_mfc1_op:
 410                         case mm_mtc1_op:
 411                         case mm_cfc1_op:
 412                         case mm_ctc1_op:
 413                         case mm_mfhc1_op:
 414                         case mm_mthc1_op:
 415                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 416                                         op = mfc_op;
 417                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 418                                         op = mtc_op;
 419                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 420                                         op = cfc_op;
 421                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 422                                         op = ctc_op;
 423                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 424                                         op = mfhc_op;
 425                                 else
 426                                         op = mthc_op;
 427                                 mips32_insn.fp1_format.opcode = cop1_op;
 428                                 mips32_insn.fp1_format.op = op;
 429                                 mips32_insn.fp1_format.rt =
 430                                         insn.mm_fp1_format.rt;
 431                                 mips32_insn.fp1_format.fs =
 432                                         insn.mm_fp1_format.fs;
 433                                 mips32_insn.fp1_format.fd = 0;
 434                                 mips32_insn.fp1_format.func = 0;
 435                                 break;
 436                         default:
 437                                 return SIGILL;
 438                         }
 439                         break;
 440                 case mm_32f_74_op:      /* c.cond.fmt */
 441                         mips32_insn.fp0_format.opcode = cop1_op;
 442                         mips32_insn.fp0_format.fmt =
 443                                 sdps_format[insn.mm_fp4_format.fmt];
 444                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 445                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 446                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 447                         mips32_insn.fp0_format.func =
 448                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 449                         break;
 450                 default:
 451                         return SIGILL;
 452                 }
 453                 break;
 454         default:
 455                 return SIGILL;
 456         }
 457
 458         *insn_ptr = mips32_insn;
 459         return 0;
 460 }
 461
 462 int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 463                      unsigned long *contpc)
 464 {
 465         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 466         int bc_false = 0;
 467         unsigned int fcr31;
 468         unsigned int bit;
 469
 470         if (!cpu_has_mmips)
 471                 return 0;
 472
 473         switch (insn.mm_i_format.opcode) {
 474         case mm_pool32a_op:
 475                 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
 476                     mm_pool32axf_op) {
 477                         switch (insn.mm_i_format.simmediate >>
 478                                 MM_POOL32A_MINOR_SHIFT) {
 479                         case mm_jalr_op:
 480                         case mm_jalrhb_op:
 481                         case mm_jalrs_op:
 482                         case mm_jalrshb_op:
 483                                 if (insn.mm_i_format.rt != 0)   /* Not mm_jr */
 484                                         regs->regs[insn.mm_i_format.rt] =
 485                                                 regs->cp0_epc +
 486                                                 dec_insn.pc_inc +
 487                                                 dec_insn.next_pc_inc;
 488                                 *contpc = regs->regs[insn.mm_i_format.rs];
 489                                 return 1;
 490                         }
 491                 }
 492                 break;
 493         case mm_pool32i_op:
 494                 switch (insn.mm_i_format.rt) {
 495                 case mm_bltzals_op:
 496                 case mm_bltzal_op:
 497                         regs->regs[31] = regs->cp0_epc +
 498                                 dec_insn.pc_inc +
 499                                 dec_insn.next_pc_inc;
 500                         /* Fall through */
 501                 case mm_bltz_op:
 502                         if ((long)regs->regs[insn.mm_i_format.rs] < 0)
 503                                 *contpc = regs->cp0_epc +
 504                                         dec_insn.pc_inc +
 505                                         (insn.mm_i_format.simmediate << 1);
 506                         else
 507                                 *contpc = regs->cp0_epc +
 508                                         dec_insn.pc_inc +
 509                                         dec_insn.next_pc_inc;
 510                         return 1;
 511                 case mm_bgezals_op:
 512                 case mm_bgezal_op:
 513                         regs->regs[31] = regs->cp0_epc +
 514                                         dec_insn.pc_inc +
 515                                         dec_insn.next_pc_inc;
 516                         /* Fall through */
 517                 case mm_bgez_op:
 518                         if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
 519                                 *contpc = regs->cp0_epc +
 520                                         dec_insn.pc_inc +
 521                                         (insn.mm_i_format.simmediate << 1);
 522                         else
 523                                 *contpc = regs->cp0_epc +
 524                                         dec_insn.pc_inc +
 525                                         dec_insn.next_pc_inc;
 526                         return 1;
 527                 case mm_blez_op:
 528                         if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 529                                 *contpc = regs->cp0_epc +
 530                                         dec_insn.pc_inc +
 531                                         (insn.mm_i_format.simmediate << 1);
 532                         else
 533                                 *contpc = regs->cp0_epc +
 534                                         dec_insn.pc_inc +
 535                                         dec_insn.next_pc_inc;
 536                         return 1;
 537                 case mm_bgtz_op:
 538                         if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 539                                 *contpc = regs->cp0_epc +
 540                                         dec_insn.pc_inc +
 541                                         (insn.mm_i_format.simmediate << 1);
 542                         else
 543                                 *contpc = regs->cp0_epc +
 544                                         dec_insn.pc_inc +
 545                                         dec_insn.next_pc_inc;
 546                         return 1;
 547                 case mm_bc2f_op:
 548                 case mm_bc1f_op:
 549                         bc_false = 1;
 550                         /* Fall through */
 551                 case mm_bc2t_op:
 552                 case mm_bc1t_op:
 553                         preempt_disable();
 554                         if (is_fpu_owner())
 555                                 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
 556                         else
 557                                 fcr31 = current->thread.fpu.fcr31;
 558                         preempt_enable();
 559
 560                         if (bc_false)
 561                                 fcr31 = ~fcr31;
 562
 563                         bit = (insn.mm_i_format.rs >> 2);
 564                         bit += (bit != 0);
 565                         bit += 23;
 566                         if (fcr31 & (1 << bit))
 567                                 *contpc = regs->cp0_epc +
 568                                         dec_insn.pc_inc +
 569                                         (insn.mm_i_format.simmediate << 1);
 570                         else
 571                                 *contpc = regs->cp0_epc +
 572                                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 573                         return 1;
 574                 }
 575                 break;
 576         case mm_pool16c_op:
 577                 switch (insn.mm_i_format.rt) {
 578                 case mm_jalr16_op:
 579                 case mm_jalrs16_op:
 580                         regs->regs[31] = regs->cp0_epc +
 581                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 582                         /* Fall through */
 583                 case mm_jr16_op:
 584                         *contpc = regs->regs[insn.mm_i_format.rs];
 585                         return 1;
 586                 }
 587                 break;
 588         case mm_beqz16_op:
 589                 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
 590                         *contpc = regs->cp0_epc +
 591                                 dec_insn.pc_inc +
 592                                 (insn.mm_b1_format.simmediate << 1);
 593                 else
 594                         *contpc = regs->cp0_epc +
 595                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 596                 return 1;
 597         case mm_bnez16_op:
 598                 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
 599                         *contpc = regs->cp0_epc +
 600                                 dec_insn.pc_inc +
 601                                 (insn.mm_b1_format.simmediate << 1);
 602                 else
 603                         *contpc = regs->cp0_epc +
 604                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 605                 return 1;
 606         case mm_b16_op:
 607                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 608                          (insn.mm_b0_format.simmediate << 1);
 609                 return 1;
 610         case mm_beq32_op:
 611                 if (regs->regs[insn.mm_i_format.rs] ==
 612                     regs->regs[insn.mm_i_format.rt])
 613                         *contpc = regs->cp0_epc +
 614                                 dec_insn.pc_inc +
 615                                 (insn.mm_i_format.simmediate << 1);
 616                 else
 617                         *contpc = regs->cp0_epc +
 618                                 dec_insn.pc_inc +
 619                                 dec_insn.next_pc_inc;
 620                 return 1;
 621         case mm_bne32_op:
 622                 if (regs->regs[insn.mm_i_format.rs] !=
 623                     regs->regs[insn.mm_i_format.rt])
 624                         *contpc = regs->cp0_epc +
 625                                 dec_insn.pc_inc +
 626                                 (insn.mm_i_format.simmediate << 1);
 627                 else
 628                         *contpc = regs->cp0_epc +
 629                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 630                 return 1;
 631         case mm_jalx32_op:
 632                 regs->regs[31] = regs->cp0_epc +
 633                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 634                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 635                 *contpc >>= 28;
 636                 *contpc <<= 28;
 637                 *contpc |= (insn.j_format.target << 2);
 638                 return 1;
 639         case mm_jals32_op:
 640         case mm_jal32_op:
 641                 regs->regs[31] = regs->cp0_epc +
 642                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 643                 /* Fall through */
 644         case mm_j32_op:
 645                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 646                 *contpc >>= 27;
 647                 *contpc <<= 27;
 648                 *contpc |= (insn.j_format.target << 1);
 649                 set_isa16_mode(*contpc);
 650                 return 1;
 651         }
 652         return 0;
 653 }
 654
 655 /*
 656  * Redundant with logic already in kernel/branch.c,
 657  * embedded in compute_return_epc.  At some point,
 658  * a single subroutine should be used across both
 659  * modules.
 660  */
 661 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 662                          unsigned long *contpc)
 663 {
 664         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 665         unsigned int fcr31;
 666         unsigned int bit = 0;
 667
 668         switch (insn.i_format.opcode) {
 669         case spec_op:
 670                 switch (insn.r_format.func) {
 671                 case jalr_op:
 672                         regs->regs[insn.r_format.rd] =
 673                                 regs->cp0_epc + dec_insn.pc_inc +
 674                                 dec_insn.next_pc_inc;
 675                         /* Fall through */
 676                 case jr_op:
 677                         *contpc = regs->regs[insn.r_format.rs];
 678                         return 1;
 679                 }
 680                 break;
 681         case bcond_op:
 682                 switch (insn.i_format.rt) {
 683                 case bltzal_op:
 684                 case bltzall_op:
 685                         regs->regs[31] = regs->cp0_epc +
 686                                 dec_insn.pc_inc +
 687                                 dec_insn.next_pc_inc;
 688                         /* Fall through */
 689                 case bltz_op:
 690                 case bltzl_op:
 691                         if ((long)regs->regs[insn.i_format.rs] < 0)
 692                                 *contpc = regs->cp0_epc +
 693                                         dec_insn.pc_inc +
 694                                         (insn.i_format.simmediate << 2);
 695                         else
 696                                 *contpc = regs->cp0_epc +
 697                                         dec_insn.pc_inc +
 698                                         dec_insn.next_pc_inc;
 699                         return 1;
 700                 case bgezal_op:
 701                 case bgezall_op:
 702                         regs->regs[31] = regs->cp0_epc +
 703                                 dec_insn.pc_inc +
 704                                 dec_insn.next_pc_inc;
 705                         /* Fall through */
 706                 case bgez_op:
 707                 case bgezl_op:
 708                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 709                                 *contpc = regs->cp0_epc +
 710                                         dec_insn.pc_inc +
 711                                         (insn.i_format.simmediate << 2);
 712                         else
 713                                 *contpc = regs->cp0_epc +
 714                                         dec_insn.pc_inc +
 715                                         dec_insn.next_pc_inc;
 716                         return 1;
 717                 }
 718                 break;
 719         case jalx_op:
 720                 set_isa16_mode(bit);
 721         case jal_op:
 722                 regs->regs[31] = regs->cp0_epc +
 723                         dec_insn.pc_inc +
 724                         dec_insn.next_pc_inc;
 725                 /* Fall through */
 726         case j_op:
 727                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 728                 *contpc >>= 28;
 729                 *contpc <<= 28;
 730                 *contpc |= (insn.j_format.target << 2);
 731                 /* Set microMIPS mode bit: XOR for jalx. */
 732                 *contpc ^= bit;
 733                 return 1;
 734         case beq_op:
 735         case beql_op:
 736                 if (regs->regs[insn.i_format.rs] ==
 737                     regs->regs[insn.i_format.rt])
 738                         *contpc = regs->cp0_epc +
 739                                 dec_insn.pc_inc +
 740                                 (insn.i_format.simmediate << 2);
 741                 else
 742                         *contpc = regs->cp0_epc +
 743                                 dec_insn.pc_inc +
 744                                 dec_insn.next_pc_inc;
 745                 return 1;
 746         case bne_op:
 747         case bnel_op:
 748                 if (regs->regs[insn.i_format.rs] !=
 749                     regs->regs[insn.i_format.rt])
 750                         *contpc = regs->cp0_epc +
 751                                 dec_insn.pc_inc +
 752                                 (insn.i_format.simmediate << 2);
 753                 else
 754                         *contpc = regs->cp0_epc +
 755                                 dec_insn.pc_inc +
 756                                 dec_insn.next_pc_inc;
 757                 return 1;
 758         case blez_op:
 759         case blezl_op:
 760                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 761                         *contpc = regs->cp0_epc +
 762                                 dec_insn.pc_inc +
 763                                 (insn.i_format.simmediate << 2);
 764                 else
 765                         *contpc = regs->cp0_epc +
 766                                 dec_insn.pc_inc +
 767                                 dec_insn.next_pc_inc;
 768                 return 1;
 769         case bgtz_op:
 770         case bgtzl_op:
 771                 if ((long)regs->regs[insn.i_format.rs] > 0)
 772                         *contpc = regs->cp0_epc +
 773                                 dec_insn.pc_inc +
 774                                 (insn.i_format.simmediate << 2);
 775                 else
 776                         *contpc = regs->cp0_epc +
 777                                 dec_insn.pc_inc +
 778                                 dec_insn.next_pc_inc;
 779                 return 1;
 780 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 781         case lwc2_op: /* This is bbit0 on Octeon */
 782                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 783                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 784                 else
 785                         *contpc = regs->cp0_epc + 8;
 786                 return 1;
 787         case ldc2_op: /* This is bbit032 on Octeon */
 788                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 789                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 790                 else
 791                         *contpc = regs->cp0_epc + 8;
 792                 return 1;
 793         case swc2_op: /* This is bbit1 on Octeon */
 794                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 795                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 796                 else
 797                         *contpc = regs->cp0_epc + 8;
 798                 return 1;
 799         case sdc2_op: /* This is bbit132 on Octeon */
 800                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 801                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 802                 else
 803                         *contpc = regs->cp0_epc + 8;
 804                 return 1;
 805 #endif
 806         case cop0_op:
 807         case cop1_op:
 808         case cop2_op:
 809         case cop1x_op:
 810                 if (insn.i_format.rs == bc_op) {
 811                         preempt_disable();
 812                         if (is_fpu_owner())
 813                                 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
 814                         else
 815                                 fcr31 = current->thread.fpu.fcr31;
 816                         preempt_enable();
 817
 818                         bit = (insn.i_format.rt >> 2);
 819                         bit += (bit != 0);
 820                         bit += 23;
 821                         switch (insn.i_format.rt & 3) {
 822                         case 0: /* bc1f */
 823                         case 2: /* bc1fl */
 824                                 if (~fcr31 & (1 << bit))
 825                                         *contpc = regs->cp0_epc +
 826                                                 dec_insn.pc_inc +
 827                                                 (insn.i_format.simmediate << 2);
 828                                 else
 829                                         *contpc = regs->cp0_epc +
 830                                                 dec_insn.pc_inc +
 831                                                 dec_insn.next_pc_inc;
 832                                 return 1;
 833                         case 1: /* bc1t */
 834                         case 3: /* bc1tl */
 835                                 if (fcr31 & (1 << bit))
 836                                         *contpc = regs->cp0_epc +
 837                                                 dec_insn.pc_inc +
 838                                                 (insn.i_format.simmediate << 2);
 839                                 else
 840                                         *contpc = regs->cp0_epc +
 841                                                 dec_insn.pc_inc +
 842                                                 dec_insn.next_pc_inc;
 843                                 return 1;
 844                         }
 845                 }
 846                 break;
 847         }
 848         return 0;
 849 }
 850
 851 /*
 852  * In the Linux kernel, we support selection of FPR format on the
 853  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 854  * is hardwired to zero, which would imply a 32-bit FPU even for
 855  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 856  * FPU emu is slow and bulky and optimizing this function offers fairly
 857  * sizeable benefits so we try to be clever and make this function return
 858  * a constant whenever possible, that is on 64-bit kernels without O32
 859  * compatibility enabled and on 32-bit without 64-bit FPU support.
 860  */
 861 static inline int cop1_64bit(struct pt_regs *xcp)
 862 {
 863 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
 864         return 1;
 865 #elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
 866         return 0;
 867 #else
 868         return !test_thread_flag(TIF_32BIT_FPREGS);
 869 #endif
 870 }
 871
 872 #define SIFROMREG(si, x) do {                                           \
 873         if (cop1_64bit(xcp))                                            \
 874                 (si) = get_fpr32(&ctx->fpr[x], 0);                      \
 875         else                                                            \
 876                 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);         \
 877 } while (0)
 878
 879 #define SITOREG(si, x) do {                                             \
 880         if (cop1_64bit(xcp)) {                                          \
 881                 unsigned i;                                             \
 882                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 883                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 884                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 885         } else {                                                        \
 886                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 887         }                                                               \
 888 } while (0)
 889
 890 #define SIFROMHREG(si, x)       ((si) = get_fpr32(&ctx->fpr[x], 1))
 891
 892 #define SITOHREG(si, x) do {                                            \
 893         unsigned i;                                                     \
 894         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 895         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 896                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 897 } while (0)
 898
 899 #define DIFROMREG(di, x) \
 900         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 901
 902 #define DITOREG(di, x) do {                                             \
 903         unsigned fpr, i;                                                \
 904         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 905         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 906         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 907                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 908 } while (0)
 909
 910 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 911 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 912 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 913 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 914
 915 /*
 916  * Emulate the single floating point instruction pointed at by EPC.
 917  * Two instructions if the instruction is in a branch delay slot.
 918  */
 919
 920 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 921                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 922 {
 923         mips_instruction ir;
 924         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 925         unsigned int cond;
 926         int pc_inc;
 927
 928         /* XXX NEC Vr54xx bug workaround */
 929         if (delay_slot(xcp)) {
 930                 if (dec_insn.micro_mips_mode) {
 931                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 932                                 clear_delay_slot(xcp);
 933                 } else {
 934                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 935                                 clear_delay_slot(xcp);
 936                 }
 937         }
 938
 939         if (delay_slot(xcp)) {
 940                 /*
 941                  * The instruction to be emulated is in a branch delay slot
 942                  * which means that we have to  emulate the branch instruction
 943                  * BEFORE we do the cop1 instruction.
 944                  *
 945                  * This branch could be a COP1 branch, but in that case we
 946                  * would have had a trap for that instruction, and would not
 947                  * come through this route.
 948                  *
 949                  * Linux MIPS branch emulator operates on context, updating the
 950                  * cp0_epc.
 951                  */
 952                 ir = dec_insn.next_insn;  /* process delay slot instr */
 953                 pc_inc = dec_insn.next_pc_inc;
 954         } else {
 955                 ir = dec_insn.insn;       /* process current instr */
 956                 pc_inc = dec_insn.pc_inc;
 957         }
 958
 959         /*
 960          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 961          * instructions, we want to convert microMIPS FPU instructions
 962          * into MIPS32 instructions so that we could reuse all of the
 963          * FPU emulation code.
 964          *
 965          * NOTE: We cannot do this for branch instructions since they
 966          *       are not a subset. Example: Cannot emulate a 16-bit
 967          *       aligned target address with a MIPS32 instruction.
 968          */
 969         if (dec_insn.micro_mips_mode) {
 970                 /*
 971                  * If next instruction is a 16-bit instruction, then it
 972                  * it cannot be a FPU instruction. This could happen
 973                  * since we can be called for non-FPU instructions.
 974                  */
 975                 if ((pc_inc == 2) ||
 976                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 977                          == SIGILL))
 978                         return SIGILL;
 979         }
 980
 981       emul:
 982         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 983         MIPS_FPU_EMU_INC_STATS(emulated);
 984         switch (MIPSInst_OPCODE(ir)) {
 985         case ldc1_op:{
 986                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 987                         MIPSInst_SIMM(ir));
 988                 u64 val;
 989
 990                 MIPS_FPU_EMU_INC_STATS(loads);
 991
 992                 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
 993                         MIPS_FPU_EMU_INC_STATS(errors);
 994                         *fault_addr = va;
 995                         return SIGBUS;
 996                 }
 997                 if (__get_user(val, va)) {
 998                         MIPS_FPU_EMU_INC_STATS(errors);
 999                         *fault_addr = va;
1000                         return SIGSEGV;
1001                 }
1002                 DITOREG(val, MIPSInst_RT(ir));
1003                 break;
1004         }
1005
1006         case sdc1_op:{
1007                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1008                         MIPSInst_SIMM(ir));
1009                 u64 val;
1010
1011                 MIPS_FPU_EMU_INC_STATS(stores);
1012                 DIFROMREG(val, MIPSInst_RT(ir));
1013                 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1014                         MIPS_FPU_EMU_INC_STATS(errors);
1015                         *fault_addr = va;
1016                         return SIGBUS;
1017                 }
1018                 if (__put_user(val, va)) {
1019                         MIPS_FPU_EMU_INC_STATS(errors);
1020                         *fault_addr = va;
1021                         return SIGSEGV;
1022                 }
1023                 break;
1024         }
1025
1026         case lwc1_op:{
1027                 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1028                         MIPSInst_SIMM(ir));
1029                 u32 val;
1030
1031                 MIPS_FPU_EMU_INC_STATS(loads);
1032                 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1033                         MIPS_FPU_EMU_INC_STATS(errors);
1034                         *fault_addr = va;
1035                         return SIGBUS;
1036                 }
1037                 if (__get_user(val, va)) {
1038                         MIPS_FPU_EMU_INC_STATS(errors);
1039                         *fault_addr = va;
1040                         return SIGSEGV;
1041                 }
1042                 SITOREG(val, MIPSInst_RT(ir));
1043                 break;
1044         }
1045
1046         case swc1_op:{
1047                 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1048                         MIPSInst_SIMM(ir));
1049                 u32 val;
1050
1051                 MIPS_FPU_EMU_INC_STATS(stores);
1052                 SIFROMREG(val, MIPSInst_RT(ir));
1053                 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1054                         MIPS_FPU_EMU_INC_STATS(errors);
1055                         *fault_addr = va;
1056                         return SIGBUS;
1057                 }
1058                 if (__put_user(val, va)) {
1059                         MIPS_FPU_EMU_INC_STATS(errors);
1060                         *fault_addr = va;
1061                         return SIGSEGV;
1062                 }
1063                 break;
1064         }
1065
1066         case cop1_op:
1067                 switch (MIPSInst_RS(ir)) {
1068
1069 #if defined(__mips64)
1070                 case dmfc_op:
1071                         /* copregister fs -> gpr[rt] */
1072                         if (MIPSInst_RT(ir) != 0) {
1073                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1074                                         MIPSInst_RD(ir));
1075                         }
1076                         break;
1077
1078                 case dmtc_op:
1079                         /* copregister fs <- rt */
1080                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1081                         break;
1082 #endif
1083
1084                 case mfhc_op:
1085                         if (!cpu_has_mips_r2)
1086                                 goto sigill;
1087
1088                         /* copregister rd -> gpr[rt] */
1089                         if (MIPSInst_RT(ir) != 0) {
1090                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1091                                         MIPSInst_RD(ir));
1092                         }
1093                         break;
1094
1095                 case mthc_op:
1096                         if (!cpu_has_mips_r2)
1097                                 goto sigill;
1098
1099                         /* copregister rd <- gpr[rt] */
1100                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1101                         break;
1102
1103                 case mfc_op:
1104                         /* copregister rd -> gpr[rt] */
1105                         if (MIPSInst_RT(ir) != 0) {
1106                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1107                                         MIPSInst_RD(ir));
1108                         }
1109                         break;
1110
1111                 case mtc_op:
1112                         /* copregister rd <- rt */
1113                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1114                         break;
1115
1116                 case cfc_op:{
1117                         /* cop control register rd -> gpr[rt] */
1118                         u32 value;
1119
1120                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
1121                                 value = ctx->fcr31;
1122                                 value = (value & ~FPU_CSR_RM) |
1123                                         mips_rm[modeindex(value)];
1124 #ifdef CSRTRACE
1125                                 printk("%p gpr[%d]<-csr=%08x\n",
1126                                         (void *) (xcp->cp0_epc),
1127                                         MIPSInst_RT(ir), value);
1128 #endif
1129                         }
1130                         else if (MIPSInst_RD(ir) == FPCREG_RID)
1131                                 value = 0;
1132                         else
1133                                 value = 0;
1134                         if (MIPSInst_RT(ir))
1135                                 xcp->regs[MIPSInst_RT(ir)] = value;
1136                         break;
1137                 }
1138
1139                 case ctc_op:{
1140                         /* copregister rd <- rt */
1141                         u32 value;
1142
1143                         if (MIPSInst_RT(ir) == 0)
1144                                 value = 0;
1145                         else
1146                                 value = xcp->regs[MIPSInst_RT(ir)];
1147
1148                         /* we only have one writable control reg
1149                          */
1150                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
1151 #ifdef CSRTRACE
1152                                 printk("%p gpr[%d]->csr=%08x\n",
1153                                         (void *) (xcp->cp0_epc),
1154                                         MIPSInst_RT(ir), value);
1155 #endif
1156
1157                                 /*
1158                                  * Don't write reserved bits,
1159                                  * and convert to ieee library modes
1160                                  */
1161                                 ctx->fcr31 = (value &
1162                                                 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1163                                                 ieee_rm[modeindex(value)];
1164                         }
1165                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1166                                 return SIGFPE;
1167                         }
1168                         break;
1169                 }
1170
1171                 case bc_op:{
1172                         int likely = 0;
1173
1174                         if (delay_slot(xcp))
1175                                 return SIGILL;
1176
1177 #if __mips >= 4
1178                         cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1179 #else
1180                         cond = ctx->fcr31 & FPU_CSR_COND;
1181 #endif
1182                         switch (MIPSInst_RT(ir) & 3) {
1183                         case bcfl_op:
1184                                 likely = 1;
1185                         case bcf_op:
1186                                 cond = !cond;
1187                                 break;
1188                         case bctl_op:
1189                                 likely = 1;
1190                         case bct_op:
1191                                 break;
1192                         default:
1193                                 /* thats an illegal instruction */
1194                                 return SIGILL;
1195                         }
1196
1197                         set_delay_slot(xcp);
1198                         if (cond) {
1199                                 /* branch taken: emulate dslot
1200                                  * instruction
1201                                  */
1202                                 xcp->cp0_epc += dec_insn.pc_inc;
1203
1204                                 contpc = MIPSInst_SIMM(ir);
1205                                 ir = dec_insn.next_insn;
1206                                 if (dec_insn.micro_mips_mode) {
1207                                         contpc = (xcp->cp0_epc + (contpc << 1));
1208
1209                                         /* If 16-bit instruction, not FPU. */
1210                                         if ((dec_insn.next_pc_inc == 2) ||
1211                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1212
1213                                                 /*
1214                                                  * Since this instruction will
1215                                                  * be put on the stack with
1216                                                  * 32-bit words, get around
1217                                                  * this problem by putting a
1218                                                  * NOP16 as the second one.
1219                                                  */
1220                                                 if (dec_insn.next_pc_inc == 2)
1221                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1222
1223                                                 /*
1224                                                  * Single step the non-CP1
1225                                                  * instruction in the dslot.
1226                                                  */
1227                                                 return mips_dsemul(xcp, ir, contpc);
1228                                         }
1229                                 } else
1230                                         contpc = (xcp->cp0_epc + (contpc << 2));
1231
1232                                 switch (MIPSInst_OPCODE(ir)) {
1233                                 case lwc1_op:
1234                                 case swc1_op:
1235 #if (__mips >= 2 || defined(__mips64))
1236                                 case ldc1_op:
1237                                 case sdc1_op:
1238 #endif
1239                                 case cop1_op:
1240 #if __mips >= 4 && __mips != 32
1241                                 case cop1x_op:
1242 #endif
1243                                         /* its one of ours */
1244                                         goto emul;
1245 #if __mips >= 4
1246                                 case spec_op:
1247                                         if (MIPSInst_FUNC(ir) == movc_op)
1248                                                 goto emul;
1249                                         break;
1250 #endif
1251                                 }
1252
1253                                 /*
1254                                  * Single step the non-cp1
1255                                  * instruction in the dslot
1256                                  */
1257                                 return mips_dsemul(xcp, ir, contpc);
1258                         }
1259                         else {
1260                                 /* branch not taken */
1261                                 if (likely) {
1262                                         /*
1263                                          * branch likely nullifies
1264                                          * dslot if not taken
1265                                          */
1266                                         xcp->cp0_epc += dec_insn.pc_inc;
1267                                         contpc += dec_insn.pc_inc;
1268                                         /*
1269                                          * else continue & execute
1270                                          * dslot as normal insn
1271                                          */
1272                                 }
1273                         }
1274                         break;
1275                 }
1276
1277                 default:
1278                         if (!(MIPSInst_RS(ir) & 0x10))
1279                                 return SIGILL;
1280                         {
1281                                 int sig;
1282
1283                                 /* a real fpu computation instruction */
1284                                 if ((sig = fpu_emu(xcp, ctx, ir)))
1285                                         return sig;
1286                         }
1287                 }
1288                 break;
1289
1290 #if __mips >= 4 && __mips != 32
1291         case cop1x_op:{
1292                 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1293                 if (sig)
1294                         return sig;
1295                 break;
1296         }
1297 #endif
1298
1299 #if __mips >= 4
1300         case spec_op:
1301                 if (MIPSInst_FUNC(ir) != movc_op)
1302                         return SIGILL;
1303                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1304                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1305                         xcp->regs[MIPSInst_RD(ir)] =
1306                                 xcp->regs[MIPSInst_RS(ir)];
1307                 break;
1308 #endif
1309
1310         default:
1311 sigill:
1312                 return SIGILL;
1313         }
1314
1315         /* we did it !! */
1316         xcp->cp0_epc = contpc;
1317         clear_delay_slot(xcp);
1318
1319         return 0;
1320 }
1321
1322 /*
1323  * Conversion table from MIPS compare ops 48-63
1324  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1325  */
1326 static const unsigned char cmptab[8] = {
1327         0,                      /* cmp_0 (sig) cmp_sf */
1328         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1329         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1330         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1331         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1332         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1333         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1334         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1335 };
1336
1337
1338 #if __mips >= 4 && __mips != 32
1339
1340 /*
1341  * Additional MIPS4 instructions
1342  */
1343
1344 #define DEF3OP(name, p, f1, f2, f3) \
1345 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, union ieee754##p s, \
1346     union ieee754##p t) \
1347 { \
1348         struct _ieee754_csr ieee754_csr_save; \
1349         s = f1(s, t); \
1350         ieee754_csr_save = ieee754_csr; \
1351         s = f2(s, r); \
1352         ieee754_csr_save.cx |= ieee754_csr.cx; \
1353         ieee754_csr_save.sx |= ieee754_csr.sx; \
1354         s = f3(s); \
1355         ieee754_csr.cx |= ieee754_csr_save.cx; \
1356         ieee754_csr.sx |= ieee754_csr_save.sx; \
1357         return s; \
1358 }
1359
1360 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1361 {
1362         return ieee754dp_div(ieee754dp_one(0), d);
1363 }
1364
1365 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1366 {
1367         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1368 }
1369
1370 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1371 {
1372         return ieee754sp_div(ieee754sp_one(0), s);
1373 }
1374
1375 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1376 {
1377         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1378 }
1379
1380 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1381 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1382 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1383 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1384 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1385 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1386 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1387 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1388
1389 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1390         mips_instruction ir, void *__user *fault_addr)
1391 {
1392         unsigned rcsr = 0;      /* resulting csr */
1393
1394         MIPS_FPU_EMU_INC_STATS(cp1xops);
1395
1396         switch (MIPSInst_FMA_FFMT(ir)) {
1397         case s_fmt:{            /* 0 */
1398
1399                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1400                 union ieee754sp fd, fr, fs, ft;
1401                 u32 __user *va;
1402                 u32 val;
1403
1404                 switch (MIPSInst_FUNC(ir)) {
1405                 case lwxc1_op:
1406                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1407                                 xcp->regs[MIPSInst_FT(ir)]);
1408
1409                         MIPS_FPU_EMU_INC_STATS(loads);
1410                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1411                                 MIPS_FPU_EMU_INC_STATS(errors);
1412                                 *fault_addr = va;
1413                                 return SIGBUS;
1414                         }
1415                         if (__get_user(val, va)) {
1416                                 MIPS_FPU_EMU_INC_STATS(errors);
1417                                 *fault_addr = va;
1418                                 return SIGSEGV;
1419                         }
1420                         SITOREG(val, MIPSInst_FD(ir));
1421                         break;
1422
1423                 case swxc1_op:
1424                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1425                                 xcp->regs[MIPSInst_FT(ir)]);
1426
1427                         MIPS_FPU_EMU_INC_STATS(stores);
1428
1429                         SIFROMREG(val, MIPSInst_FS(ir));
1430                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1431                                 MIPS_FPU_EMU_INC_STATS(errors);
1432                                 *fault_addr = va;
1433                                 return SIGBUS;
1434                         }
1435                         if (put_user(val, va)) {
1436                                 MIPS_FPU_EMU_INC_STATS(errors);
1437                                 *fault_addr = va;
1438                                 return SIGSEGV;
1439                         }
1440                         break;
1441
1442                 case madd_s_op:
1443                         handler = fpemu_sp_madd;
1444                         goto scoptop;
1445                 case msub_s_op:
1446                         handler = fpemu_sp_msub;
1447                         goto scoptop;
1448                 case nmadd_s_op:
1449                         handler = fpemu_sp_nmadd;
1450                         goto scoptop;
1451                 case nmsub_s_op:
1452                         handler = fpemu_sp_nmsub;
1453                         goto scoptop;
1454
1455                       scoptop:
1456                         SPFROMREG(fr, MIPSInst_FR(ir));
1457                         SPFROMREG(fs, MIPSInst_FS(ir));
1458                         SPFROMREG(ft, MIPSInst_FT(ir));
1459                         fd = (*handler) (fr, fs, ft);
1460                         SPTOREG(fd, MIPSInst_FD(ir));
1461
1462                       copcsr:
1463                         if (ieee754_cxtest(IEEE754_INEXACT))
1464                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1465                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
1466                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1467                         if (ieee754_cxtest(IEEE754_OVERFLOW))
1468                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1469                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1470                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1471
1472                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1473                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1474                                 /*printk ("SIGFPE: fpu csr = %08x\n",
1475                                    ctx->fcr31); */
1476                                 return SIGFPE;
1477                         }
1478
1479                         break;
1480
1481                 default:
1482                         return SIGILL;
1483                 }
1484                 break;
1485         }
1486
1487         case d_fmt:{            /* 1 */
1488                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1489                 union ieee754dp fd, fr, fs, ft;
1490                 u64 __user *va;
1491                 u64 val;
1492
1493                 switch (MIPSInst_FUNC(ir)) {
1494                 case ldxc1_op:
1495                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1496                                 xcp->regs[MIPSInst_FT(ir)]);
1497
1498                         MIPS_FPU_EMU_INC_STATS(loads);
1499                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1500                                 MIPS_FPU_EMU_INC_STATS(errors);
1501                                 *fault_addr = va;
1502                                 return SIGBUS;
1503                         }
1504                         if (__get_user(val, va)) {
1505                                 MIPS_FPU_EMU_INC_STATS(errors);
1506                                 *fault_addr = va;
1507                                 return SIGSEGV;
1508                         }
1509                         DITOREG(val, MIPSInst_FD(ir));
1510                         break;
1511
1512                 case sdxc1_op:
1513                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1514                                 xcp->regs[MIPSInst_FT(ir)]);
1515
1516                         MIPS_FPU_EMU_INC_STATS(stores);
1517                         DIFROMREG(val, MIPSInst_FS(ir));
1518                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1519                                 MIPS_FPU_EMU_INC_STATS(errors);
1520                                 *fault_addr = va;
1521                                 return SIGBUS;
1522                         }
1523                         if (__put_user(val, va)) {
1524                                 MIPS_FPU_EMU_INC_STATS(errors);
1525                                 *fault_addr = va;
1526                                 return SIGSEGV;
1527                         }
1528                         break;
1529
1530                 case madd_d_op:
1531                         handler = fpemu_dp_madd;
1532                         goto dcoptop;
1533                 case msub_d_op:
1534                         handler = fpemu_dp_msub;
1535                         goto dcoptop;
1536                 case nmadd_d_op:
1537                         handler = fpemu_dp_nmadd;
1538                         goto dcoptop;
1539                 case nmsub_d_op:
1540                         handler = fpemu_dp_nmsub;
1541                         goto dcoptop;
1542
1543                       dcoptop:
1544                         DPFROMREG(fr, MIPSInst_FR(ir));
1545                         DPFROMREG(fs, MIPSInst_FS(ir));
1546                         DPFROMREG(ft, MIPSInst_FT(ir));
1547                         fd = (*handler) (fr, fs, ft);
1548                         DPTOREG(fd, MIPSInst_FD(ir));
1549                         goto copcsr;
1550
1551                 default:
1552                         return SIGILL;
1553                 }
1554                 break;
1555         }
1556
1557         case 0x3:
1558                 if (MIPSInst_FUNC(ir) != pfetch_op)
1559                         return SIGILL;
1560
1561                 /* ignore prefx operation */
1562                 break;
1563
1564         default:
1565                 return SIGILL;
1566         }
1567
1568         return 0;
1569 }
1570 #endif
1571
1572
1573
1574 /*
1575  * Emulate a single COP1 arithmetic instruction.
1576  */
1577 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1578         mips_instruction ir)
1579 {
1580         int rfmt;               /* resulting format */
1581         unsigned rcsr = 0;      /* resulting csr */
1582         unsigned cond;
1583         union {
1584                 union ieee754dp d;
1585                 union ieee754sp s;
1586                 int w;
1587 #ifdef __mips64
1588                 s64 l;
1589 #endif
1590         } rv;                   /* resulting value */
1591
1592         MIPS_FPU_EMU_INC_STATS(cp1ops);
1593         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1594         case s_fmt:{            /* 0 */
1595                 union {
1596                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1597                         union ieee754sp(*u) (union ieee754sp);
1598                 } handler;
1599
1600                 switch (MIPSInst_FUNC(ir)) {
1601                         /* binary ops */
1602                 case fadd_op:
1603                         handler.b = ieee754sp_add;
1604                         goto scopbop;
1605                 case fsub_op:
1606                         handler.b = ieee754sp_sub;
1607                         goto scopbop;
1608                 case fmul_op:
1609                         handler.b = ieee754sp_mul;
1610                         goto scopbop;
1611                 case fdiv_op:
1612                         handler.b = ieee754sp_div;
1613                         goto scopbop;
1614
1615                         /* unary  ops */
1616 #if __mips >= 2 || defined(__mips64)
1617                 case fsqrt_op:
1618                         handler.u = ieee754sp_sqrt;
1619                         goto scopuop;
1620 #endif
1621 #if __mips >= 4 && __mips != 32
1622                 case frsqrt_op:
1623                         handler.u = fpemu_sp_rsqrt;
1624                         goto scopuop;
1625                 case frecip_op:
1626                         handler.u = fpemu_sp_recip;
1627                         goto scopuop;
1628 #endif
1629 #if __mips >= 4
1630                 case fmovc_op:
1631                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1632                         if (((ctx->fcr31 & cond) != 0) !=
1633                                 ((MIPSInst_FT(ir) & 1) != 0))
1634                                 return 0;
1635                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1636                         break;
1637                 case fmovz_op:
1638                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1639                                 return 0;
1640                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1641                         break;
1642                 case fmovn_op:
1643                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1644                                 return 0;
1645                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1646                         break;
1647 #endif
1648                 case fabs_op:
1649                         handler.u = ieee754sp_abs;
1650                         goto scopuop;
1651                 case fneg_op:
1652                         handler.u = ieee754sp_neg;
1653                         goto scopuop;
1654                 case fmov_op:
1655                         /* an easy one */
1656                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1657                         goto copcsr;
1658
1659                         /* binary op on handler */
1660                       scopbop:
1661                         {
1662                                 union ieee754sp fs, ft;
1663
1664                                 SPFROMREG(fs, MIPSInst_FS(ir));
1665                                 SPFROMREG(ft, MIPSInst_FT(ir));
1666
1667                                 rv.s = (*handler.b) (fs, ft);
1668                                 goto copcsr;
1669                         }
1670                       scopuop:
1671                         {
1672                                 union ieee754sp fs;
1673
1674                                 SPFROMREG(fs, MIPSInst_FS(ir));
1675                                 rv.s = (*handler.u) (fs);
1676                                 goto copcsr;
1677                         }
1678                       copcsr:
1679                         if (ieee754_cxtest(IEEE754_INEXACT))
1680                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1681                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
1682                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1683                         if (ieee754_cxtest(IEEE754_OVERFLOW))
1684                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1685                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1686                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1687                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1688                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1689                         break;
1690
1691                         /* unary conv ops */
1692                 case fcvts_op:
1693                         return SIGILL;  /* not defined */
1694                 case fcvtd_op:{
1695                         union ieee754sp fs;
1696
1697                         SPFROMREG(fs, MIPSInst_FS(ir));
1698                         rv.d = ieee754dp_fsp(fs);
1699                         rfmt = d_fmt;
1700                         goto copcsr;
1701                 }
1702                 case fcvtw_op:{
1703                         union ieee754sp fs;
1704
1705                         SPFROMREG(fs, MIPSInst_FS(ir));
1706                         rv.w = ieee754sp_tint(fs);
1707                         rfmt = w_fmt;
1708                         goto copcsr;
1709                 }
1710
1711 #if __mips >= 2 || defined(__mips64)
1712                 case fround_op:
1713                 case ftrunc_op:
1714                 case fceil_op:
1715                 case ffloor_op:{
1716                         unsigned int oldrm = ieee754_csr.rm;
1717                         union ieee754sp fs;
1718
1719                         SPFROMREG(fs, MIPSInst_FS(ir));
1720                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1721                         rv.w = ieee754sp_tint(fs);
1722                         ieee754_csr.rm = oldrm;
1723                         rfmt = w_fmt;
1724                         goto copcsr;
1725                 }
1726 #endif /* __mips >= 2 */
1727
1728 #if defined(__mips64)
1729                 case fcvtl_op:{
1730                         union ieee754sp fs;
1731
1732                         SPFROMREG(fs, MIPSInst_FS(ir));
1733                         rv.l = ieee754sp_tlong(fs);
1734                         rfmt = l_fmt;
1735                         goto copcsr;
1736                 }
1737
1738                 case froundl_op:
1739                 case ftruncl_op:
1740                 case fceill_op:
1741                 case ffloorl_op:{
1742                         unsigned int oldrm = ieee754_csr.rm;
1743                         union ieee754sp fs;
1744
1745                         SPFROMREG(fs, MIPSInst_FS(ir));
1746                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1747                         rv.l = ieee754sp_tlong(fs);
1748                         ieee754_csr.rm = oldrm;
1749                         rfmt = l_fmt;
1750                         goto copcsr;
1751                 }
1752 #endif /* defined(__mips64) */
1753
1754                 default:
1755                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1756                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1757                                 union ieee754sp fs, ft;
1758
1759                                 SPFROMREG(fs, MIPSInst_FS(ir));
1760                                 SPFROMREG(ft, MIPSInst_FT(ir));
1761                                 rv.w = ieee754sp_cmp(fs, ft,
1762                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1763                                 rfmt = -1;
1764                                 if ((cmpop & 0x8) && ieee754_cxtest
1765                                         (IEEE754_INVALID_OPERATION))
1766                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1767                                 else
1768                                         goto copcsr;
1769
1770                         }
1771                         else {
1772                                 return SIGILL;
1773                         }
1774                         break;
1775                 }
1776                 break;
1777         }
1778
1779         case d_fmt:{
1780                 union {
1781                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1782                         union ieee754dp(*u) (union ieee754dp);
1783                 } handler;
1784
1785                 switch (MIPSInst_FUNC(ir)) {
1786                         /* binary ops */
1787                 case fadd_op:
1788                         handler.b = ieee754dp_add;
1789                         goto dcopbop;
1790                 case fsub_op:
1791                         handler.b = ieee754dp_sub;
1792                         goto dcopbop;
1793                 case fmul_op:
1794                         handler.b = ieee754dp_mul;
1795                         goto dcopbop;
1796                 case fdiv_op:
1797                         handler.b = ieee754dp_div;
1798                         goto dcopbop;
1799
1800                         /* unary  ops */
1801 #if __mips >= 2 || defined(__mips64)
1802                 case fsqrt_op:
1803                         handler.u = ieee754dp_sqrt;
1804                         goto dcopuop;
1805 #endif
1806 #if __mips >= 4 && __mips != 32
1807                 case frsqrt_op:
1808                         handler.u = fpemu_dp_rsqrt;
1809                         goto dcopuop;
1810                 case frecip_op:
1811                         handler.u = fpemu_dp_recip;
1812                         goto dcopuop;
1813 #endif
1814 #if __mips >= 4
1815                 case fmovc_op:
1816                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1817                         if (((ctx->fcr31 & cond) != 0) !=
1818                                 ((MIPSInst_FT(ir) & 1) != 0))
1819                                 return 0;
1820                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1821                         break;
1822                 case fmovz_op:
1823                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1824                                 return 0;
1825                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1826                         break;
1827                 case fmovn_op:
1828                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1829                                 return 0;
1830                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1831                         break;
1832 #endif
1833                 case fabs_op:
1834                         handler.u = ieee754dp_abs;
1835                         goto dcopuop;
1836
1837                 case fneg_op:
1838                         handler.u = ieee754dp_neg;
1839                         goto dcopuop;
1840
1841                 case fmov_op:
1842                         /* an easy one */
1843                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1844                         goto copcsr;
1845
1846                         /* binary op on handler */
1847                       dcopbop:{
1848                                 union ieee754dp fs, ft;
1849
1850                                 DPFROMREG(fs, MIPSInst_FS(ir));
1851                                 DPFROMREG(ft, MIPSInst_FT(ir));
1852
1853                                 rv.d = (*handler.b) (fs, ft);
1854                                 goto copcsr;
1855                         }
1856                       dcopuop:{
1857                                 union ieee754dp fs;
1858
1859                                 DPFROMREG(fs, MIPSInst_FS(ir));
1860                                 rv.d = (*handler.u) (fs);
1861                                 goto copcsr;
1862                         }
1863
1864                         /* unary conv ops */
1865                 case fcvts_op:{
1866                         union ieee754dp fs;
1867
1868                         DPFROMREG(fs, MIPSInst_FS(ir));
1869                         rv.s = ieee754sp_fdp(fs);
1870                         rfmt = s_fmt;
1871                         goto copcsr;
1872                 }
1873                 case fcvtd_op:
1874                         return SIGILL;  /* not defined */
1875
1876                 case fcvtw_op:{
1877                         union ieee754dp fs;
1878
1879                         DPFROMREG(fs, MIPSInst_FS(ir));
1880                         rv.w = ieee754dp_tint(fs);      /* wrong */
1881                         rfmt = w_fmt;
1882                         goto copcsr;
1883                 }
1884
1885 #if __mips >= 2 || defined(__mips64)
1886                 case fround_op:
1887                 case ftrunc_op:
1888                 case fceil_op:
1889                 case ffloor_op:{
1890                         unsigned int oldrm = ieee754_csr.rm;
1891                         union ieee754dp fs;
1892
1893                         DPFROMREG(fs, MIPSInst_FS(ir));
1894                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1895                         rv.w = ieee754dp_tint(fs);
1896                         ieee754_csr.rm = oldrm;
1897                         rfmt = w_fmt;
1898                         goto copcsr;
1899                 }
1900 #endif
1901
1902 #if defined(__mips64)
1903                 case fcvtl_op:{
1904                         union ieee754dp fs;
1905
1906                         DPFROMREG(fs, MIPSInst_FS(ir));
1907                         rv.l = ieee754dp_tlong(fs);
1908                         rfmt = l_fmt;
1909                         goto copcsr;
1910                 }
1911
1912                 case froundl_op:
1913                 case ftruncl_op:
1914                 case fceill_op:
1915                 case ffloorl_op:{
1916                         unsigned int oldrm = ieee754_csr.rm;
1917                         union ieee754dp fs;
1918
1919                         DPFROMREG(fs, MIPSInst_FS(ir));
1920                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1921                         rv.l = ieee754dp_tlong(fs);
1922                         ieee754_csr.rm = oldrm;
1923                         rfmt = l_fmt;
1924                         goto copcsr;
1925                 }
1926 #endif /* __mips >= 3 */
1927
1928                 default:
1929                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1930                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1931                                 union ieee754dp fs, ft;
1932
1933                                 DPFROMREG(fs, MIPSInst_FS(ir));
1934                                 DPFROMREG(ft, MIPSInst_FT(ir));
1935                                 rv.w = ieee754dp_cmp(fs, ft,
1936                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1937                                 rfmt = -1;
1938                                 if ((cmpop & 0x8)
1939                                         &&
1940                                         ieee754_cxtest
1941                                         (IEEE754_INVALID_OPERATION))
1942                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1943                                 else
1944                                         goto copcsr;
1945
1946                         }
1947                         else {
1948                                 return SIGILL;
1949                         }
1950                         break;
1951                 }
1952                 break;
1953         }
1954
1955         case w_fmt:{
1956                 union ieee754sp fs;
1957
1958                 switch (MIPSInst_FUNC(ir)) {
1959                 case fcvts_op:
1960                         /* convert word to single precision real */
1961                         SPFROMREG(fs, MIPSInst_FS(ir));
1962                         rv.s = ieee754sp_fint(fs.bits);
1963                         rfmt = s_fmt;
1964                         goto copcsr;
1965                 case fcvtd_op:
1966                         /* convert word to double precision real */
1967                         SPFROMREG(fs, MIPSInst_FS(ir));
1968                         rv.d = ieee754dp_fint(fs.bits);
1969                         rfmt = d_fmt;
1970                         goto copcsr;
1971                 default:
1972                         return SIGILL;
1973                 }
1974                 break;
1975         }
1976
1977 #if defined(__mips64)
1978         case l_fmt:{
1979                 u64 bits;
1980                 DIFROMREG(bits, MIPSInst_FS(ir));
1981
1982                 switch (MIPSInst_FUNC(ir)) {
1983                 case fcvts_op:
1984                         /* convert long to single precision real */
1985                         rv.s = ieee754sp_flong(bits);
1986                         rfmt = s_fmt;
1987                         goto copcsr;
1988                 case fcvtd_op:
1989                         /* convert long to double precision real */
1990                         rv.d = ieee754dp_flong(bits);
1991                         rfmt = d_fmt;
1992                         goto copcsr;
1993                 default:
1994                         return SIGILL;
1995                 }
1996                 break;
1997         }
1998 #endif
1999
2000         default:
2001                 return SIGILL;
2002         }
2003
2004         /*
2005          * Update the fpu CSR register for this operation.
2006          * If an exception is required, generate a tidy SIGFPE exception,
2007          * without updating the result register.
2008          * Note: cause exception bits do not accumulate, they are rewritten
2009          * for each op; only the flag/sticky bits accumulate.
2010          */
2011         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2012         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2013                 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
2014                 return SIGFPE;
2015         }
2016
2017         /*
2018          * Now we can safely write the result back to the register file.
2019          */
2020         switch (rfmt) {
2021         case -1:{
2022 #if __mips >= 4
2023                 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
2024 #else
2025                 cond = FPU_CSR_COND;
2026 #endif
2027                 if (rv.w)
2028                         ctx->fcr31 |= cond;
2029                 else
2030                         ctx->fcr31 &= ~cond;
2031                 break;
2032         }
2033         case d_fmt:
2034                 DPTOREG(rv.d, MIPSInst_FD(ir));
2035                 break;
2036         case s_fmt:
2037                 SPTOREG(rv.s, MIPSInst_FD(ir));
2038                 break;
2039         case w_fmt:
2040                 SITOREG(rv.w, MIPSInst_FD(ir));
2041                 break;
2042 #if defined(__mips64)
2043         case l_fmt:
2044                 DITOREG(rv.l, MIPSInst_FD(ir));
2045                 break;
2046 #endif
2047         default:
2048                 return SIGILL;
2049         }
2050
2051         return 0;
2052 }
2053
2054 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2055         int has_fpu, void *__user *fault_addr)
2056 {
2057         unsigned long oldepc, prevepc;
2058         struct mm_decoded_insn dec_insn;
2059         u16 instr[4];
2060         u16 *instr_ptr;
2061         int sig = 0;
2062
2063         oldepc = xcp->cp0_epc;
2064         do {
2065                 prevepc = xcp->cp0_epc;
2066
2067                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2068                         /*
2069                          * Get next 2 microMIPS instructions and convert them
2070                          * into 32-bit instructions.
2071                          */
2072                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2073                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2074                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2075                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2076                                 MIPS_FPU_EMU_INC_STATS(errors);
2077                                 return SIGBUS;
2078                         }
2079                         instr_ptr = instr;
2080
2081                         /* Get first instruction. */
2082                         if (mm_insn_16bit(*instr_ptr)) {
2083                                 /* Duplicate the half-word. */
2084                                 dec_insn.insn = (*instr_ptr << 16) |
2085                                         (*instr_ptr);
2086                                 /* 16-bit instruction. */
2087                                 dec_insn.pc_inc = 2;
2088                                 instr_ptr += 1;
2089                         } else {
2090                                 dec_insn.insn = (*instr_ptr << 16) |
2091                                         *(instr_ptr+1);
2092                                 /* 32-bit instruction. */
2093                                 dec_insn.pc_inc = 4;
2094                                 instr_ptr += 2;
2095                         }
2096                         /* Get second instruction. */
2097                         if (mm_insn_16bit(*instr_ptr)) {
2098                                 /* Duplicate the half-word. */
2099                                 dec_insn.next_insn = (*instr_ptr << 16) |
2100                                         (*instr_ptr);
2101                                 /* 16-bit instruction. */
2102                                 dec_insn.next_pc_inc = 2;
2103                         } else {
2104                                 dec_insn.next_insn = (*instr_ptr << 16) |
2105                                         *(instr_ptr+1);
2106                                 /* 32-bit instruction. */
2107                                 dec_insn.next_pc_inc = 4;
2108                         }
2109                         dec_insn.micro_mips_mode = 1;
2110                 } else {
2111                         if ((get_user(dec_insn.insn,
2112                             (mips_instruction __user *) xcp->cp0_epc)) ||
2113                             (get_user(dec_insn.next_insn,
2114                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2115                                 MIPS_FPU_EMU_INC_STATS(errors);
2116                                 return SIGBUS;
2117                         }
2118                         dec_insn.pc_inc = 4;
2119                         dec_insn.next_pc_inc = 4;
2120                         dec_insn.micro_mips_mode = 0;
2121                 }
2122
2123                 if ((dec_insn.insn == 0) ||
2124                    ((dec_insn.pc_inc == 2) &&
2125                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2126                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2127                 else {
2128                         /*
2129                          * The 'ieee754_csr' is an alias of
2130                          * ctx->fcr31.  No need to copy ctx->fcr31 to
2131                          * ieee754_csr.  But ieee754_csr.rm is ieee
2132                          * library modes. (not mips rounding mode)
2133                          */
2134                         /* convert to ieee library modes */
2135                         ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
2136                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2137                         /* revert to mips rounding mode */
2138                         ieee754_csr.rm = mips_rm[ieee754_csr.rm];
2139                 }
2140
2141                 if (has_fpu)
2142                         break;
2143                 if (sig)
2144                         break;
2145
2146                 cond_resched();
2147         } while (xcp->cp0_epc > prevepc);
2148
2149         /* SIGILL indicates a non-fpu instruction */
2150         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2151                 /* but if epc has advanced, then ignore it */
2152                 sig = 0;
2153
2154         return sig;
2155 }