arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/kconfig.h>
  39 #include <linux/percpu-defs.h>
  40 #include <linux/perf_event.h>
  41
  42 #include <asm/branch.h>
  43 #include <asm/inst.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/uaccess.h>
  47
  48 #include <asm/processor.h>
  49 #include <asm/fpu_emulator.h>
  50 #include <asm/fpu.h>
  51
  52 #include "ieee754.h"
  53
  54 /* Function which emulates a floating point instruction. */
  55
  56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  57         mips_instruction);
  58
  59 static int fpux_emu(struct pt_regs *,
  60         struct mips_fpu_struct *, mips_instruction, void *__user *);
  61
  62 /* Control registers */
  63
  64 #define FPCREG_RID      0       /* $0  = revision id */
  65 #define FPCREG_CSR      31      /* $31 = csr */
  66
  67 /* Determine rounding mode from the RM bits of the FCSR */
  68 #define modeindex(v) ((v) & FPU_CSR_RM)
  69
  70 /* Convert MIPS rounding mode (0..3) to IEEE library modes. */
  71 static const unsigned char ieee_rm[4] = {
  72         [FPU_CSR_RN] = IEEE754_RN,
  73         [FPU_CSR_RZ] = IEEE754_RZ,
  74         [FPU_CSR_RU] = IEEE754_RU,
  75         [FPU_CSR_RD] = IEEE754_RD,
  76 };
  77 /* Convert IEEE library modes to MIPS rounding mode (0..3). */
  78 static const unsigned char mips_rm[4] = {
  79         [IEEE754_RN] = FPU_CSR_RN,
  80         [IEEE754_RZ] = FPU_CSR_RZ,
  81         [IEEE754_RD] = FPU_CSR_RD,
  82         [IEEE754_RU] = FPU_CSR_RU,
  83 };
  84
  85 /* convert condition code register number to csr bit */
  86 static const unsigned int fpucondbit[8] = {
  87         FPU_CSR_COND0,
  88         FPU_CSR_COND1,
  89         FPU_CSR_COND2,
  90         FPU_CSR_COND3,
  91         FPU_CSR_COND4,
  92         FPU_CSR_COND5,
  93         FPU_CSR_COND6,
  94         FPU_CSR_COND7
  95 };
  96
  97 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  98 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  99 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
 100 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
 101 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
 102
 103 /*
 104  * This functions translates a 32-bit microMIPS instruction
 105  * into a 32-bit MIPS32 instruction. Returns 0 on success
 106  * and SIGILL otherwise.
 107  */
 108 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
 109 {
 110         union mips_instruction insn = *insn_ptr;
 111         union mips_instruction mips32_insn = insn;
 112         int func, fmt, op;
 113
 114         switch (insn.mm_i_format.opcode) {
 115         case mm_ldc132_op:
 116                 mips32_insn.mm_i_format.opcode = ldc1_op;
 117                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 118                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 119                 break;
 120         case mm_lwc132_op:
 121                 mips32_insn.mm_i_format.opcode = lwc1_op;
 122                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 123                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 124                 break;
 125         case mm_sdc132_op:
 126                 mips32_insn.mm_i_format.opcode = sdc1_op;
 127                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 128                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 129                 break;
 130         case mm_swc132_op:
 131                 mips32_insn.mm_i_format.opcode = swc1_op;
 132                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 133                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 134                 break;
 135         case mm_pool32i_op:
 136                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 137                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 138                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 139                         mips32_insn.fb_format.opcode = cop1_op;
 140                         mips32_insn.fb_format.bc = bc_op;
 141                         mips32_insn.fb_format.flag =
 142                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 143                 } else
 144                         return SIGILL;
 145                 break;
 146         case mm_pool32f_op:
 147                 switch (insn.mm_fp0_format.func) {
 148                 case mm_32f_01_op:
 149                 case mm_32f_11_op:
 150                 case mm_32f_02_op:
 151                 case mm_32f_12_op:
 152                 case mm_32f_41_op:
 153                 case mm_32f_51_op:
 154                 case mm_32f_42_op:
 155                 case mm_32f_52_op:
 156                         op = insn.mm_fp0_format.func;
 157                         if (op == mm_32f_01_op)
 158                                 func = madd_s_op;
 159                         else if (op == mm_32f_11_op)
 160                                 func = madd_d_op;
 161                         else if (op == mm_32f_02_op)
 162                                 func = nmadd_s_op;
 163                         else if (op == mm_32f_12_op)
 164                                 func = nmadd_d_op;
 165                         else if (op == mm_32f_41_op)
 166                                 func = msub_s_op;
 167                         else if (op == mm_32f_51_op)
 168                                 func = msub_d_op;
 169                         else if (op == mm_32f_42_op)
 170                                 func = nmsub_s_op;
 171                         else
 172                                 func = nmsub_d_op;
 173                         mips32_insn.fp6_format.opcode = cop1x_op;
 174                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 175                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 176                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 177                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 178                         mips32_insn.fp6_format.func = func;
 179                         break;
 180                 case mm_32f_10_op:
 181                         func = -1;      /* Invalid */
 182                         op = insn.mm_fp5_format.op & 0x7;
 183                         if (op == mm_ldxc1_op)
 184                                 func = ldxc1_op;
 185                         else if (op == mm_sdxc1_op)
 186                                 func = sdxc1_op;
 187                         else if (op == mm_lwxc1_op)
 188                                 func = lwxc1_op;
 189                         else if (op == mm_swxc1_op)
 190                                 func = swxc1_op;
 191
 192                         if (func != -1) {
 193                                 mips32_insn.r_format.opcode = cop1x_op;
 194                                 mips32_insn.r_format.rs =
 195                                         insn.mm_fp5_format.base;
 196                                 mips32_insn.r_format.rt =
 197                                         insn.mm_fp5_format.index;
 198                                 mips32_insn.r_format.rd = 0;
 199                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 200                                 mips32_insn.r_format.func = func;
 201                         } else
 202                                 return SIGILL;
 203                         break;
 204                 case mm_32f_40_op:
 205                         op = -1;        /* Invalid */
 206                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 207                                 op = 1;
 208                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 209                                 op = 0;
 210                         if (op != -1) {
 211                                 mips32_insn.fp0_format.opcode = cop1_op;
 212                                 mips32_insn.fp0_format.fmt =
 213                                         sdps_format[insn.mm_fp2_format.fmt];
 214                                 mips32_insn.fp0_format.ft =
 215                                         (insn.mm_fp2_format.cc<<2) + op;
 216                                 mips32_insn.fp0_format.fs =
 217                                         insn.mm_fp2_format.fs;
 218                                 mips32_insn.fp0_format.fd =
 219                                         insn.mm_fp2_format.fd;
 220                                 mips32_insn.fp0_format.func = fmovc_op;
 221                         } else
 222                                 return SIGILL;
 223                         break;
 224                 case mm_32f_60_op:
 225                         func = -1;      /* Invalid */
 226                         if (insn.mm_fp0_format.op == mm_fadd_op)
 227                                 func = fadd_op;
 228                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 229                                 func = fsub_op;
 230                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 231                                 func = fmul_op;
 232                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 233                                 func = fdiv_op;
 234                         if (func != -1) {
 235                                 mips32_insn.fp0_format.opcode = cop1_op;
 236                                 mips32_insn.fp0_format.fmt =
 237                                         sdps_format[insn.mm_fp0_format.fmt];
 238                                 mips32_insn.fp0_format.ft =
 239                                         insn.mm_fp0_format.ft;
 240                                 mips32_insn.fp0_format.fs =
 241                                         insn.mm_fp0_format.fs;
 242                                 mips32_insn.fp0_format.fd =
 243                                         insn.mm_fp0_format.fd;
 244                                 mips32_insn.fp0_format.func = func;
 245                         } else
 246                                 return SIGILL;
 247                         break;
 248                 case mm_32f_70_op:
 249                         func = -1;      /* Invalid */
 250                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 251                                 func = fmovn_op;
 252                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 253                                 func = fmovz_op;
 254                         if (func != -1) {
 255                                 mips32_insn.fp0_format.opcode = cop1_op;
 256                                 mips32_insn.fp0_format.fmt =
 257                                         sdps_format[insn.mm_fp0_format.fmt];
 258                                 mips32_insn.fp0_format.ft =
 259                                         insn.mm_fp0_format.ft;
 260                                 mips32_insn.fp0_format.fs =
 261                                         insn.mm_fp0_format.fs;
 262                                 mips32_insn.fp0_format.fd =
 263                                         insn.mm_fp0_format.fd;
 264                                 mips32_insn.fp0_format.func = func;
 265                         } else
 266                                 return SIGILL;
 267                         break;
 268                 case mm_32f_73_op:    /* POOL32FXF */
 269                         switch (insn.mm_fp1_format.op) {
 270                         case mm_movf0_op:
 271                         case mm_movf1_op:
 272                         case mm_movt0_op:
 273                         case mm_movt1_op:
 274                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 275                                     mm_movf0_op)
 276                                         op = 0;
 277                                 else
 278                                         op = 1;
 279                                 mips32_insn.r_format.opcode = spec_op;
 280                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 281                                 mips32_insn.r_format.rt =
 282                                         (insn.mm_fp4_format.cc << 2) + op;
 283                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 284                                 mips32_insn.r_format.re = 0;
 285                                 mips32_insn.r_format.func = movc_op;
 286                                 break;
 287                         case mm_fcvtd0_op:
 288                         case mm_fcvtd1_op:
 289                         case mm_fcvts0_op:
 290                         case mm_fcvts1_op:
 291                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 292                                     mm_fcvtd0_op) {
 293                                         func = fcvtd_op;
 294                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 295                                 } else {
 296                                         func = fcvts_op;
 297                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 298                                 }
 299                                 mips32_insn.fp0_format.opcode = cop1_op;
 300                                 mips32_insn.fp0_format.fmt = fmt;
 301                                 mips32_insn.fp0_format.ft = 0;
 302                                 mips32_insn.fp0_format.fs =
 303                                         insn.mm_fp3_format.fs;
 304                                 mips32_insn.fp0_format.fd =
 305                                         insn.mm_fp3_format.rt;
 306                                 mips32_insn.fp0_format.func = func;
 307                                 break;
 308                         case mm_fmov0_op:
 309                         case mm_fmov1_op:
 310                         case mm_fabs0_op:
 311                         case mm_fabs1_op:
 312                         case mm_fneg0_op:
 313                         case mm_fneg1_op:
 314                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 315                                     mm_fmov0_op)
 316                                         func = fmov_op;
 317                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 318                                          mm_fabs0_op)
 319                                         func = fabs_op;
 320                                 else
 321                                         func = fneg_op;
 322                                 mips32_insn.fp0_format.opcode = cop1_op;
 323                                 mips32_insn.fp0_format.fmt =
 324                                         sdps_format[insn.mm_fp3_format.fmt];
 325                                 mips32_insn.fp0_format.ft = 0;
 326                                 mips32_insn.fp0_format.fs =
 327                                         insn.mm_fp3_format.fs;
 328                                 mips32_insn.fp0_format.fd =
 329                                         insn.mm_fp3_format.rt;
 330                                 mips32_insn.fp0_format.func = func;
 331                                 break;
 332                         case mm_ffloorl_op:
 333                         case mm_ffloorw_op:
 334                         case mm_fceill_op:
 335                         case mm_fceilw_op:
 336                         case mm_ftruncl_op:
 337                         case mm_ftruncw_op:
 338                         case mm_froundl_op:
 339                         case mm_froundw_op:
 340                         case mm_fcvtl_op:
 341                         case mm_fcvtw_op:
 342                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 343                                         func = ffloorl_op;
 344                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 345                                         func = ffloor_op;
 346                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 347                                         func = fceill_op;
 348                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 349                                         func = fceil_op;
 350                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 351                                         func = ftruncl_op;
 352                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 353                                         func = ftrunc_op;
 354                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 355                                         func = froundl_op;
 356                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 357                                         func = fround_op;
 358                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 359                                         func = fcvtl_op;
 360                                 else
 361                                         func = fcvtw_op;
 362                                 mips32_insn.fp0_format.opcode = cop1_op;
 363                                 mips32_insn.fp0_format.fmt =
 364                                         sd_format[insn.mm_fp1_format.fmt];
 365                                 mips32_insn.fp0_format.ft = 0;
 366                                 mips32_insn.fp0_format.fs =
 367                                         insn.mm_fp1_format.fs;
 368                                 mips32_insn.fp0_format.fd =
 369                                         insn.mm_fp1_format.rt;
 370                                 mips32_insn.fp0_format.func = func;
 371                                 break;
 372                         case mm_frsqrt_op:
 373                         case mm_fsqrt_op:
 374                         case mm_frecip_op:
 375                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 376                                         func = frsqrt_op;
 377                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 378                                         func = fsqrt_op;
 379                                 else
 380                                         func = frecip_op;
 381                                 mips32_insn.fp0_format.opcode = cop1_op;
 382                                 mips32_insn.fp0_format.fmt =
 383                                         sdps_format[insn.mm_fp1_format.fmt];
 384                                 mips32_insn.fp0_format.ft = 0;
 385                                 mips32_insn.fp0_format.fs =
 386                                         insn.mm_fp1_format.fs;
 387                                 mips32_insn.fp0_format.fd =
 388                                         insn.mm_fp1_format.rt;
 389                                 mips32_insn.fp0_format.func = func;
 390                                 break;
 391                         case mm_mfc1_op:
 392                         case mm_mtc1_op:
 393                         case mm_cfc1_op:
 394                         case mm_ctc1_op:
 395                         case mm_mfhc1_op:
 396                         case mm_mthc1_op:
 397                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 398                                         op = mfc_op;
 399                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 400                                         op = mtc_op;
 401                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 402                                         op = cfc_op;
 403                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 404                                         op = ctc_op;
 405                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 406                                         op = mfhc_op;
 407                                 else
 408                                         op = mthc_op;
 409                                 mips32_insn.fp1_format.opcode = cop1_op;
 410                                 mips32_insn.fp1_format.op = op;
 411                                 mips32_insn.fp1_format.rt =
 412                                         insn.mm_fp1_format.rt;
 413                                 mips32_insn.fp1_format.fs =
 414                                         insn.mm_fp1_format.fs;
 415                                 mips32_insn.fp1_format.fd = 0;
 416                                 mips32_insn.fp1_format.func = 0;
 417                                 break;
 418                         default:
 419                                 return SIGILL;
 420                         }
 421                         break;
 422                 case mm_32f_74_op:      /* c.cond.fmt */
 423                         mips32_insn.fp0_format.opcode = cop1_op;
 424                         mips32_insn.fp0_format.fmt =
 425                                 sdps_format[insn.mm_fp4_format.fmt];
 426                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 427                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 428                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 429                         mips32_insn.fp0_format.func =
 430                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 431                         break;
 432                 default:
 433                         return SIGILL;
 434                 }
 435                 break;
 436         default:
 437                 return SIGILL;
 438         }
 439
 440         *insn_ptr = mips32_insn;
 441         return 0;
 442 }
 443
 444 /*
 445  * Redundant with logic already in kernel/branch.c,
 446  * embedded in compute_return_epc.  At some point,
 447  * a single subroutine should be used across both
 448  * modules.
 449  */
 450 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 451                          unsigned long *contpc)
 452 {
 453         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 454         unsigned int fcr31;
 455         unsigned int bit = 0;
 456
 457         switch (insn.i_format.opcode) {
 458         case spec_op:
 459                 switch (insn.r_format.func) {
 460                 case jalr_op:
 461                         regs->regs[insn.r_format.rd] =
 462                                 regs->cp0_epc + dec_insn.pc_inc +
 463                                 dec_insn.next_pc_inc;
 464                         /* Fall through */
 465                 case jr_op:
 466                         *contpc = regs->regs[insn.r_format.rs];
 467                         return 1;
 468                 }
 469                 break;
 470         case bcond_op:
 471                 switch (insn.i_format.rt) {
 472                 case bltzal_op:
 473                 case bltzall_op:
 474                         regs->regs[31] = regs->cp0_epc +
 475                                 dec_insn.pc_inc +
 476                                 dec_insn.next_pc_inc;
 477                         /* Fall through */
 478                 case bltz_op:
 479                 case bltzl_op:
 480                         if ((long)regs->regs[insn.i_format.rs] < 0)
 481                                 *contpc = regs->cp0_epc +
 482                                         dec_insn.pc_inc +
 483                                         (insn.i_format.simmediate << 2);
 484                         else
 485                                 *contpc = regs->cp0_epc +
 486                                         dec_insn.pc_inc +
 487                                         dec_insn.next_pc_inc;
 488                         return 1;
 489                 case bgezal_op:
 490                 case bgezall_op:
 491                         regs->regs[31] = regs->cp0_epc +
 492                                 dec_insn.pc_inc +
 493                                 dec_insn.next_pc_inc;
 494                         /* Fall through */
 495                 case bgez_op:
 496                 case bgezl_op:
 497                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 498                                 *contpc = regs->cp0_epc +
 499                                         dec_insn.pc_inc +
 500                                         (insn.i_format.simmediate << 2);
 501                         else
 502                                 *contpc = regs->cp0_epc +
 503                                         dec_insn.pc_inc +
 504                                         dec_insn.next_pc_inc;
 505                         return 1;
 506                 }
 507                 break;
 508         case jalx_op:
 509                 set_isa16_mode(bit);
 510         case jal_op:
 511                 regs->regs[31] = regs->cp0_epc +
 512                         dec_insn.pc_inc +
 513                         dec_insn.next_pc_inc;
 514                 /* Fall through */
 515         case j_op:
 516                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 517                 *contpc >>= 28;
 518                 *contpc <<= 28;
 519                 *contpc |= (insn.j_format.target << 2);
 520                 /* Set microMIPS mode bit: XOR for jalx. */
 521                 *contpc ^= bit;
 522                 return 1;
 523         case beq_op:
 524         case beql_op:
 525                 if (regs->regs[insn.i_format.rs] ==
 526                     regs->regs[insn.i_format.rt])
 527                         *contpc = regs->cp0_epc +
 528                                 dec_insn.pc_inc +
 529                                 (insn.i_format.simmediate << 2);
 530                 else
 531                         *contpc = regs->cp0_epc +
 532                                 dec_insn.pc_inc +
 533                                 dec_insn.next_pc_inc;
 534                 return 1;
 535         case bne_op:
 536         case bnel_op:
 537                 if (regs->regs[insn.i_format.rs] !=
 538                     regs->regs[insn.i_format.rt])
 539                         *contpc = regs->cp0_epc +
 540                                 dec_insn.pc_inc +
 541                                 (insn.i_format.simmediate << 2);
 542                 else
 543                         *contpc = regs->cp0_epc +
 544                                 dec_insn.pc_inc +
 545                                 dec_insn.next_pc_inc;
 546                 return 1;
 547         case blez_op:
 548         case blezl_op:
 549                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 550                         *contpc = regs->cp0_epc +
 551                                 dec_insn.pc_inc +
 552                                 (insn.i_format.simmediate << 2);
 553                 else
 554                         *contpc = regs->cp0_epc +
 555                                 dec_insn.pc_inc +
 556                                 dec_insn.next_pc_inc;
 557                 return 1;
 558         case bgtz_op:
 559         case bgtzl_op:
 560                 if ((long)regs->regs[insn.i_format.rs] > 0)
 561                         *contpc = regs->cp0_epc +
 562                                 dec_insn.pc_inc +
 563                                 (insn.i_format.simmediate << 2);
 564                 else
 565                         *contpc = regs->cp0_epc +
 566                                 dec_insn.pc_inc +
 567                                 dec_insn.next_pc_inc;
 568                 return 1;
 569 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 570         case lwc2_op: /* This is bbit0 on Octeon */
 571                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 572                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 573                 else
 574                         *contpc = regs->cp0_epc + 8;
 575                 return 1;
 576         case ldc2_op: /* This is bbit032 on Octeon */
 577                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 578                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 579                 else
 580                         *contpc = regs->cp0_epc + 8;
 581                 return 1;
 582         case swc2_op: /* This is bbit1 on Octeon */
 583                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 584                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 585                 else
 586                         *contpc = regs->cp0_epc + 8;
 587                 return 1;
 588         case sdc2_op: /* This is bbit132 on Octeon */
 589                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 590                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 591                 else
 592                         *contpc = regs->cp0_epc + 8;
 593                 return 1;
 594 #endif
 595         case cop0_op:
 596         case cop1_op:
 597         case cop2_op:
 598         case cop1x_op:
 599                 if (insn.i_format.rs == bc_op) {
 600                         preempt_disable();
 601                         if (is_fpu_owner())
 602                                 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
 603                         else
 604                                 fcr31 = current->thread.fpu.fcr31;
 605                         preempt_enable();
 606
 607                         bit = (insn.i_format.rt >> 2);
 608                         bit += (bit != 0);
 609                         bit += 23;
 610                         switch (insn.i_format.rt & 3) {
 611                         case 0: /* bc1f */
 612                         case 2: /* bc1fl */
 613                                 if (~fcr31 & (1 << bit))
 614                                         *contpc = regs->cp0_epc +
 615                                                 dec_insn.pc_inc +
 616                                                 (insn.i_format.simmediate << 2);
 617                                 else
 618                                         *contpc = regs->cp0_epc +
 619                                                 dec_insn.pc_inc +
 620                                                 dec_insn.next_pc_inc;
 621                                 return 1;
 622                         case 1: /* bc1t */
 623                         case 3: /* bc1tl */
 624                                 if (fcr31 & (1 << bit))
 625                                         *contpc = regs->cp0_epc +
 626                                                 dec_insn.pc_inc +
 627                                                 (insn.i_format.simmediate << 2);
 628                                 else
 629                                         *contpc = regs->cp0_epc +
 630                                                 dec_insn.pc_inc +
 631                                                 dec_insn.next_pc_inc;
 632                                 return 1;
 633                         }
 634                 }
 635                 break;
 636         }
 637         return 0;
 638 }
 639
 640 /*
 641  * In the Linux kernel, we support selection of FPR format on the
 642  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 643  * is hardwired to zero, which would imply a 32-bit FPU even for
 644  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 645  * FPU emu is slow and bulky and optimizing this function offers fairly
 646  * sizeable benefits so we try to be clever and make this function return
 647  * a constant whenever possible, that is on 64-bit kernels without O32
 648  * compatibility enabled and on 32-bit without 64-bit FPU support.
 649  */
 650 static inline int cop1_64bit(struct pt_regs *xcp)
 651 {
 652         if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
 653                 return 1;
 654         else if (config_enabled(CONFIG_32BIT) &&
 655                  !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
 656                 return 0;
 657
 658         return !test_thread_flag(TIF_32BIT_FPREGS);
 659 }
 660
 661 #define SIFROMREG(si, x)                                                \
 662 do {                                                                    \
 663         if (cop1_64bit(xcp))                                            \
 664                 (si) = get_fpr32(&ctx->fpr[x], 0);                      \
 665         else                                                            \
 666                 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);         \
 667 } while (0)
 668
 669 #define SITOREG(si, x)                                                  \
 670 do {                                                                    \
 671         if (cop1_64bit(xcp)) {                                          \
 672                 unsigned i;                                             \
 673                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 674                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 675                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 676         } else {                                                        \
 677                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 678         }                                                               \
 679 } while (0)
 680
 681 #define SIFROMHREG(si, x)       ((si) = get_fpr32(&ctx->fpr[x], 1))
 682
 683 #define SITOHREG(si, x)                                                 \
 684 do {                                                                    \
 685         unsigned i;                                                     \
 686         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 687         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 688                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 689 } while (0)
 690
 691 #define DIFROMREG(di, x)                                                \
 692         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 693
 694 #define DITOREG(di, x)                                                  \
 695 do {                                                                    \
 696         unsigned fpr, i;                                                \
 697         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 698         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 699         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 700                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 701 } while (0)
 702
 703 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 704 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 705 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 706 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 707
 708 /*
 709  * Emulate the single floating point instruction pointed at by EPC.
 710  * Two instructions if the instruction is in a branch delay slot.
 711  */
 712
 713 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 714                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 715 {
 716         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 717         unsigned int cond, cbit;
 718         mips_instruction ir;
 719         int likely, pc_inc;
 720         u32 __user *wva;
 721         u64 __user *dva;
 722         u32 value;
 723         u32 wval;
 724         u64 dval;
 725         int sig;
 726
 727         /* XXX NEC Vr54xx bug workaround */
 728         if (delay_slot(xcp)) {
 729                 if (dec_insn.micro_mips_mode) {
 730                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 731                                 clear_delay_slot(xcp);
 732                 } else {
 733                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 734                                 clear_delay_slot(xcp);
 735                 }
 736         }
 737
 738         if (delay_slot(xcp)) {
 739                 /*
 740                  * The instruction to be emulated is in a branch delay slot
 741                  * which means that we have to  emulate the branch instruction
 742                  * BEFORE we do the cop1 instruction.
 743                  *
 744                  * This branch could be a COP1 branch, but in that case we
 745                  * would have had a trap for that instruction, and would not
 746                  * come through this route.
 747                  *
 748                  * Linux MIPS branch emulator operates on context, updating the
 749                  * cp0_epc.
 750                  */
 751                 ir = dec_insn.next_insn;  /* process delay slot instr */
 752                 pc_inc = dec_insn.next_pc_inc;
 753         } else {
 754                 ir = dec_insn.insn;       /* process current instr */
 755                 pc_inc = dec_insn.pc_inc;
 756         }
 757
 758         /*
 759          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 760          * instructions, we want to convert microMIPS FPU instructions
 761          * into MIPS32 instructions so that we could reuse all of the
 762          * FPU emulation code.
 763          *
 764          * NOTE: We cannot do this for branch instructions since they
 765          *       are not a subset. Example: Cannot emulate a 16-bit
 766          *       aligned target address with a MIPS32 instruction.
 767          */
 768         if (dec_insn.micro_mips_mode) {
 769                 /*
 770                  * If next instruction is a 16-bit instruction, then it
 771                  * it cannot be a FPU instruction. This could happen
 772                  * since we can be called for non-FPU instructions.
 773                  */
 774                 if ((pc_inc == 2) ||
 775                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 776                          == SIGILL))
 777                         return SIGILL;
 778         }
 779
 780 emul:
 781         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 782         MIPS_FPU_EMU_INC_STATS(emulated);
 783         switch (MIPSInst_OPCODE(ir)) {
 784         case ldc1_op:
 785                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 786                                      MIPSInst_SIMM(ir));
 787                 MIPS_FPU_EMU_INC_STATS(loads);
 788
 789                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
 790                         MIPS_FPU_EMU_INC_STATS(errors);
 791                         *fault_addr = dva;
 792                         return SIGBUS;
 793                 }
 794                 if (__get_user(dval, dva)) {
 795                         MIPS_FPU_EMU_INC_STATS(errors);
 796                         *fault_addr = dva;
 797                         return SIGSEGV;
 798                 }
 799                 DITOREG(dval, MIPSInst_RT(ir));
 800                 break;
 801
 802         case sdc1_op:
 803                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 804                                       MIPSInst_SIMM(ir));
 805                 MIPS_FPU_EMU_INC_STATS(stores);
 806                 DIFROMREG(dval, MIPSInst_RT(ir));
 807                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
 808                         MIPS_FPU_EMU_INC_STATS(errors);
 809                         *fault_addr = dva;
 810                         return SIGBUS;
 811                 }
 812                 if (__put_user(dval, dva)) {
 813                         MIPS_FPU_EMU_INC_STATS(errors);
 814                         *fault_addr = dva;
 815                         return SIGSEGV;
 816                 }
 817                 break;
 818
 819         case lwc1_op:
 820                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 821                                       MIPSInst_SIMM(ir));
 822                 MIPS_FPU_EMU_INC_STATS(loads);
 823                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
 824                         MIPS_FPU_EMU_INC_STATS(errors);
 825                         *fault_addr = wva;
 826                         return SIGBUS;
 827                 }
 828                 if (__get_user(wval, wva)) {
 829                         MIPS_FPU_EMU_INC_STATS(errors);
 830                         *fault_addr = wva;
 831                         return SIGSEGV;
 832                 }
 833                 SITOREG(wval, MIPSInst_RT(ir));
 834                 break;
 835
 836         case swc1_op:
 837                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 838                                       MIPSInst_SIMM(ir));
 839                 MIPS_FPU_EMU_INC_STATS(stores);
 840                 SIFROMREG(wval, MIPSInst_RT(ir));
 841                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
 842                         MIPS_FPU_EMU_INC_STATS(errors);
 843                         *fault_addr = wva;
 844                         return SIGBUS;
 845                 }
 846                 if (__put_user(wval, wva)) {
 847                         MIPS_FPU_EMU_INC_STATS(errors);
 848                         *fault_addr = wva;
 849                         return SIGSEGV;
 850                 }
 851                 break;
 852
 853         case cop1_op:
 854                 switch (MIPSInst_RS(ir)) {
 855                 case dmfc_op:
 856                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 857                                 return SIGILL;
 858
 859                         /* copregister fs -> gpr[rt] */
 860                         if (MIPSInst_RT(ir) != 0) {
 861                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 862                                         MIPSInst_RD(ir));
 863                         }
 864                         break;
 865
 866                 case dmtc_op:
 867                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 868                                 return SIGILL;
 869
 870                         /* copregister fs <- rt */
 871                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 872                         break;
 873
 874                 case mfhc_op:
 875                         if (!cpu_has_mips_r2)
 876                                 goto sigill;
 877
 878                         /* copregister rd -> gpr[rt] */
 879                         if (MIPSInst_RT(ir) != 0) {
 880                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
 881                                         MIPSInst_RD(ir));
 882                         }
 883                         break;
 884
 885                 case mthc_op:
 886                         if (!cpu_has_mips_r2)
 887                                 goto sigill;
 888
 889                         /* copregister rd <- gpr[rt] */
 890                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 891                         break;
 892
 893                 case mfc_op:
 894                         /* copregister rd -> gpr[rt] */
 895                         if (MIPSInst_RT(ir) != 0) {
 896                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 897                                         MIPSInst_RD(ir));
 898                         }
 899                         break;
 900
 901                 case mtc_op:
 902                         /* copregister rd <- rt */
 903                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 904                         break;
 905
 906                 case cfc_op:
 907                         /* cop control register rd -> gpr[rt] */
 908                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 909                                 value = ctx->fcr31;
 910                                 value = (value & ~FPU_CSR_RM) |
 911                                         mips_rm[modeindex(value)];
 912                                 pr_debug("%p gpr[%d]<-csr=%08x\n",
 913                                          (void *) (xcp->cp0_epc),
 914                                          MIPSInst_RT(ir), value);
 915                         }
 916                         else if (MIPSInst_RD(ir) == FPCREG_RID)
 917                                 value = 0;
 918                         else
 919                                 value = 0;
 920                         if (MIPSInst_RT(ir))
 921                                 xcp->regs[MIPSInst_RT(ir)] = value;
 922                         break;
 923
 924                 case ctc_op:
 925                         /* copregister rd <- rt */
 926                         if (MIPSInst_RT(ir) == 0)
 927                                 value = 0;
 928                         else
 929                                 value = xcp->regs[MIPSInst_RT(ir)];
 930
 931                         /* we only have one writable control reg
 932                          */
 933                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 934                                 pr_debug("%p gpr[%d]->csr=%08x\n",
 935                                          (void *) (xcp->cp0_epc),
 936                                          MIPSInst_RT(ir), value);
 937
 938                                 /*
 939                                  * Don't write reserved bits,
 940                                  * and convert to ieee library modes
 941                                  */
 942                                 ctx->fcr31 = (value &
 943                                                 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
 944                                                 ieee_rm[modeindex(value)];
 945                         }
 946                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
 947                                 return SIGFPE;
 948                         }
 949                         break;
 950
 951                 case bc_op:
 952                         if (delay_slot(xcp))
 953                                 return SIGILL;
 954
 955                         if (cpu_has_mips_4_5_r)
 956                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
 957                         else
 958                                 cbit = FPU_CSR_COND;
 959                         cond = ctx->fcr31 & cbit;
 960
 961                         likely = 0;
 962                         switch (MIPSInst_RT(ir) & 3) {
 963                         case bcfl_op:
 964                                 likely = 1;
 965                         case bcf_op:
 966                                 cond = !cond;
 967                                 break;
 968                         case bctl_op:
 969                                 likely = 1;
 970                         case bct_op:
 971                                 break;
 972                         default:
 973                                 /* thats an illegal instruction */
 974                                 return SIGILL;
 975                         }
 976
 977                         set_delay_slot(xcp);
 978                         if (cond) {
 979                                 /*
 980                                  * Branch taken: emulate dslot instruction
 981                                  */
 982                                 xcp->cp0_epc += dec_insn.pc_inc;
 983
 984                                 contpc = MIPSInst_SIMM(ir);
 985                                 ir = dec_insn.next_insn;
 986                                 if (dec_insn.micro_mips_mode) {
 987                                         contpc = (xcp->cp0_epc + (contpc << 1));
 988
 989                                         /* If 16-bit instruction, not FPU. */
 990                                         if ((dec_insn.next_pc_inc == 2) ||
 991                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
 992
 993                                                 /*
 994                                                  * Since this instruction will
 995                                                  * be put on the stack with
 996                                                  * 32-bit words, get around
 997                                                  * this problem by putting a
 998                                                  * NOP16 as the second one.
 999                                                  */
1000                                                 if (dec_insn.next_pc_inc == 2)
1001                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1002
1003                                                 /*
1004                                                  * Single step the non-CP1
1005                                                  * instruction in the dslot.
1006                                                  */
1007                                                 return mips_dsemul(xcp, ir, contpc);
1008                                         }
1009                                 } else
1010                                         contpc = (xcp->cp0_epc + (contpc << 2));
1011
1012                                 switch (MIPSInst_OPCODE(ir)) {
1013                                 case lwc1_op:
1014                                         goto emul;
1015
1016                                 case swc1_op:
1017                                         goto emul;
1018
1019                                 case ldc1_op:
1020                                 case sdc1_op:
1021                                         if (cpu_has_mips_2_3_4_5 ||
1022                                             cpu_has_mips64)
1023                                                 goto emul;
1024
1025                                         return SIGILL;
1026                                         goto emul;
1027
1028                                 case cop1_op:
1029                                         goto emul;
1030
1031                                 case cop1x_op:
1032                                         if (cpu_has_mips_4_5 || cpu_has_mips64)
1033                                                 /* its one of ours */
1034                                                 goto emul;
1035
1036                                         return SIGILL;
1037
1038                                 case spec_op:
1039                                         if (!cpu_has_mips_4_5_r)
1040                                                 return SIGILL;
1041
1042                                         if (MIPSInst_FUNC(ir) == movc_op)
1043                                                 goto emul;
1044                                         break;
1045                                 }
1046
1047                                 /*
1048                                  * Single step the non-cp1
1049                                  * instruction in the dslot
1050                                  */
1051                                 return mips_dsemul(xcp, ir, contpc);
1052                         } else if (likely) {    /* branch not taken */
1053                                         /*
1054                                          * branch likely nullifies
1055                                          * dslot if not taken
1056                                          */
1057                                         xcp->cp0_epc += dec_insn.pc_inc;
1058                                         contpc += dec_insn.pc_inc;
1059                                         /*
1060                                          * else continue & execute
1061                                          * dslot as normal insn
1062                                          */
1063                                 }
1064                         break;
1065
1066                 default:
1067                         if (!(MIPSInst_RS(ir) & 0x10))
1068                                 return SIGILL;
1069
1070                         /* a real fpu computation instruction */
1071                         if ((sig = fpu_emu(xcp, ctx, ir)))
1072                                 return sig;
1073                 }
1074                 break;
1075
1076         case cop1x_op:
1077                 if (!cpu_has_mips_4_5 && !cpu_has_mips64)
1078                         return SIGILL;
1079
1080                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1081                 if (sig)
1082                         return sig;
1083                 break;
1084
1085         case spec_op:
1086                 if (!cpu_has_mips_4_5_r)
1087                         return SIGILL;
1088
1089                 if (MIPSInst_FUNC(ir) != movc_op)
1090                         return SIGILL;
1091                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1092                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1093                         xcp->regs[MIPSInst_RD(ir)] =
1094                                 xcp->regs[MIPSInst_RS(ir)];
1095                 break;
1096         default:
1097 sigill:
1098                 return SIGILL;
1099         }
1100
1101         /* we did it !! */
1102         xcp->cp0_epc = contpc;
1103         clear_delay_slot(xcp);
1104
1105         return 0;
1106 }
1107
1108 /*
1109  * Conversion table from MIPS compare ops 48-63
1110  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1111  */
1112 static const unsigned char cmptab[8] = {
1113         0,                      /* cmp_0 (sig) cmp_sf */
1114         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1115         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1116         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1117         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1118         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1119         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1120         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1121 };
1122
1123
1124 /*
1125  * Additional MIPS4 instructions
1126  */
1127
1128 #define DEF3OP(name, p, f1, f2, f3)                                     \
1129 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1130         union ieee754##p s, union ieee754##p t)                         \
1131 {                                                                       \
1132         struct _ieee754_csr ieee754_csr_save;                           \
1133         s = f1(s, t);                                                   \
1134         ieee754_csr_save = ieee754_csr;                                 \
1135         s = f2(s, r);                                                   \
1136         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1137         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1138         s = f3(s);                                                      \
1139         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1140         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1141         return s;                                                       \
1142 }
1143
1144 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1145 {
1146         return ieee754dp_div(ieee754dp_one(0), d);
1147 }
1148
1149 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1150 {
1151         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1152 }
1153
1154 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1155 {
1156         return ieee754sp_div(ieee754sp_one(0), s);
1157 }
1158
1159 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1160 {
1161         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1162 }
1163
1164 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1165 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1166 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1167 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1168 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1169 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1170 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1171 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1172
1173 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1174         mips_instruction ir, void *__user *fault_addr)
1175 {
1176         unsigned rcsr = 0;      /* resulting csr */
1177
1178         MIPS_FPU_EMU_INC_STATS(cp1xops);
1179
1180         switch (MIPSInst_FMA_FFMT(ir)) {
1181         case s_fmt:{            /* 0 */
1182
1183                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1184                 union ieee754sp fd, fr, fs, ft;
1185                 u32 __user *va;
1186                 u32 val;
1187
1188                 switch (MIPSInst_FUNC(ir)) {
1189                 case lwxc1_op:
1190                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1191                                 xcp->regs[MIPSInst_FT(ir)]);
1192
1193                         MIPS_FPU_EMU_INC_STATS(loads);
1194                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1195                                 MIPS_FPU_EMU_INC_STATS(errors);
1196                                 *fault_addr = va;
1197                                 return SIGBUS;
1198                         }
1199                         if (__get_user(val, va)) {
1200                                 MIPS_FPU_EMU_INC_STATS(errors);
1201                                 *fault_addr = va;
1202                                 return SIGSEGV;
1203                         }
1204                         SITOREG(val, MIPSInst_FD(ir));
1205                         break;
1206
1207                 case swxc1_op:
1208                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1209                                 xcp->regs[MIPSInst_FT(ir)]);
1210
1211                         MIPS_FPU_EMU_INC_STATS(stores);
1212
1213                         SIFROMREG(val, MIPSInst_FS(ir));
1214                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1215                                 MIPS_FPU_EMU_INC_STATS(errors);
1216                                 *fault_addr = va;
1217                                 return SIGBUS;
1218                         }
1219                         if (put_user(val, va)) {
1220                                 MIPS_FPU_EMU_INC_STATS(errors);
1221                                 *fault_addr = va;
1222                                 return SIGSEGV;
1223                         }
1224                         break;
1225
1226                 case madd_s_op:
1227                         handler = fpemu_sp_madd;
1228                         goto scoptop;
1229                 case msub_s_op:
1230                         handler = fpemu_sp_msub;
1231                         goto scoptop;
1232                 case nmadd_s_op:
1233                         handler = fpemu_sp_nmadd;
1234                         goto scoptop;
1235                 case nmsub_s_op:
1236                         handler = fpemu_sp_nmsub;
1237                         goto scoptop;
1238
1239                       scoptop:
1240                         SPFROMREG(fr, MIPSInst_FR(ir));
1241                         SPFROMREG(fs, MIPSInst_FS(ir));
1242                         SPFROMREG(ft, MIPSInst_FT(ir));
1243                         fd = (*handler) (fr, fs, ft);
1244                         SPTOREG(fd, MIPSInst_FD(ir));
1245
1246                       copcsr:
1247                         if (ieee754_cxtest(IEEE754_INEXACT))
1248                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1249                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
1250                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1251                         if (ieee754_cxtest(IEEE754_OVERFLOW))
1252                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1253                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1254                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1255
1256                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1257                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1258                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1259                                    ctx->fcr31); */
1260                                 return SIGFPE;
1261                         }
1262
1263                         break;
1264
1265                 default:
1266                         return SIGILL;
1267                 }
1268                 break;
1269         }
1270
1271         case d_fmt:{            /* 1 */
1272                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1273                 union ieee754dp fd, fr, fs, ft;
1274                 u64 __user *va;
1275                 u64 val;
1276
1277                 switch (MIPSInst_FUNC(ir)) {
1278                 case ldxc1_op:
1279                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1280                                 xcp->regs[MIPSInst_FT(ir)]);
1281
1282                         MIPS_FPU_EMU_INC_STATS(loads);
1283                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1284                                 MIPS_FPU_EMU_INC_STATS(errors);
1285                                 *fault_addr = va;
1286                                 return SIGBUS;
1287                         }
1288                         if (__get_user(val, va)) {
1289                                 MIPS_FPU_EMU_INC_STATS(errors);
1290                                 *fault_addr = va;
1291                                 return SIGSEGV;
1292                         }
1293                         DITOREG(val, MIPSInst_FD(ir));
1294                         break;
1295
1296                 case sdxc1_op:
1297                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1298                                 xcp->regs[MIPSInst_FT(ir)]);
1299
1300                         MIPS_FPU_EMU_INC_STATS(stores);
1301                         DIFROMREG(val, MIPSInst_FS(ir));
1302                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1303                                 MIPS_FPU_EMU_INC_STATS(errors);
1304                                 *fault_addr = va;
1305                                 return SIGBUS;
1306                         }
1307                         if (__put_user(val, va)) {
1308                                 MIPS_FPU_EMU_INC_STATS(errors);
1309                                 *fault_addr = va;
1310                                 return SIGSEGV;
1311                         }
1312                         break;
1313
1314                 case madd_d_op:
1315                         handler = fpemu_dp_madd;
1316                         goto dcoptop;
1317                 case msub_d_op:
1318                         handler = fpemu_dp_msub;
1319                         goto dcoptop;
1320                 case nmadd_d_op:
1321                         handler = fpemu_dp_nmadd;
1322                         goto dcoptop;
1323                 case nmsub_d_op:
1324                         handler = fpemu_dp_nmsub;
1325                         goto dcoptop;
1326
1327                       dcoptop:
1328                         DPFROMREG(fr, MIPSInst_FR(ir));
1329                         DPFROMREG(fs, MIPSInst_FS(ir));
1330                         DPFROMREG(ft, MIPSInst_FT(ir));
1331                         fd = (*handler) (fr, fs, ft);
1332                         DPTOREG(fd, MIPSInst_FD(ir));
1333                         goto copcsr;
1334
1335                 default:
1336                         return SIGILL;
1337                 }
1338                 break;
1339         }
1340
1341         case 0x3:
1342                 if (MIPSInst_FUNC(ir) != pfetch_op)
1343                         return SIGILL;
1344
1345                 /* ignore prefx operation */
1346                 break;
1347
1348         default:
1349                 return SIGILL;
1350         }
1351
1352         return 0;
1353 }
1354
1355
1356
1357 /*
1358  * Emulate a single COP1 arithmetic instruction.
1359  */
1360 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1361         mips_instruction ir)
1362 {
1363         int rfmt;               /* resulting format */
1364         unsigned rcsr = 0;      /* resulting csr */
1365         unsigned int oldrm;
1366         unsigned int cbit;
1367         unsigned cond;
1368         union {
1369                 union ieee754dp d;
1370                 union ieee754sp s;
1371                 int w;
1372                 s64 l;
1373         } rv;                   /* resulting value */
1374         u64 bits;
1375
1376         MIPS_FPU_EMU_INC_STATS(cp1ops);
1377         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1378         case s_fmt: {           /* 0 */
1379                 union {
1380                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1381                         union ieee754sp(*u) (union ieee754sp);
1382                 } handler;
1383                 union ieee754sp fs, ft;
1384
1385                 switch (MIPSInst_FUNC(ir)) {
1386                         /* binary ops */
1387                 case fadd_op:
1388                         handler.b = ieee754sp_add;
1389                         goto scopbop;
1390                 case fsub_op:
1391                         handler.b = ieee754sp_sub;
1392                         goto scopbop;
1393                 case fmul_op:
1394                         handler.b = ieee754sp_mul;
1395                         goto scopbop;
1396                 case fdiv_op:
1397                         handler.b = ieee754sp_div;
1398                         goto scopbop;
1399
1400                         /* unary  ops */
1401                 case fsqrt_op:
1402                         if (!cpu_has_mips_4_5_r)
1403                                 return SIGILL;
1404
1405                         handler.u = ieee754sp_sqrt;
1406                         goto scopuop;
1407
1408                 /*
1409                  * Note that on some MIPS IV implementations such as the
1410                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1411                  * achieve full IEEE-754 accuracy - however this emulator does.
1412                  */
1413                 case frsqrt_op:
1414                         if (!cpu_has_mips_4_5_r2)
1415                                 return SIGILL;
1416
1417                         handler.u = fpemu_sp_rsqrt;
1418                         goto scopuop;
1419
1420                 case frecip_op:
1421                         if (!cpu_has_mips_4_5_r2)
1422                                 return SIGILL;
1423
1424                         handler.u = fpemu_sp_recip;
1425                         goto scopuop;
1426
1427                 case fmovc_op:
1428                         if (!cpu_has_mips_4_5_r)
1429                                 return SIGILL;
1430
1431                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1432                         if (((ctx->fcr31 & cond) != 0) !=
1433                                 ((MIPSInst_FT(ir) & 1) != 0))
1434                                 return 0;
1435                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1436                         break;
1437
1438                 case fmovz_op:
1439                         if (!cpu_has_mips_4_5_r)
1440                                 return SIGILL;
1441
1442                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1443                                 return 0;
1444                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1445                         break;
1446
1447                 case fmovn_op:
1448                         if (!cpu_has_mips_4_5_r)
1449                                 return SIGILL;
1450
1451                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1452                                 return 0;
1453                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1454                         break;
1455
1456                 case fabs_op:
1457                         handler.u = ieee754sp_abs;
1458                         goto scopuop;
1459
1460                 case fneg_op:
1461                         handler.u = ieee754sp_neg;
1462                         goto scopuop;
1463
1464                 case fmov_op:
1465                         /* an easy one */
1466                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1467                         goto copcsr;
1468
1469                         /* binary op on handler */
1470 scopbop:
1471                         SPFROMREG(fs, MIPSInst_FS(ir));
1472                         SPFROMREG(ft, MIPSInst_FT(ir));
1473
1474                         rv.s = (*handler.b) (fs, ft);
1475                         goto copcsr;
1476 scopuop:
1477                         SPFROMREG(fs, MIPSInst_FS(ir));
1478                         rv.s = (*handler.u) (fs);
1479                         goto copcsr;
1480 copcsr:
1481                         if (ieee754_cxtest(IEEE754_INEXACT))
1482                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1483                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
1484                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1485                         if (ieee754_cxtest(IEEE754_OVERFLOW))
1486                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1487                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1488                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1489                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1490                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1491                         break;
1492
1493                         /* unary conv ops */
1494                 case fcvts_op:
1495                         return SIGILL;  /* not defined */
1496
1497                 case fcvtd_op:
1498                         SPFROMREG(fs, MIPSInst_FS(ir));
1499                         rv.d = ieee754dp_fsp(fs);
1500                         rfmt = d_fmt;
1501                         goto copcsr;
1502
1503                 case fcvtw_op:
1504                         SPFROMREG(fs, MIPSInst_FS(ir));
1505                         rv.w = ieee754sp_tint(fs);
1506                         rfmt = w_fmt;
1507                         goto copcsr;
1508
1509                 case fround_op:
1510                 case ftrunc_op:
1511                 case fceil_op:
1512                 case ffloor_op:
1513                         if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1514                                 return SIGILL;
1515
1516                         oldrm = ieee754_csr.rm;
1517                         SPFROMREG(fs, MIPSInst_FS(ir));
1518                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1519                         rv.w = ieee754sp_tint(fs);
1520                         ieee754_csr.rm = oldrm;
1521                         rfmt = w_fmt;
1522                         goto copcsr;
1523
1524                 case fcvtl_op:
1525                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1526                                 return SIGILL;
1527
1528                         SPFROMREG(fs, MIPSInst_FS(ir));
1529                         rv.l = ieee754sp_tlong(fs);
1530                         rfmt = l_fmt;
1531                         goto copcsr;
1532
1533                 case froundl_op:
1534                 case ftruncl_op:
1535                 case fceill_op:
1536                 case ffloorl_op:
1537                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1538                                 return SIGILL;
1539
1540                         oldrm = ieee754_csr.rm;
1541                         SPFROMREG(fs, MIPSInst_FS(ir));
1542                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1543                         rv.l = ieee754sp_tlong(fs);
1544                         ieee754_csr.rm = oldrm;
1545                         rfmt = l_fmt;
1546                         goto copcsr;
1547
1548                 default:
1549                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1550                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1551                                 union ieee754sp fs, ft;
1552
1553                                 SPFROMREG(fs, MIPSInst_FS(ir));
1554                                 SPFROMREG(ft, MIPSInst_FT(ir));
1555                                 rv.w = ieee754sp_cmp(fs, ft,
1556                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1557                                 rfmt = -1;
1558                                 if ((cmpop & 0x8) && ieee754_cxtest
1559                                         (IEEE754_INVALID_OPERATION))
1560                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1561                                 else
1562                                         goto copcsr;
1563
1564                         } else
1565                                 return SIGILL;
1566                         break;
1567                 }
1568                 break;
1569         }
1570
1571         case d_fmt: {
1572                 union ieee754dp fs, ft;
1573                 union {
1574                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1575                         union ieee754dp(*u) (union ieee754dp);
1576                 } handler;
1577
1578                 switch (MIPSInst_FUNC(ir)) {
1579                         /* binary ops */
1580                 case fadd_op:
1581                         handler.b = ieee754dp_add;
1582                         goto dcopbop;
1583                 case fsub_op:
1584                         handler.b = ieee754dp_sub;
1585                         goto dcopbop;
1586                 case fmul_op:
1587                         handler.b = ieee754dp_mul;
1588                         goto dcopbop;
1589                 case fdiv_op:
1590                         handler.b = ieee754dp_div;
1591                         goto dcopbop;
1592
1593                         /* unary  ops */
1594                 case fsqrt_op:
1595                         if (!cpu_has_mips_2_3_4_5_r)
1596                                 return SIGILL;
1597
1598                         handler.u = ieee754dp_sqrt;
1599                         goto dcopuop;
1600                 /*
1601                  * Note that on some MIPS IV implementations such as the
1602                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1603                  * achieve full IEEE-754 accuracy - however this emulator does.
1604                  */
1605                 case frsqrt_op:
1606                         if (!cpu_has_mips_4_5_r2)
1607                                 return SIGILL;
1608
1609                         handler.u = fpemu_dp_rsqrt;
1610                         goto dcopuop;
1611                 case frecip_op:
1612                         if (!cpu_has_mips_4_5_r2)
1613                                 return SIGILL;
1614
1615                         handler.u = fpemu_dp_recip;
1616                         goto dcopuop;
1617                 case fmovc_op:
1618                         if (!cpu_has_mips_4_5_r)
1619                                 return SIGILL;
1620
1621                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1622                         if (((ctx->fcr31 & cond) != 0) !=
1623                                 ((MIPSInst_FT(ir) & 1) != 0))
1624                                 return 0;
1625                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1626                         break;
1627                 case fmovz_op:
1628                         if (!cpu_has_mips_4_5_r)
1629                                 return SIGILL;
1630
1631                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1632                                 return 0;
1633                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1634                         break;
1635                 case fmovn_op:
1636                         if (!cpu_has_mips_4_5_r)
1637                                 return SIGILL;
1638
1639                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1640                                 return 0;
1641                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1642                         break;
1643                 case fabs_op:
1644                         handler.u = ieee754dp_abs;
1645                         goto dcopuop;
1646
1647                 case fneg_op:
1648                         handler.u = ieee754dp_neg;
1649                         goto dcopuop;
1650
1651                 case fmov_op:
1652                         /* an easy one */
1653                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1654                         goto copcsr;
1655
1656                         /* binary op on handler */
1657 dcopbop:
1658                         DPFROMREG(fs, MIPSInst_FS(ir));
1659                         DPFROMREG(ft, MIPSInst_FT(ir));
1660
1661                         rv.d = (*handler.b) (fs, ft);
1662                         goto copcsr;
1663 dcopuop:
1664                         DPFROMREG(fs, MIPSInst_FS(ir));
1665                         rv.d = (*handler.u) (fs);
1666                         goto copcsr;
1667
1668                 /*
1669                  * unary conv ops
1670                  */
1671                 case fcvts_op:
1672                         DPFROMREG(fs, MIPSInst_FS(ir));
1673                         rv.s = ieee754sp_fdp(fs);
1674                         rfmt = s_fmt;
1675                         goto copcsr;
1676
1677                 case fcvtd_op:
1678                         return SIGILL;  /* not defined */
1679
1680                 case fcvtw_op:
1681                         DPFROMREG(fs, MIPSInst_FS(ir));
1682                         rv.w = ieee754dp_tint(fs);      /* wrong */
1683                         rfmt = w_fmt;
1684                         goto copcsr;
1685
1686                 case fround_op:
1687                 case ftrunc_op:
1688                 case fceil_op:
1689                 case ffloor_op:
1690                         if (!cpu_has_mips_2_3_4_5_r)
1691                                 return SIGILL;
1692
1693                         oldrm = ieee754_csr.rm;
1694                         DPFROMREG(fs, MIPSInst_FS(ir));
1695                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1696                         rv.w = ieee754dp_tint(fs);
1697                         ieee754_csr.rm = oldrm;
1698                         rfmt = w_fmt;
1699                         goto copcsr;
1700
1701                 case fcvtl_op:
1702                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1703                                 return SIGILL;
1704
1705                         DPFROMREG(fs, MIPSInst_FS(ir));
1706                         rv.l = ieee754dp_tlong(fs);
1707                         rfmt = l_fmt;
1708                         goto copcsr;
1709
1710                 case froundl_op:
1711                 case ftruncl_op:
1712                 case fceill_op:
1713                 case ffloorl_op:
1714                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1715                                 return SIGILL;
1716
1717                         oldrm = ieee754_csr.rm;
1718                         DPFROMREG(fs, MIPSInst_FS(ir));
1719                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1720                         rv.l = ieee754dp_tlong(fs);
1721                         ieee754_csr.rm = oldrm;
1722                         rfmt = l_fmt;
1723                         goto copcsr;
1724
1725                 default:
1726                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1727                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1728                                 union ieee754dp fs, ft;
1729
1730                                 DPFROMREG(fs, MIPSInst_FS(ir));
1731                                 DPFROMREG(ft, MIPSInst_FT(ir));
1732                                 rv.w = ieee754dp_cmp(fs, ft,
1733                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1734                                 rfmt = -1;
1735                                 if ((cmpop & 0x8)
1736                                         &&
1737                                         ieee754_cxtest
1738                                         (IEEE754_INVALID_OPERATION))
1739                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1740                                 else
1741                                         goto copcsr;
1742
1743                         }
1744                         else {
1745                                 return SIGILL;
1746                         }
1747                         break;
1748                 }
1749                 break;
1750
1751         case w_fmt:
1752                 switch (MIPSInst_FUNC(ir)) {
1753                 case fcvts_op:
1754                         /* convert word to single precision real */
1755                         SPFROMREG(fs, MIPSInst_FS(ir));
1756                         rv.s = ieee754sp_fint(fs.bits);
1757                         rfmt = s_fmt;
1758                         goto copcsr;
1759                 case fcvtd_op:
1760                         /* convert word to double precision real */
1761                         SPFROMREG(fs, MIPSInst_FS(ir));
1762                         rv.d = ieee754dp_fint(fs.bits);
1763                         rfmt = d_fmt;
1764                         goto copcsr;
1765                 default:
1766                         return SIGILL;
1767                 }
1768                 break;
1769         }
1770
1771         case l_fmt:
1772
1773                 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1774                         return SIGILL;
1775
1776                 DIFROMREG(bits, MIPSInst_FS(ir));
1777
1778                 switch (MIPSInst_FUNC(ir)) {
1779                 case fcvts_op:
1780                         /* convert long to single precision real */
1781                         rv.s = ieee754sp_flong(bits);
1782                         rfmt = s_fmt;
1783                         goto copcsr;
1784                 case fcvtd_op:
1785                         /* convert long to double precision real */
1786                         rv.d = ieee754dp_flong(bits);
1787                         rfmt = d_fmt;
1788                         goto copcsr;
1789                 default:
1790                         return SIGILL;
1791                 }
1792                 break;
1793
1794         default:
1795                 return SIGILL;
1796         }
1797
1798         /*
1799          * Update the fpu CSR register for this operation.
1800          * If an exception is required, generate a tidy SIGFPE exception,
1801          * without updating the result register.
1802          * Note: cause exception bits do not accumulate, they are rewritten
1803          * for each op; only the flag/sticky bits accumulate.
1804          */
1805         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1806         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1807                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1808                 return SIGFPE;
1809         }
1810
1811         /*
1812          * Now we can safely write the result back to the register file.
1813          */
1814         switch (rfmt) {
1815         case -1:
1816
1817                 if (cpu_has_mips_4_5_r)
1818                         cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1819                 else
1820                         cbit = FPU_CSR_COND;
1821                 if (rv.w)
1822                         ctx->fcr31 |= cbit;
1823                 else
1824                         ctx->fcr31 &= ~cbit;
1825                 break;
1826
1827         case d_fmt:
1828                 DPTOREG(rv.d, MIPSInst_FD(ir));
1829                 break;
1830         case s_fmt:
1831                 SPTOREG(rv.s, MIPSInst_FD(ir));
1832                 break;
1833         case w_fmt:
1834                 SITOREG(rv.w, MIPSInst_FD(ir));
1835                 break;
1836         case l_fmt:
1837                 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1838                         return SIGILL;
1839
1840                 DITOREG(rv.l, MIPSInst_FD(ir));
1841                 break;
1842         default:
1843                 return SIGILL;
1844         }
1845
1846         return 0;
1847 }
1848
1849 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1850         int has_fpu, void *__user *fault_addr)
1851 {
1852         unsigned long oldepc, prevepc;
1853         struct mm_decoded_insn dec_insn;
1854         u16 instr[4];
1855         u16 *instr_ptr;
1856         int sig = 0;
1857
1858         oldepc = xcp->cp0_epc;
1859         do {
1860                 prevepc = xcp->cp0_epc;
1861
1862                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1863                         /*
1864                          * Get next 2 microMIPS instructions and convert them
1865                          * into 32-bit instructions.
1866                          */
1867                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
1868                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
1869                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
1870                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
1871                                 MIPS_FPU_EMU_INC_STATS(errors);
1872                                 return SIGBUS;
1873                         }
1874                         instr_ptr = instr;
1875
1876                         /* Get first instruction. */
1877                         if (mm_insn_16bit(*instr_ptr)) {
1878                                 /* Duplicate the half-word. */
1879                                 dec_insn.insn = (*instr_ptr << 16) |
1880                                         (*instr_ptr);
1881                                 /* 16-bit instruction. */
1882                                 dec_insn.pc_inc = 2;
1883                                 instr_ptr += 1;
1884                         } else {
1885                                 dec_insn.insn = (*instr_ptr << 16) |
1886                                         *(instr_ptr+1);
1887                                 /* 32-bit instruction. */
1888                                 dec_insn.pc_inc = 4;
1889                                 instr_ptr += 2;
1890                         }
1891                         /* Get second instruction. */
1892                         if (mm_insn_16bit(*instr_ptr)) {
1893                                 /* Duplicate the half-word. */
1894                                 dec_insn.next_insn = (*instr_ptr << 16) |
1895                                         (*instr_ptr);
1896                                 /* 16-bit instruction. */
1897                                 dec_insn.next_pc_inc = 2;
1898                         } else {
1899                                 dec_insn.next_insn = (*instr_ptr << 16) |
1900                                         *(instr_ptr+1);
1901                                 /* 32-bit instruction. */
1902                                 dec_insn.next_pc_inc = 4;
1903                         }
1904                         dec_insn.micro_mips_mode = 1;
1905                 } else {
1906                         if ((get_user(dec_insn.insn,
1907                             (mips_instruction __user *) xcp->cp0_epc)) ||
1908                             (get_user(dec_insn.next_insn,
1909                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
1910                                 MIPS_FPU_EMU_INC_STATS(errors);
1911                                 return SIGBUS;
1912                         }
1913                         dec_insn.pc_inc = 4;
1914                         dec_insn.next_pc_inc = 4;
1915                         dec_insn.micro_mips_mode = 0;
1916                 }
1917
1918                 if ((dec_insn.insn == 0) ||
1919                    ((dec_insn.pc_inc == 2) &&
1920                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
1921                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
1922                 else {
1923                         /*
1924                          * The 'ieee754_csr' is an alias of
1925                          * ctx->fcr31.  No need to copy ctx->fcr31 to
1926                          * ieee754_csr.  But ieee754_csr.rm is ieee
1927                          * library modes. (not mips rounding mode)
1928                          */
1929                         /* convert to ieee library modes */
1930                         ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1931                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1932                         /* revert to mips rounding mode */
1933                         ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1934                 }
1935
1936                 if (has_fpu)
1937                         break;
1938                 if (sig)
1939                         break;
1940
1941                 cond_resched();
1942         } while (xcp->cp0_epc > prevepc);
1943
1944         /* SIGILL indicates a non-fpu instruction */
1945         if (sig == SIGILL && xcp->cp0_epc != oldepc)
1946                 /* but if EPC has advanced, then ignore it */
1947                 sig = 0;
1948
1949         return sig;
1950 }