d2072cd385922db78c5b1278622ad4d4243a4949
[pandora-kernel.git] / arch / mips / kernel / irq-gic.c
1 #undef DEBUG
2
3 #include <linux/bitmap.h>
4 #include <linux/init.h>
5 #include <linux/smp.h>
6
7 #include <asm/io.h>
8 #include <asm/gic.h>
9 #include <asm/gcmpregs.h>
10 #include <asm/mips-boards/maltaint.h>
11 #include <asm/irq.h>
12 #include <linux/hardirq.h>
13 #include <asm-generic/bitops/find.h>
14
15
16 static unsigned long _gic_base;
17 static unsigned int _irqbase, _mapsize, numvpes, numintrs;
18 static struct gic_intr_map *_intrmap;
19
20 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
21 static struct gic_pending_regs pending_regs[NR_CPUS];
22 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
23
24 #define gic_wedgeb2bok 0        /*
25                                  * Can GIC handle b2b writes to wedge register?
26                                  */
27 #if gic_wedgeb2bok == 0
28 static DEFINE_SPINLOCK(gic_wedgeb2b_lock);
29 #endif
30
31 void gic_send_ipi(unsigned int intr)
32 {
33 #if gic_wedgeb2bok == 0
34         unsigned long flags;
35 #endif
36         pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
37                  read_c0_status());
38         if (!gic_wedgeb2bok)
39                 spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
40         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
41         if (!gic_wedgeb2bok) {
42                 (void) GIC_REG(SHARED, GIC_SH_CONFIG);
43                 spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
44         }
45 }
46
47 /* This is Malta specific and needs to be exported */
48 static void vpe_local_setup(unsigned int numvpes)
49 {
50         int i;
51         unsigned long timer_interrupt = 5, perf_interrupt = 5;
52         unsigned int vpe_ctl;
53
54         /*
55          * Setup the default performance counter timer interrupts
56          * for all VPEs
57          */
58         for (i = 0; i < numvpes; i++) {
59                 GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
60
61                 /* Are Interrupts locally routable? */
62                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
63                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
64                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
65                                  GIC_MAP_TO_PIN_MSK | timer_interrupt);
66
67                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
68                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
69                                  GIC_MAP_TO_PIN_MSK | perf_interrupt);
70         }
71 }
72
73 unsigned int gic_get_int(void)
74 {
75         unsigned int i;
76         unsigned long *pending, *intrmask, *pcpu_mask;
77         unsigned long *pending_abs, *intrmask_abs;
78
79         /* Get per-cpu bitmaps */
80         pending = pending_regs[smp_processor_id()].pending;
81         intrmask = intrmask_regs[smp_processor_id()].intrmask;
82         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
83
84         pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
85                                                          GIC_SH_PEND_31_0_OFS);
86         intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
87                                                           GIC_SH_MASK_31_0_OFS);
88
89         for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
90                 GICREAD(*pending_abs, pending[i]);
91                 GICREAD(*intrmask_abs, intrmask[i]);
92                 pending_abs++;
93                 intrmask_abs++;
94         }
95
96         bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
97         bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
98
99         i = find_first_bit(pending, GIC_NUM_INTRS);
100
101         pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);
102
103         return i;
104 }
105
106 static unsigned int gic_irq_startup(unsigned int irq)
107 {
108         pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
109         irq -= _irqbase;
110         GIC_SET_INTR_MASK(irq, 1);
111         return 0;
112 }
113
114 static void gic_irq_ack(unsigned int irq)
115 {
116 #if gic_wedgeb2bok == 0
117         unsigned long flags;
118 #endif
119         pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
120         irq -= _irqbase;
121         GIC_CLR_INTR_MASK(irq, 1);
122
123         if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) {
124                 if (!gic_wedgeb2bok)
125                         spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
126                 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
127                 if (!gic_wedgeb2bok) {
128                         (void) GIC_REG(SHARED, GIC_SH_CONFIG);
129                         spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
130                 }
131         }
132 }
133
134 static void gic_mask_irq(unsigned int irq)
135 {
136         pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
137         irq -= _irqbase;
138         GIC_CLR_INTR_MASK(irq, 1);
139 }
140
141 static void gic_unmask_irq(unsigned int irq)
142 {
143         pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
144         irq -= _irqbase;
145         GIC_SET_INTR_MASK(irq, 1);
146 }
147
148 #ifdef CONFIG_SMP
149
150 static DEFINE_SPINLOCK(gic_lock);
151
152 static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
153 {
154         cpumask_t       tmp = CPU_MASK_NONE;
155         unsigned long   flags;
156         int             i;
157
158         pr_debug(KERN_DEBUG "%s called\n", __func__);
159         irq -= _irqbase;
160
161         cpumask_and(&tmp, cpumask, cpu_online_mask);
162         if (cpus_empty(tmp))
163                 return -1;
164
165         /* Assumption : cpumask refers to a single CPU */
166         spin_lock_irqsave(&gic_lock, flags);
167         for (;;) {
168                 /* Re-route this IRQ */
169                 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
170
171                 /*
172                  * FIXME: assumption that _intrmap is ordered and has no holes
173                  */
174
175                 /* Update the intr_map */
176                 _intrmap[irq].cpunum = first_cpu(tmp);
177
178                 /* Update the pcpu_masks */
179                 for (i = 0; i < NR_CPUS; i++)
180                         clear_bit(irq, pcpu_masks[i].pcpu_mask);
181                 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
182
183         }
184         cpumask_copy(irq_desc[irq].affinity, cpumask);
185         spin_unlock_irqrestore(&gic_lock, flags);
186
187         return 0;
188 }
189 #endif
190
191 static struct irq_chip gic_irq_controller = {
192         .name           =       "MIPS GIC",
193         .startup        =       gic_irq_startup,
194         .ack            =       gic_irq_ack,
195         .mask           =       gic_mask_irq,
196         .mask_ack       =       gic_mask_irq,
197         .unmask         =       gic_unmask_irq,
198         .eoi            =       gic_unmask_irq,
199 #ifdef CONFIG_SMP
200         .set_affinity   =       gic_set_affinity,
201 #endif
202 };
203
204 static void __init setup_intr(unsigned int intr, unsigned int cpu,
205         unsigned int pin, unsigned int polarity, unsigned int trigtype)
206 {
207         /* Setup Intr to Pin mapping */
208         if (pin & GIC_MAP_TO_NMI_MSK) {
209                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
210                 /* FIXME: hack to route NMI to all cpu's */
211                 for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
212                         GICWRITE(GIC_REG_ADDR(SHARED,
213                                           GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
214                                  0xffffffff);
215                 }
216         } else {
217                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
218                          GIC_MAP_TO_PIN_MSK | pin);
219                 /* Setup Intr to CPU mapping */
220                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
221         }
222
223         /* Setup Intr Polarity */
224         GIC_SET_POLARITY(intr, polarity);
225
226         /* Setup Intr Trigger Type */
227         GIC_SET_TRIGGER(intr, trigtype);
228
229         /* Init Intr Masks */
230         GIC_SET_INTR_MASK(intr, 0);
231 }
232
233 static void __init gic_basic_init(void)
234 {
235         unsigned int i, cpu;
236
237         /* Setup defaults */
238         for (i = 0; i < GIC_NUM_INTRS; i++) {
239                 GIC_SET_POLARITY(i, GIC_POL_POS);
240                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
241                 GIC_SET_INTR_MASK(i, 0);
242         }
243
244         /* Setup specifics */
245         for (i = 0; i < _mapsize; i++) {
246                 cpu = _intrmap[i].cpunum;
247                 if (cpu == X)
248                         continue;
249
250                 if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 &&
251                                         _intrmap[i].ipiflag == 0)
252                         continue;
253
254                 setup_intr(_intrmap[i].intrnum,
255                                 _intrmap[i].cpunum,
256                                 _intrmap[i].pin,
257                                 _intrmap[i].polarity,
258                                 _intrmap[i].trigtype);
259                 /* Initialise per-cpu Interrupt software masks */
260                 if (_intrmap[i].ipiflag)
261                         set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask);
262         }
263
264         vpe_local_setup(numvpes);
265
266         for (i = _irqbase; i < (_irqbase + numintrs); i++)
267                 set_irq_chip(i, &gic_irq_controller);
268 }
269
270 void __init gic_init(unsigned long gic_base_addr,
271                      unsigned long gic_addrspace_size,
272                      struct gic_intr_map *intr_map, unsigned int intr_map_size,
273                      unsigned int irqbase)
274 {
275         unsigned int gicconfig;
276
277         _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
278                                                     gic_addrspace_size);
279         _irqbase = irqbase;
280         _intrmap = intr_map;
281         _mapsize = intr_map_size;
282
283         GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
284         numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
285                    GIC_SH_CONFIG_NUMINTRS_SHF;
286         numintrs = ((numintrs + 1) * 8);
287
288         numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
289                   GIC_SH_CONFIG_NUMVPES_SHF;
290
291         pr_debug("%s called\n", __func__);
292
293         gic_basic_init();
294 }