2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
28 #include <mach/mcbsp.h>
30 struct omap_mcbsp **mcbsp_ptr;
33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
35 if (cpu_class_is_omap1() || cpu_is_omap2420())
36 __raw_writew((u16)val, io_base + reg);
38 __raw_writel(val, io_base + reg);
41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base + reg);
46 return __raw_readl(io_base + reg);
49 #define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51 #define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
54 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
57 static void omap_mcbsp_dump_reg(u8 id)
59 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
61 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
62 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
64 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
66 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
67 OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
68 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
69 OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
70 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
71 OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
72 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
73 OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
74 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
75 OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
76 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
77 OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
78 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
79 OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
80 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
81 OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
82 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
83 OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
84 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
85 OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
86 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
88 dev_dbg(mcbsp->dev, "***********************\n");
91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
93 struct omap_mcbsp *mcbsp_tx = dev_id;
96 irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
97 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
99 if (irqst_spcr2 & XSYNC_ERR) {
100 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
102 /* Writing zero to XSYNC_ERR clears the IRQ */
103 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
104 irqst_spcr2 & ~(XSYNC_ERR));
106 complete(&mcbsp_tx->tx_irq_completion);
112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
114 struct omap_mcbsp *mcbsp_rx = dev_id;
117 irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
118 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
120 if (irqst_spcr1 & RSYNC_ERR) {
121 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
123 /* Writing zero to RSYNC_ERR clears the IRQ */
124 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
125 irqst_spcr1 & ~(RSYNC_ERR));
127 complete(&mcbsp_rx->tx_irq_completion);
133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
135 struct omap_mcbsp *mcbsp_dma_tx = data;
137 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
138 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
140 /* We can free the channels */
141 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
142 mcbsp_dma_tx->dma_tx_lch = -1;
144 complete(&mcbsp_dma_tx->tx_dma_completion);
147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
149 struct omap_mcbsp *mcbsp_dma_rx = data;
151 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
152 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
154 /* We can free the channels */
155 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
156 mcbsp_dma_rx->dma_rx_lch = -1;
158 complete(&mcbsp_dma_rx->rx_dma_completion);
162 * omap_mcbsp_config simply write a config to the
164 * You either call this function or set the McBSP registers
165 * by yourself before calling omap_mcbsp_start().
167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
169 struct omap_mcbsp *mcbsp;
170 void __iomem *io_base;
172 if (!omap_mcbsp_check_valid_id(id)) {
173 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
176 mcbsp = id_to_mcbsp_ptr(id);
178 io_base = mcbsp->io_base;
179 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
180 mcbsp->id, mcbsp->phys_base);
182 /* We write the given config */
183 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
184 OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
185 OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
186 OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
187 OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
188 OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
189 OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
190 OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
194 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
199 EXPORT_SYMBOL(omap_mcbsp_config);
201 #ifdef CONFIG_ARCH_OMAP34XX
203 * omap_mcbsp_set_tx_threshold configures how to deal
204 * with transmit threshold. the threshold value and handler can be
207 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
209 struct omap_mcbsp *mcbsp;
210 void __iomem *io_base;
212 if (!cpu_is_omap34xx())
215 if (!omap_mcbsp_check_valid_id(id)) {
216 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
219 mcbsp = id_to_mcbsp_ptr(id);
220 io_base = mcbsp->io_base;
222 OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
227 * omap_mcbsp_set_rx_threshold configures how to deal
228 * with receive threshold. the threshold value and handler can be
231 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
233 struct omap_mcbsp *mcbsp;
234 void __iomem *io_base;
236 if (!cpu_is_omap34xx())
239 if (!omap_mcbsp_check_valid_id(id)) {
240 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
243 mcbsp = id_to_mcbsp_ptr(id);
244 io_base = mcbsp->io_base;
246 OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
251 * omap_mcbsp_get_max_tx_thres just return the current configured
252 * maximum threshold for transmission
254 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
256 struct omap_mcbsp *mcbsp;
258 if (!omap_mcbsp_check_valid_id(id)) {
259 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
262 mcbsp = id_to_mcbsp_ptr(id);
264 return mcbsp->max_tx_thres;
266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
269 * omap_mcbsp_get_max_rx_thres just return the current configured
270 * maximum threshold for reception
272 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
274 struct omap_mcbsp *mcbsp;
276 if (!omap_mcbsp_check_valid_id(id)) {
277 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
280 mcbsp = id_to_mcbsp_ptr(id);
282 return mcbsp->max_rx_thres;
284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
287 * omap_mcbsp_get_dma_op_mode just return the current configured
288 * operating mode for the mcbsp channel
290 int omap_mcbsp_get_dma_op_mode(unsigned int id)
292 struct omap_mcbsp *mcbsp;
295 if (!omap_mcbsp_check_valid_id(id)) {
296 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
299 mcbsp = id_to_mcbsp_ptr(id);
301 spin_lock_irq(&mcbsp->lock);
302 dma_op_mode = mcbsp->dma_op_mode;
303 spin_unlock_irq(&mcbsp->lock);
307 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
309 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
312 * Enable wakup behavior, smart idle and all wakeups
313 * REVISIT: some wakeups may be unnecessary
315 if (cpu_is_omap34xx()) {
318 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
319 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
321 spin_lock_irq(&mcbsp->lock);
322 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
323 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
324 CLOCKACTIVITY(0x02));
325 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
328 syscon |= SIDLEMODE(0x01);
330 spin_unlock_irq(&mcbsp->lock);
332 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
336 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
339 * Disable wakup behavior, smart idle and all wakeups
341 if (cpu_is_omap34xx()) {
344 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
345 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
347 * HW bug workaround - If no_idle mode is taken, we need to
348 * go to smart_idle before going to always_idle, or the
349 * device will not hit retention anymore.
351 syscon |= SIDLEMODE(0x02);
352 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
354 syscon &= ~(SIDLEMODE(0x03));
355 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
357 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
361 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
362 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
366 * We can choose between IRQ based or polled IO.
367 * This needs to be called before omap_mcbsp_request().
369 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
371 struct omap_mcbsp *mcbsp;
373 if (!omap_mcbsp_check_valid_id(id)) {
374 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
377 mcbsp = id_to_mcbsp_ptr(id);
379 spin_lock(&mcbsp->lock);
382 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
384 spin_unlock(&mcbsp->lock);
388 mcbsp->io_type = io_type;
390 spin_unlock(&mcbsp->lock);
394 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
396 int omap_mcbsp_request(unsigned int id)
398 struct omap_mcbsp *mcbsp;
401 if (!omap_mcbsp_check_valid_id(id)) {
402 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
405 mcbsp = id_to_mcbsp_ptr(id);
407 spin_lock(&mcbsp->lock);
409 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
411 spin_unlock(&mcbsp->lock);
416 spin_unlock(&mcbsp->lock);
418 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
419 mcbsp->pdata->ops->request(id);
421 clk_enable(mcbsp->iclk);
422 clk_enable(mcbsp->fclk);
424 /* Do procedure specific to omap34xx arch, if applicable */
425 omap34xx_mcbsp_request(mcbsp);
428 * Make sure that transmitter, receiver and sample-rate generator are
429 * not running before activating IRQs.
431 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
432 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
434 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
435 /* We need to get IRQs here */
436 init_completion(&mcbsp->tx_irq_completion);
437 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
438 0, "McBSP", (void *)mcbsp);
440 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
441 "for McBSP%d\n", mcbsp->tx_irq,
446 init_completion(&mcbsp->rx_irq_completion);
447 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
448 0, "McBSP", (void *)mcbsp);
450 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
451 "for McBSP%d\n", mcbsp->rx_irq,
453 free_irq(mcbsp->tx_irq, (void *)mcbsp);
460 EXPORT_SYMBOL(omap_mcbsp_request);
462 void omap_mcbsp_free(unsigned int id)
464 struct omap_mcbsp *mcbsp;
466 if (!omap_mcbsp_check_valid_id(id)) {
467 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
470 mcbsp = id_to_mcbsp_ptr(id);
472 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
473 mcbsp->pdata->ops->free(id);
475 /* Do procedure specific to omap34xx arch, if applicable */
476 omap34xx_mcbsp_free(mcbsp);
478 clk_disable(mcbsp->fclk);
479 clk_disable(mcbsp->iclk);
481 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
483 free_irq(mcbsp->rx_irq, (void *)mcbsp);
484 free_irq(mcbsp->tx_irq, (void *)mcbsp);
487 spin_lock(&mcbsp->lock);
489 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
491 spin_unlock(&mcbsp->lock);
496 spin_unlock(&mcbsp->lock);
498 EXPORT_SYMBOL(omap_mcbsp_free);
501 * Here we start the McBSP, by enabling transmitter, receiver or both.
502 * If no transmitter or receiver is active prior calling, then sample-rate
503 * generator and frame sync are started.
505 void omap_mcbsp_start(unsigned int id, int tx, int rx)
507 struct omap_mcbsp *mcbsp;
508 void __iomem *io_base;
512 if (!omap_mcbsp_check_valid_id(id)) {
513 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
516 mcbsp = id_to_mcbsp_ptr(id);
517 io_base = mcbsp->io_base;
519 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
520 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
522 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
523 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
526 /* Start the sample generator */
527 w = OMAP_MCBSP_READ(io_base, SPCR2);
528 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
531 /* Enable transmitter and receiver */
532 w = OMAP_MCBSP_READ(io_base, SPCR2);
533 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (tx & 1));
535 w = OMAP_MCBSP_READ(io_base, SPCR1);
536 OMAP_MCBSP_WRITE(io_base, SPCR1, w | (rx & 1));
539 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
540 * REVISIT: 100us may give enough time for two CLKSRG, however
541 * due to some unknown PM related, clock gating etc. reason it
547 /* Start frame sync */
548 w = OMAP_MCBSP_READ(io_base, SPCR2);
549 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
552 /* Dump McBSP Regs */
553 omap_mcbsp_dump_reg(id);
555 EXPORT_SYMBOL(omap_mcbsp_start);
557 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
559 struct omap_mcbsp *mcbsp;
560 void __iomem *io_base;
564 if (!omap_mcbsp_check_valid_id(id)) {
565 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
569 mcbsp = id_to_mcbsp_ptr(id);
570 io_base = mcbsp->io_base;
572 /* Reset transmitter */
573 w = OMAP_MCBSP_READ(io_base, SPCR2);
574 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(tx & 1));
577 w = OMAP_MCBSP_READ(io_base, SPCR1);
578 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(rx & 1));
580 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
581 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
584 /* Reset the sample rate generator */
585 w = OMAP_MCBSP_READ(io_base, SPCR2);
586 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
589 EXPORT_SYMBOL(omap_mcbsp_stop);
591 void omap_mcbsp_xmit_enable(unsigned int id, u8 enable)
593 struct omap_mcbsp *mcbsp;
594 void __iomem *io_base;
597 if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
600 if (!omap_mcbsp_check_valid_id(id)) {
601 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
605 mcbsp = id_to_mcbsp_ptr(id);
606 io_base = mcbsp->io_base;
608 w = OMAP_MCBSP_READ(io_base, XCCR);
611 OMAP_MCBSP_WRITE(io_base, XCCR, w & ~(XDISABLE));
613 OMAP_MCBSP_WRITE(io_base, XCCR, w | XDISABLE);
615 EXPORT_SYMBOL(omap_mcbsp_xmit_enable);
617 void omap_mcbsp_recv_enable(unsigned int id, u8 enable)
619 struct omap_mcbsp *mcbsp;
620 void __iomem *io_base;
623 if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
626 if (!omap_mcbsp_check_valid_id(id)) {
627 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
631 mcbsp = id_to_mcbsp_ptr(id);
632 io_base = mcbsp->io_base;
634 w = OMAP_MCBSP_READ(io_base, RCCR);
637 OMAP_MCBSP_WRITE(io_base, RCCR, w & ~(RDISABLE));
639 OMAP_MCBSP_WRITE(io_base, RCCR, w | RDISABLE);
641 EXPORT_SYMBOL(omap_mcbsp_recv_enable);
643 /* polled mcbsp i/o operations */
644 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
646 struct omap_mcbsp *mcbsp;
649 if (!omap_mcbsp_check_valid_id(id)) {
650 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
654 mcbsp = id_to_mcbsp_ptr(id);
655 base = mcbsp->io_base;
657 writew(buf, base + OMAP_MCBSP_REG_DXR1);
658 /* if frame sync error - clear the error */
659 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
661 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
662 base + OMAP_MCBSP_REG_SPCR2);
666 /* wait for transmit confirmation */
668 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
669 if (attemps++ > 1000) {
670 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
672 base + OMAP_MCBSP_REG_SPCR2);
674 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
676 base + OMAP_MCBSP_REG_SPCR2);
678 dev_err(mcbsp->dev, "Could not write to"
679 " McBSP%d Register\n", mcbsp->id);
687 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
689 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
691 struct omap_mcbsp *mcbsp;
694 if (!omap_mcbsp_check_valid_id(id)) {
695 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
698 mcbsp = id_to_mcbsp_ptr(id);
700 base = mcbsp->io_base;
701 /* if frame sync error - clear the error */
702 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
704 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
705 base + OMAP_MCBSP_REG_SPCR1);
709 /* wait for recieve confirmation */
711 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
712 if (attemps++ > 1000) {
713 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
715 base + OMAP_MCBSP_REG_SPCR1);
717 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
719 base + OMAP_MCBSP_REG_SPCR1);
721 dev_err(mcbsp->dev, "Could not read from"
722 " McBSP%d Register\n", mcbsp->id);
727 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
731 EXPORT_SYMBOL(omap_mcbsp_pollread);
734 * IRQ based word transmission.
736 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
738 struct omap_mcbsp *mcbsp;
739 void __iomem *io_base;
740 omap_mcbsp_word_length word_length;
742 if (!omap_mcbsp_check_valid_id(id)) {
743 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
747 mcbsp = id_to_mcbsp_ptr(id);
748 io_base = mcbsp->io_base;
749 word_length = mcbsp->tx_word_length;
751 wait_for_completion(&mcbsp->tx_irq_completion);
753 if (word_length > OMAP_MCBSP_WORD_16)
754 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
755 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
757 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
759 u32 omap_mcbsp_recv_word(unsigned int id)
761 struct omap_mcbsp *mcbsp;
762 void __iomem *io_base;
763 u16 word_lsb, word_msb = 0;
764 omap_mcbsp_word_length word_length;
766 if (!omap_mcbsp_check_valid_id(id)) {
767 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
770 mcbsp = id_to_mcbsp_ptr(id);
772 word_length = mcbsp->rx_word_length;
773 io_base = mcbsp->io_base;
775 wait_for_completion(&mcbsp->rx_irq_completion);
777 if (word_length > OMAP_MCBSP_WORD_16)
778 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
779 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
781 return (word_lsb | (word_msb << 16));
783 EXPORT_SYMBOL(omap_mcbsp_recv_word);
785 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
787 struct omap_mcbsp *mcbsp;
788 void __iomem *io_base;
789 omap_mcbsp_word_length tx_word_length;
790 omap_mcbsp_word_length rx_word_length;
791 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
793 if (!omap_mcbsp_check_valid_id(id)) {
794 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
797 mcbsp = id_to_mcbsp_ptr(id);
798 io_base = mcbsp->io_base;
799 tx_word_length = mcbsp->tx_word_length;
800 rx_word_length = mcbsp->rx_word_length;
802 if (tx_word_length != rx_word_length)
805 /* First we wait for the transmitter to be ready */
806 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
807 while (!(spcr2 & XRDY)) {
808 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
809 if (attempts++ > 1000) {
810 /* We must reset the transmitter */
811 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
813 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
815 dev_err(mcbsp->dev, "McBSP%d transmitter not "
816 "ready\n", mcbsp->id);
821 /* Now we can push the data */
822 if (tx_word_length > OMAP_MCBSP_WORD_16)
823 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
824 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
826 /* We wait for the receiver to be ready */
827 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
828 while (!(spcr1 & RRDY)) {
829 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
830 if (attempts++ > 1000) {
831 /* We must reset the receiver */
832 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
834 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
836 dev_err(mcbsp->dev, "McBSP%d receiver not "
837 "ready\n", mcbsp->id);
842 /* Receiver is ready, let's read the dummy data */
843 if (rx_word_length > OMAP_MCBSP_WORD_16)
844 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
845 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
849 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
851 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
853 struct omap_mcbsp *mcbsp;
855 void __iomem *io_base;
856 omap_mcbsp_word_length tx_word_length;
857 omap_mcbsp_word_length rx_word_length;
858 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
860 if (!omap_mcbsp_check_valid_id(id)) {
861 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
865 mcbsp = id_to_mcbsp_ptr(id);
866 io_base = mcbsp->io_base;
868 tx_word_length = mcbsp->tx_word_length;
869 rx_word_length = mcbsp->rx_word_length;
871 if (tx_word_length != rx_word_length)
874 /* First we wait for the transmitter to be ready */
875 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
876 while (!(spcr2 & XRDY)) {
877 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
878 if (attempts++ > 1000) {
879 /* We must reset the transmitter */
880 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
882 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
884 dev_err(mcbsp->dev, "McBSP%d transmitter not "
885 "ready\n", mcbsp->id);
890 /* We first need to enable the bus clock */
891 if (tx_word_length > OMAP_MCBSP_WORD_16)
892 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
893 OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
895 /* We wait for the receiver to be ready */
896 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
897 while (!(spcr1 & RRDY)) {
898 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
899 if (attempts++ > 1000) {
900 /* We must reset the receiver */
901 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
903 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
905 dev_err(mcbsp->dev, "McBSP%d receiver not "
906 "ready\n", mcbsp->id);
911 /* Receiver is ready, there is something for us */
912 if (rx_word_length > OMAP_MCBSP_WORD_16)
913 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
914 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
916 word[0] = (word_lsb | (word_msb << 16));
920 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
923 * Simple DMA based buffer rx/tx routines.
924 * Nothing fancy, just a single buffer tx/rx through DMA.
925 * The DMA resources are released once the transfer is done.
926 * For anything fancier, you should use your own customized DMA
927 * routines and callbacks.
929 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
932 struct omap_mcbsp *mcbsp;
938 if (!omap_mcbsp_check_valid_id(id)) {
939 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
942 mcbsp = id_to_mcbsp_ptr(id);
944 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
945 omap_mcbsp_tx_dma_callback,
948 dev_err(mcbsp->dev, " Unable to request DMA channel for "
949 "McBSP%d TX. Trying IRQ based TX\n",
953 mcbsp->dma_tx_lch = dma_tx_ch;
955 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
958 init_completion(&mcbsp->tx_dma_completion);
960 if (cpu_class_is_omap1()) {
961 src_port = OMAP_DMA_PORT_TIPB;
962 dest_port = OMAP_DMA_PORT_EMIFF;
964 if (cpu_class_is_omap2())
965 sync_dev = mcbsp->dma_tx_sync;
967 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
968 OMAP_DMA_DATA_TYPE_S16,
970 OMAP_DMA_SYNC_ELEMENT,
973 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
975 OMAP_DMA_AMODE_CONSTANT,
976 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
979 omap_set_dma_src_params(mcbsp->dma_tx_lch,
981 OMAP_DMA_AMODE_POST_INC,
985 omap_start_dma(mcbsp->dma_tx_lch);
986 wait_for_completion(&mcbsp->tx_dma_completion);
990 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
992 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
995 struct omap_mcbsp *mcbsp;
1001 if (!omap_mcbsp_check_valid_id(id)) {
1002 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1005 mcbsp = id_to_mcbsp_ptr(id);
1007 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1008 omap_mcbsp_rx_dma_callback,
1011 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1012 "McBSP%d RX. Trying IRQ based RX\n",
1016 mcbsp->dma_rx_lch = dma_rx_ch;
1018 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1021 init_completion(&mcbsp->rx_dma_completion);
1023 if (cpu_class_is_omap1()) {
1024 src_port = OMAP_DMA_PORT_TIPB;
1025 dest_port = OMAP_DMA_PORT_EMIFF;
1027 if (cpu_class_is_omap2())
1028 sync_dev = mcbsp->dma_rx_sync;
1030 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1031 OMAP_DMA_DATA_TYPE_S16,
1033 OMAP_DMA_SYNC_ELEMENT,
1036 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1038 OMAP_DMA_AMODE_CONSTANT,
1039 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1042 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1044 OMAP_DMA_AMODE_POST_INC,
1048 omap_start_dma(mcbsp->dma_rx_lch);
1049 wait_for_completion(&mcbsp->rx_dma_completion);
1053 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1057 * Since SPI setup is much simpler than the generic McBSP one,
1058 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1059 * Once this is done, you can call omap_mcbsp_start().
1061 void omap_mcbsp_set_spi_mode(unsigned int id,
1062 const struct omap_mcbsp_spi_cfg *spi_cfg)
1064 struct omap_mcbsp *mcbsp;
1065 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1067 if (!omap_mcbsp_check_valid_id(id)) {
1068 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1071 mcbsp = id_to_mcbsp_ptr(id);
1073 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1075 /* SPI has only one frame */
1076 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1077 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1079 /* Clock stop mode */
1080 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1081 mcbsp_cfg.spcr1 |= (1 << 12);
1083 mcbsp_cfg.spcr1 |= (3 << 11);
1085 /* Set clock parities */
1086 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1087 mcbsp_cfg.pcr0 |= CLKRP;
1089 mcbsp_cfg.pcr0 &= ~CLKRP;
1091 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1092 mcbsp_cfg.pcr0 &= ~CLKXP;
1094 mcbsp_cfg.pcr0 |= CLKXP;
1096 /* Set SCLKME to 0 and CLKSM to 1 */
1097 mcbsp_cfg.pcr0 &= ~SCLKME;
1098 mcbsp_cfg.srgr2 |= CLKSM;
1101 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1102 mcbsp_cfg.pcr0 &= ~FSXP;
1104 mcbsp_cfg.pcr0 |= FSXP;
1106 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1107 mcbsp_cfg.pcr0 |= CLKXM;
1108 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1109 mcbsp_cfg.pcr0 |= FSXM;
1110 mcbsp_cfg.srgr2 &= ~FSGM;
1111 mcbsp_cfg.xcr2 |= XDATDLY(1);
1112 mcbsp_cfg.rcr2 |= RDATDLY(1);
1114 mcbsp_cfg.pcr0 &= ~CLKXM;
1115 mcbsp_cfg.srgr1 |= CLKGDV(1);
1116 mcbsp_cfg.pcr0 &= ~FSXM;
1117 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1118 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1121 mcbsp_cfg.xcr2 &= ~XPHASE;
1122 mcbsp_cfg.rcr2 &= ~RPHASE;
1124 omap_mcbsp_config(id, &mcbsp_cfg);
1126 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1128 #ifdef CONFIG_ARCH_OMAP34XX
1129 #define max_thres(m) (mcbsp->pdata->buffer_size)
1130 #define valid_threshold(m, val) ((val) <= max_thres(m))
1131 #define THRESHOLD_PROP_BUILDER(prop) \
1132 static ssize_t prop##_show(struct device *dev, \
1133 struct device_attribute *attr, char *buf) \
1135 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1137 return sprintf(buf, "%u\n", mcbsp->prop); \
1140 static ssize_t prop##_store(struct device *dev, \
1141 struct device_attribute *attr, \
1142 const char *buf, size_t size) \
1144 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1145 unsigned long val; \
1148 status = strict_strtoul(buf, 0, &val); \
1152 if (!valid_threshold(mcbsp, val)) \
1155 mcbsp->prop = val; \
1159 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1161 THRESHOLD_PROP_BUILDER(max_tx_thres);
1162 THRESHOLD_PROP_BUILDER(max_rx_thres);
1164 static ssize_t dma_op_mode_show(struct device *dev,
1165 struct device_attribute *attr, char *buf)
1167 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1170 spin_lock_irq(&mcbsp->lock);
1171 dma_op_mode = mcbsp->dma_op_mode;
1172 spin_unlock_irq(&mcbsp->lock);
1174 return sprintf(buf, "current mode: %d\n"
1175 "possible mode values are:\n"
1180 MCBSP_DMA_MODE_ELEMENT, "element mode",
1181 MCBSP_DMA_MODE_THRESHOLD, "threshold mode",
1182 MCBSP_DMA_MODE_FRAME, "frame mode");
1185 static ssize_t dma_op_mode_store(struct device *dev,
1186 struct device_attribute *attr,
1187 const char *buf, size_t size)
1189 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1193 status = strict_strtoul(buf, 0, &val);
1197 spin_lock_irq(&mcbsp->lock);
1204 if (val > MCBSP_DMA_MODE_FRAME || val < MCBSP_DMA_MODE_ELEMENT) {
1209 mcbsp->dma_op_mode = val;
1212 spin_unlock_irq(&mcbsp->lock);
1217 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1219 static const struct attribute *additional_attrs[] = {
1220 &dev_attr_max_tx_thres.attr,
1221 &dev_attr_max_rx_thres.attr,
1222 &dev_attr_dma_op_mode.attr,
1226 static const struct attribute_group additional_attr_group = {
1227 .attrs = (struct attribute **)additional_attrs,
1230 static inline int __devinit omap_additional_add(struct device *dev)
1232 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1235 static inline void __devexit omap_additional_remove(struct device *dev)
1237 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1240 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1242 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1243 if (cpu_is_omap34xx()) {
1244 mcbsp->max_tx_thres = max_thres(mcbsp);
1245 mcbsp->max_rx_thres = max_thres(mcbsp);
1247 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1248 * for mcbsp2 instances.
1250 if (omap_additional_add(mcbsp->dev))
1251 dev_warn(mcbsp->dev,
1252 "Unable to create additional controls\n");
1254 mcbsp->max_tx_thres = -EINVAL;
1255 mcbsp->max_rx_thres = -EINVAL;
1259 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1261 if (cpu_is_omap34xx())
1262 omap_additional_remove(mcbsp->dev);
1265 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1266 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1267 #endif /* CONFIG_ARCH_OMAP34XX */
1270 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1271 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1273 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1275 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1276 struct omap_mcbsp *mcbsp;
1277 int id = pdev->id - 1;
1281 dev_err(&pdev->dev, "McBSP device initialized without"
1287 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1289 if (id >= omap_mcbsp_count) {
1290 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1295 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1301 spin_lock_init(&mcbsp->lock);
1304 mcbsp->dma_tx_lch = -1;
1305 mcbsp->dma_rx_lch = -1;
1307 mcbsp->phys_base = pdata->phys_base;
1308 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1309 if (!mcbsp->io_base) {
1314 /* Default I/O is IRQ based */
1315 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1316 mcbsp->tx_irq = pdata->tx_irq;
1317 mcbsp->rx_irq = pdata->rx_irq;
1318 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1319 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1321 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1322 if (IS_ERR(mcbsp->iclk)) {
1323 ret = PTR_ERR(mcbsp->iclk);
1324 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1328 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1329 if (IS_ERR(mcbsp->fclk)) {
1330 ret = PTR_ERR(mcbsp->fclk);
1331 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1335 mcbsp->pdata = pdata;
1336 mcbsp->dev = &pdev->dev;
1337 mcbsp_ptr[id] = mcbsp;
1338 platform_set_drvdata(pdev, mcbsp);
1340 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1341 omap34xx_device_init(mcbsp);
1346 clk_put(mcbsp->iclk);
1348 iounmap(mcbsp->io_base);
1355 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1357 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1359 platform_set_drvdata(pdev, NULL);
1362 if (mcbsp->pdata && mcbsp->pdata->ops &&
1363 mcbsp->pdata->ops->free)
1364 mcbsp->pdata->ops->free(mcbsp->id);
1366 omap34xx_device_exit(mcbsp);
1368 clk_disable(mcbsp->fclk);
1369 clk_disable(mcbsp->iclk);
1370 clk_put(mcbsp->fclk);
1371 clk_put(mcbsp->iclk);
1373 iounmap(mcbsp->io_base);
1384 static struct platform_driver omap_mcbsp_driver = {
1385 .probe = omap_mcbsp_probe,
1386 .remove = __devexit_p(omap_mcbsp_remove),
1388 .name = "omap-mcbsp",
1392 int __init omap_mcbsp_init(void)
1394 /* Register the McBSP driver */
1395 return platform_driver_register(&omap_mcbsp_driver);