2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <asm/system.h>
40 #include <mach/hardware.h>
47 #ifndef CONFIG_ARCH_OMAP1
48 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
49 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
52 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
55 #define OMAP_DMA_ACTIVE 0x01
56 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
58 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
60 static struct omap_system_dma_plat_info *p;
61 static struct omap_dma_dev_attr *d;
63 static int enable_1510_mode;
66 static struct omap_dma_global_context_registers {
68 u32 dma_ocp_sysconfig;
70 } omap_dma_global_context;
72 struct dma_link_info {
74 int no_of_lchs_linked;
85 static struct dma_link_info *dma_linked_lch;
87 #ifndef CONFIG_ARCH_OMAP1
89 /* Chain handling macros */
90 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
92 dma_linked_lch[chain_id].q_head = \
93 dma_linked_lch[chain_id].q_tail = \
94 dma_linked_lch[chain_id].q_count = 0; \
96 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
97 (dma_linked_lch[chain_id].no_of_lchs_linked == \
98 dma_linked_lch[chain_id].q_count)
99 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
101 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
102 dma_linked_lch[chain_id].q_count) \
104 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
105 (0 == dma_linked_lch[chain_id].q_count)
106 #define __OMAP_DMA_CHAIN_INCQ(end) \
107 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
108 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
110 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
111 dma_linked_lch[chain_id].q_count--; \
114 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
117 dma_linked_lch[chain_id].q_count++; \
121 static int dma_lch_count;
122 static int dma_chan_count;
123 static int omap_dma_reserve_channels;
125 static spinlock_t dma_chan_lock;
126 static struct omap_dma_lch *dma_chan;
128 static inline void disable_lnk(int lch);
129 static void omap_disable_channel_irq(int lch);
130 static inline void omap_enable_channel_irq(int lch);
132 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
135 #ifdef CONFIG_ARCH_OMAP15XX
136 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
137 static int omap_dma_in_1510_mode(void)
139 return enable_1510_mode;
142 #define omap_dma_in_1510_mode() 0
145 #ifdef CONFIG_ARCH_OMAP1
146 static inline int get_gdma_dev(int req)
148 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
149 int shift = ((req - 1) % 5) * 6;
151 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
154 static inline void set_gdma_dev(int req, int dev)
156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157 int shift = ((req - 1) % 5) * 6;
161 l &= ~(0x3f << shift);
162 l |= (dev - 1) << shift;
166 #define set_gdma_dev(req, dev) do {} while (0)
169 void omap_set_dma_priority(int lch, int dst_port, int priority)
174 if (cpu_class_is_omap1()) {
176 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
177 reg = OMAP_TC_OCPT1_PRIOR;
179 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
180 reg = OMAP_TC_OCPT2_PRIOR;
182 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
183 reg = OMAP_TC_EMIFF_PRIOR;
185 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
186 reg = OMAP_TC_EMIFS_PRIOR;
194 l |= (priority & 0xf) << 8;
198 if (cpu_class_is_omap2()) {
201 ccr = p->dma_read(CCR, lch);
206 p->dma_write(ccr, CCR, lch);
209 EXPORT_SYMBOL(omap_set_dma_priority);
211 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
212 int frame_count, int sync_mode,
213 int dma_trigger, int src_or_dst_synch)
217 l = p->dma_read(CSDP, lch);
220 p->dma_write(l, CSDP, lch);
222 if (cpu_class_is_omap1()) {
225 ccr = p->dma_read(CCR, lch);
227 if (sync_mode == OMAP_DMA_SYNC_FRAME)
229 p->dma_write(ccr, CCR, lch);
231 ccr = p->dma_read(CCR2, lch);
233 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
235 p->dma_write(ccr, CCR2, lch);
238 if (cpu_class_is_omap2() && dma_trigger) {
241 val = p->dma_read(CCR, lch);
243 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
244 val &= ~((1 << 23) | (3 << 19) | 0x1f);
245 val |= (dma_trigger & ~0x1f) << 14;
246 val |= dma_trigger & 0x1f;
248 if (sync_mode & OMAP_DMA_SYNC_FRAME)
253 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
258 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
259 val &= ~(1 << 24); /* dest synch */
260 val |= (1 << 23); /* Prefetch */
261 } else if (src_or_dst_synch) {
262 val |= 1 << 24; /* source synch */
264 val &= ~(1 << 24); /* dest synch */
266 p->dma_write(val, CCR, lch);
269 p->dma_write(elem_count, CEN, lch);
270 p->dma_write(frame_count, CFN, lch);
272 EXPORT_SYMBOL(omap_set_dma_transfer_params);
274 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
276 BUG_ON(omap_dma_in_1510_mode());
278 if (cpu_class_is_omap1()) {
281 w = p->dma_read(CCR2, lch);
285 case OMAP_DMA_CONSTANT_FILL:
288 case OMAP_DMA_TRANSPARENT_COPY:
291 case OMAP_DMA_COLOR_DIS:
296 p->dma_write(w, CCR2, lch);
298 w = p->dma_read(LCH_CTRL, lch);
300 /* Default is channel type 2D */
302 p->dma_write(color, COLOR, lch);
303 w |= 1; /* Channel type G */
305 p->dma_write(w, LCH_CTRL, lch);
308 if (cpu_class_is_omap2()) {
311 val = p->dma_read(CCR, lch);
312 val &= ~((1 << 17) | (1 << 16));
315 case OMAP_DMA_CONSTANT_FILL:
318 case OMAP_DMA_TRANSPARENT_COPY:
321 case OMAP_DMA_COLOR_DIS:
326 p->dma_write(val, CCR, lch);
329 p->dma_write(color, COLOR, lch);
332 EXPORT_SYMBOL(omap_set_dma_color_mode);
334 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
336 if (cpu_class_is_omap2()) {
339 csdp = p->dma_read(CSDP, lch);
340 csdp &= ~(0x3 << 16);
341 csdp |= (mode << 16);
342 p->dma_write(csdp, CSDP, lch);
345 EXPORT_SYMBOL(omap_set_dma_write_mode);
347 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
349 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
352 l = p->dma_read(LCH_CTRL, lch);
355 p->dma_write(l, LCH_CTRL, lch);
358 EXPORT_SYMBOL(omap_set_dma_channel_mode);
360 /* Note that src_port is only for omap1 */
361 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
362 unsigned long src_start,
363 int src_ei, int src_fi)
367 if (cpu_class_is_omap1()) {
370 w = p->dma_read(CSDP, lch);
373 p->dma_write(w, CSDP, lch);
376 l = p->dma_read(CCR, lch);
378 l |= src_amode << 12;
379 p->dma_write(l, CCR, lch);
381 p->dma_write(src_start, CSSA, lch);
383 p->dma_write(src_ei, CSEI, lch);
384 p->dma_write(src_fi, CSFI, lch);
386 EXPORT_SYMBOL(omap_set_dma_src_params);
388 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
390 omap_set_dma_transfer_params(lch, params->data_type,
391 params->elem_count, params->frame_count,
392 params->sync_mode, params->trigger,
393 params->src_or_dst_synch);
394 omap_set_dma_src_params(lch, params->src_port,
395 params->src_amode, params->src_start,
396 params->src_ei, params->src_fi);
398 omap_set_dma_dest_params(lch, params->dst_port,
399 params->dst_amode, params->dst_start,
400 params->dst_ei, params->dst_fi);
401 if (params->read_prio || params->write_prio)
402 omap_dma_set_prio_lch(lch, params->read_prio,
405 EXPORT_SYMBOL(omap_set_dma_params);
407 void omap_set_dma_src_index(int lch, int eidx, int fidx)
409 if (cpu_class_is_omap2())
412 p->dma_write(eidx, CSEI, lch);
413 p->dma_write(fidx, CSFI, lch);
415 EXPORT_SYMBOL(omap_set_dma_src_index);
417 void omap_set_dma_src_data_pack(int lch, int enable)
421 l = p->dma_read(CSDP, lch);
425 p->dma_write(l, CSDP, lch);
427 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
429 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
431 unsigned int burst = 0;
434 l = p->dma_read(CSDP, lch);
437 switch (burst_mode) {
438 case OMAP_DMA_DATA_BURST_DIS:
440 case OMAP_DMA_DATA_BURST_4:
441 if (cpu_class_is_omap2())
446 case OMAP_DMA_DATA_BURST_8:
447 if (cpu_class_is_omap2()) {
452 * not supported by current hardware on OMAP1
456 case OMAP_DMA_DATA_BURST_16:
457 if (cpu_class_is_omap2()) {
462 * OMAP1 don't support burst 16
470 p->dma_write(l, CSDP, lch);
472 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
474 /* Note that dest_port is only for OMAP1 */
475 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
476 unsigned long dest_start,
477 int dst_ei, int dst_fi)
481 if (cpu_class_is_omap1()) {
482 l = p->dma_read(CSDP, lch);
485 p->dma_write(l, CSDP, lch);
488 l = p->dma_read(CCR, lch);
490 l |= dest_amode << 14;
491 p->dma_write(l, CCR, lch);
493 p->dma_write(dest_start, CDSA, lch);
495 p->dma_write(dst_ei, CDEI, lch);
496 p->dma_write(dst_fi, CDFI, lch);
498 EXPORT_SYMBOL(omap_set_dma_dest_params);
500 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
502 if (cpu_class_is_omap2())
505 p->dma_write(eidx, CDEI, lch);
506 p->dma_write(fidx, CDFI, lch);
508 EXPORT_SYMBOL(omap_set_dma_dest_index);
510 void omap_set_dma_dest_data_pack(int lch, int enable)
514 l = p->dma_read(CSDP, lch);
518 p->dma_write(l, CSDP, lch);
520 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
522 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
524 unsigned int burst = 0;
527 l = p->dma_read(CSDP, lch);
530 switch (burst_mode) {
531 case OMAP_DMA_DATA_BURST_DIS:
533 case OMAP_DMA_DATA_BURST_4:
534 if (cpu_class_is_omap2())
539 case OMAP_DMA_DATA_BURST_8:
540 if (cpu_class_is_omap2())
545 case OMAP_DMA_DATA_BURST_16:
546 if (cpu_class_is_omap2()) {
551 * OMAP1 don't support burst 16
555 printk(KERN_ERR "Invalid DMA burst mode\n");
560 p->dma_write(l, CSDP, lch);
562 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
564 static inline void omap_enable_channel_irq(int lch)
567 if (cpu_class_is_omap1())
568 p->dma_read(CSR, lch);
570 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
572 /* Enable some nice interrupts. */
573 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
576 static inline void omap_disable_channel_irq(int lch)
578 /* disable channel interrupts */
579 p->dma_write(0, CICR, lch);
581 if (cpu_class_is_omap1())
582 p->dma_read(CSR, lch);
584 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
587 void omap_enable_dma_irq(int lch, u16 bits)
589 dma_chan[lch].enabled_irqs |= bits;
591 EXPORT_SYMBOL(omap_enable_dma_irq);
593 void omap_disable_dma_irq(int lch, u16 bits)
595 dma_chan[lch].enabled_irqs &= ~bits;
597 EXPORT_SYMBOL(omap_disable_dma_irq);
599 static inline void enable_lnk(int lch)
603 l = p->dma_read(CLNK_CTRL, lch);
605 if (cpu_class_is_omap1())
608 /* Set the ENABLE_LNK bits */
609 if (dma_chan[lch].next_lch != -1)
610 l = dma_chan[lch].next_lch | (1 << 15);
612 #ifndef CONFIG_ARCH_OMAP1
613 if (cpu_class_is_omap2())
614 if (dma_chan[lch].next_linked_ch != -1)
615 l = dma_chan[lch].next_linked_ch | (1 << 15);
618 p->dma_write(l, CLNK_CTRL, lch);
621 static inline void disable_lnk(int lch)
625 l = p->dma_read(CLNK_CTRL, lch);
627 /* Disable interrupts */
628 omap_disable_channel_irq(lch);
630 if (cpu_class_is_omap1()) {
631 /* Set the STOP_LNK bit */
635 if (cpu_class_is_omap2()) {
636 /* Clear the ENABLE_LNK bit */
640 p->dma_write(l, CLNK_CTRL, lch);
641 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
644 static inline void omap2_enable_irq_lch(int lch)
649 if (!cpu_class_is_omap2())
652 spin_lock_irqsave(&dma_chan_lock, flags);
653 /* clear IRQ STATUS */
654 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
655 /* Enable interrupt */
656 val = p->dma_read(IRQENABLE_L0, lch);
658 p->dma_write(val, IRQENABLE_L0, lch);
659 spin_unlock_irqrestore(&dma_chan_lock, flags);
662 static inline void omap2_disable_irq_lch(int lch)
667 if (!cpu_class_is_omap2())
670 spin_lock_irqsave(&dma_chan_lock, flags);
671 /* Disable interrupt */
672 val = p->dma_read(IRQENABLE_L0, lch);
674 p->dma_write(val, IRQENABLE_L0, lch);
675 /* clear IRQ STATUS */
676 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
677 spin_unlock_irqrestore(&dma_chan_lock, flags);
680 int omap_request_dma(int dev_id, const char *dev_name,
681 void (*callback)(int lch, u16 ch_status, void *data),
682 void *data, int *dma_ch_out)
684 int ch, free_ch = -1;
686 struct omap_dma_lch *chan;
688 spin_lock_irqsave(&dma_chan_lock, flags);
689 for (ch = 0; ch < dma_chan_count; ch++) {
690 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
697 spin_unlock_irqrestore(&dma_chan_lock, flags);
700 chan = dma_chan + free_ch;
701 chan->dev_id = dev_id;
703 if (p->clear_lch_regs)
704 p->clear_lch_regs(free_ch);
706 if (cpu_class_is_omap2())
707 omap_clear_dma(free_ch);
709 spin_unlock_irqrestore(&dma_chan_lock, flags);
711 chan->dev_name = dev_name;
712 chan->callback = callback;
716 #ifndef CONFIG_ARCH_OMAP1
717 if (cpu_class_is_omap2()) {
719 chan->next_linked_ch = -1;
723 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
725 if (cpu_class_is_omap1())
726 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
727 else if (cpu_class_is_omap2())
728 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
729 OMAP2_DMA_TRANS_ERR_IRQ;
731 if (cpu_is_omap16xx()) {
732 /* If the sync device is set, configure it dynamically. */
734 set_gdma_dev(free_ch + 1, dev_id);
735 dev_id = free_ch + 1;
738 * Disable the 1510 compatibility mode and set the sync device
741 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
742 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
743 p->dma_write(dev_id, CCR, free_ch);
746 if (cpu_class_is_omap2()) {
747 omap_enable_channel_irq(free_ch);
748 omap2_enable_irq_lch(free_ch);
751 *dma_ch_out = free_ch;
755 EXPORT_SYMBOL(omap_request_dma);
757 void omap_free_dma(int lch)
761 if (dma_chan[lch].dev_id == -1) {
762 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
767 /* Disable interrupt for logical channel */
768 if (cpu_class_is_omap2())
769 omap2_disable_irq_lch(lch);
771 /* Disable all DMA interrupts for the channel. */
772 omap_disable_channel_irq(lch);
774 /* Make sure the DMA transfer is stopped. */
775 p->dma_write(0, CCR, lch);
777 /* Clear registers */
778 if (cpu_class_is_omap2())
781 spin_lock_irqsave(&dma_chan_lock, flags);
782 dma_chan[lch].dev_id = -1;
783 dma_chan[lch].next_lch = -1;
784 dma_chan[lch].callback = NULL;
785 spin_unlock_irqrestore(&dma_chan_lock, flags);
787 EXPORT_SYMBOL(omap_free_dma);
790 * @brief omap_dma_set_global_params : Set global priority settings for dma
793 * @param max_fifo_depth
794 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
795 * DMA_THREAD_RESERVE_ONET
796 * DMA_THREAD_RESERVE_TWOT
797 * DMA_THREAD_RESERVE_THREET
800 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
804 if (!cpu_class_is_omap2()) {
805 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
809 if (max_fifo_depth == 0)
814 reg = 0xff & max_fifo_depth;
815 reg |= (0x3 & tparams) << 12;
816 reg |= (arb_rate & 0xff) << 16;
818 p->dma_write(reg, GCR, 0);
820 EXPORT_SYMBOL(omap_dma_set_global_params);
823 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
826 * @param read_prio - Read priority
827 * @param write_prio - Write priority
828 * Both of the above can be set with one of the following values :
829 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
832 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
833 unsigned char write_prio)
837 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
838 printk(KERN_ERR "Invalid channel id\n");
841 l = p->dma_read(CCR, lch);
842 l &= ~((1 << 6) | (1 << 26));
843 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
844 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
846 l |= ((read_prio & 0x1) << 6);
848 p->dma_write(l, CCR, lch);
852 EXPORT_SYMBOL(omap_dma_set_prio_lch);
855 * Clears any DMA state so the DMA engine is ready to restart with new buffers
856 * through omap_start_dma(). Any buffers in flight are discarded.
858 void omap_clear_dma(int lch)
862 local_irq_save(flags);
864 local_irq_restore(flags);
866 EXPORT_SYMBOL(omap_clear_dma);
868 void omap_start_dma(int lch)
873 * The CPC/CDAC register needs to be initialized to zero
874 * before starting dma transfer.
876 if (cpu_is_omap15xx())
877 p->dma_write(0, CPC, lch);
879 p->dma_write(0, CDAC, lch);
881 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
882 int next_lch, cur_lch;
883 char dma_chan_link_map[dma_lch_count];
885 dma_chan_link_map[lch] = 1;
886 /* Set the link register of the first channel */
889 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
890 cur_lch = dma_chan[lch].next_lch;
892 next_lch = dma_chan[cur_lch].next_lch;
894 /* The loop case: we've been here already */
895 if (dma_chan_link_map[cur_lch])
897 /* Mark the current channel */
898 dma_chan_link_map[cur_lch] = 1;
901 omap_enable_channel_irq(cur_lch);
904 } while (next_lch != -1);
905 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
906 p->dma_write(lch, CLNK_CTRL, lch);
908 omap_enable_channel_irq(lch);
910 l = p->dma_read(CCR, lch);
912 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
913 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
914 l |= OMAP_DMA_CCR_EN;
917 * As dma_write() uses IO accessors which are weakly ordered, there
918 * is no guarantee that data in coherent DMA memory will be visible
919 * to the DMA device. Add a memory barrier here to ensure that any
920 * such data is visible prior to enabling DMA.
923 p->dma_write(l, CCR, lch);
925 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
927 EXPORT_SYMBOL(omap_start_dma);
929 void omap_stop_dma(int lch)
933 /* Disable all interrupts on the channel */
934 omap_disable_channel_irq(lch);
936 l = p->dma_read(CCR, lch);
937 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
938 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
942 /* Configure No-Standby */
943 l = p->dma_read(OCP_SYSCONFIG, lch);
945 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
946 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
947 p->dma_write(l , OCP_SYSCONFIG, 0);
949 l = p->dma_read(CCR, lch);
950 l &= ~OMAP_DMA_CCR_EN;
951 p->dma_write(l, CCR, lch);
953 /* Wait for sDMA FIFO drain */
954 l = p->dma_read(CCR, lch);
955 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
956 OMAP_DMA_CCR_WR_ACTIVE))) {
959 l = p->dma_read(CCR, lch);
962 printk(KERN_ERR "DMA drain did not complete on "
964 /* Restore OCP_SYSCONFIG */
965 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
967 l &= ~OMAP_DMA_CCR_EN;
968 p->dma_write(l, CCR, lch);
972 * Ensure that data transferred by DMA is visible to any access
973 * after DMA has been disabled. This is important for coherent
978 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
979 int next_lch, cur_lch = lch;
980 char dma_chan_link_map[dma_lch_count];
982 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
984 /* The loop case: we've been here already */
985 if (dma_chan_link_map[cur_lch])
987 /* Mark the current channel */
988 dma_chan_link_map[cur_lch] = 1;
990 disable_lnk(cur_lch);
992 next_lch = dma_chan[cur_lch].next_lch;
994 } while (next_lch != -1);
997 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
999 EXPORT_SYMBOL(omap_stop_dma);
1002 * Allows changing the DMA callback function or data. This may be needed if
1003 * the driver shares a single DMA channel for multiple dma triggers.
1005 int omap_set_dma_callback(int lch,
1006 void (*callback)(int lch, u16 ch_status, void *data),
1009 unsigned long flags;
1014 spin_lock_irqsave(&dma_chan_lock, flags);
1015 if (dma_chan[lch].dev_id == -1) {
1016 printk(KERN_ERR "DMA callback for not set for free channel\n");
1017 spin_unlock_irqrestore(&dma_chan_lock, flags);
1020 dma_chan[lch].callback = callback;
1021 dma_chan[lch].data = data;
1022 spin_unlock_irqrestore(&dma_chan_lock, flags);
1026 EXPORT_SYMBOL(omap_set_dma_callback);
1029 * Returns current physical source address for the given DMA channel.
1030 * If the channel is running the caller must disable interrupts prior calling
1031 * this function and process the returned value before re-enabling interrupt to
1032 * prevent races with the interrupt handler. Note that in continuous mode there
1033 * is a chance for CSSA_L register overflow between the two reads resulting
1034 * in incorrect return value.
1036 dma_addr_t omap_get_dma_src_pos(int lch)
1038 dma_addr_t offset = 0;
1040 if (cpu_is_omap15xx())
1041 offset = p->dma_read(CPC, lch);
1043 offset = p->dma_read(CSAC, lch);
1045 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1046 offset = p->dma_read(CSAC, lch);
1048 if (!cpu_is_omap15xx()) {
1050 * CDAC == 0 indicates that the DMA transfer on the channel has
1051 * not been started (no data has been transferred so far).
1052 * Return the programmed source start address in this case.
1054 if (likely(p->dma_read(CDAC, lch)))
1055 offset = p->dma_read(CSAC, lch);
1057 offset = p->dma_read(CSSA, lch);
1060 if (cpu_class_is_omap1())
1061 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1065 EXPORT_SYMBOL(omap_get_dma_src_pos);
1068 * Returns current physical destination address for the given DMA channel.
1069 * If the channel is running the caller must disable interrupts prior calling
1070 * this function and process the returned value before re-enabling interrupt to
1071 * prevent races with the interrupt handler. Note that in continuous mode there
1072 * is a chance for CDSA_L register overflow between the two reads resulting
1073 * in incorrect return value.
1075 dma_addr_t omap_get_dma_dst_pos(int lch)
1077 dma_addr_t offset = 0;
1079 if (cpu_is_omap15xx())
1080 offset = p->dma_read(CPC, lch);
1082 offset = p->dma_read(CDAC, lch);
1085 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1086 * read before the DMA controller finished disabling the channel.
1088 if (!cpu_is_omap15xx() && offset == 0) {
1089 offset = p->dma_read(CDAC, lch);
1091 * CDAC == 0 indicates that the DMA transfer on the channel has
1092 * not been started (no data has been transferred so far).
1093 * Return the programmed destination start address in this case.
1095 if (unlikely(!offset))
1096 offset = p->dma_read(CDSA, lch);
1099 if (cpu_class_is_omap1())
1100 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1104 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1106 int omap_get_dma_active_status(int lch)
1108 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1110 EXPORT_SYMBOL(omap_get_dma_active_status);
1112 int omap_dma_running(void)
1116 if (cpu_class_is_omap1())
1117 if (omap_lcd_dma_running())
1120 for (lch = 0; lch < dma_chan_count; lch++)
1121 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1128 * lch_queue DMA will start right after lch_head one is finished.
1129 * For this DMA link to start, you still need to start (see omap_start_dma)
1130 * the first one. That will fire up the entire queue.
1132 void omap_dma_link_lch(int lch_head, int lch_queue)
1134 if (omap_dma_in_1510_mode()) {
1135 if (lch_head == lch_queue) {
1136 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1140 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1145 if ((dma_chan[lch_head].dev_id == -1) ||
1146 (dma_chan[lch_queue].dev_id == -1)) {
1147 printk(KERN_ERR "omap_dma: trying to link "
1148 "non requested channels\n");
1152 dma_chan[lch_head].next_lch = lch_queue;
1154 EXPORT_SYMBOL(omap_dma_link_lch);
1157 * Once the DMA queue is stopped, we can destroy it.
1159 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1161 if (omap_dma_in_1510_mode()) {
1162 if (lch_head == lch_queue) {
1163 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1167 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1172 if (dma_chan[lch_head].next_lch != lch_queue ||
1173 dma_chan[lch_head].next_lch == -1) {
1174 printk(KERN_ERR "omap_dma: trying to unlink "
1175 "non linked channels\n");
1179 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1180 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1181 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1182 "before unlinking\n");
1186 dma_chan[lch_head].next_lch = -1;
1188 EXPORT_SYMBOL(omap_dma_unlink_lch);
1190 #ifndef CONFIG_ARCH_OMAP1
1191 /* Create chain of DMA channesls */
1192 static void create_dma_lch_chain(int lch_head, int lch_queue)
1196 /* Check if this is the first link in chain */
1197 if (dma_chan[lch_head].next_linked_ch == -1) {
1198 dma_chan[lch_head].next_linked_ch = lch_queue;
1199 dma_chan[lch_head].prev_linked_ch = lch_queue;
1200 dma_chan[lch_queue].next_linked_ch = lch_head;
1201 dma_chan[lch_queue].prev_linked_ch = lch_head;
1204 /* a link exists, link the new channel in circular chain */
1206 dma_chan[lch_queue].next_linked_ch =
1207 dma_chan[lch_head].next_linked_ch;
1208 dma_chan[lch_queue].prev_linked_ch = lch_head;
1209 dma_chan[lch_head].next_linked_ch = lch_queue;
1210 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1214 l = p->dma_read(CLNK_CTRL, lch_head);
1217 p->dma_write(l, CLNK_CTRL, lch_head);
1219 l = p->dma_read(CLNK_CTRL, lch_queue);
1221 l |= (dma_chan[lch_queue].next_linked_ch);
1222 p->dma_write(l, CLNK_CTRL, lch_queue);
1226 * @brief omap_request_dma_chain : Request a chain of DMA channels
1228 * @param dev_id - Device id using the dma channel
1229 * @param dev_name - Device name
1230 * @param callback - Call back function
1232 * @no_of_chans - Number of channels requested
1233 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1234 * OMAP_DMA_DYNAMIC_CHAIN
1235 * @params - Channel parameters
1237 * @return - Success : 0
1238 * Failure: -EINVAL/-ENOMEM
1240 int omap_request_dma_chain(int dev_id, const char *dev_name,
1241 void (*callback) (int lch, u16 ch_status,
1243 int *chain_id, int no_of_chans, int chain_mode,
1244 struct omap_dma_channel_params params)
1249 /* Is the chain mode valid ? */
1250 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1251 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1252 printk(KERN_ERR "Invalid chain mode requested\n");
1256 if (unlikely((no_of_chans < 1
1257 || no_of_chans > dma_lch_count))) {
1258 printk(KERN_ERR "Invalid Number of channels requested\n");
1263 * Allocate a queue to maintain the status of the channels
1266 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1267 if (channels == NULL) {
1268 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1272 /* request and reserve DMA channels for the chain */
1273 for (i = 0; i < no_of_chans; i++) {
1274 err = omap_request_dma(dev_id, dev_name,
1275 callback, NULL, &channels[i]);
1278 for (j = 0; j < i; j++)
1279 omap_free_dma(channels[j]);
1281 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1284 dma_chan[channels[i]].prev_linked_ch = -1;
1285 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1288 * Allowing client drivers to set common parameters now,
1289 * so that later only relevant (src_start, dest_start
1290 * and element count) can be set
1292 omap_set_dma_params(channels[i], ¶ms);
1295 *chain_id = channels[0];
1296 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1297 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1298 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1299 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1301 for (i = 0; i < no_of_chans; i++)
1302 dma_chan[channels[i]].chain_id = *chain_id;
1304 /* Reset the Queue pointers */
1305 OMAP_DMA_CHAIN_QINIT(*chain_id);
1307 /* Set up the chain */
1308 if (no_of_chans == 1)
1309 create_dma_lch_chain(channels[0], channels[0]);
1311 for (i = 0; i < (no_of_chans - 1); i++)
1312 create_dma_lch_chain(channels[i], channels[i + 1]);
1317 EXPORT_SYMBOL(omap_request_dma_chain);
1320 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1321 * params after setting it. Dont do this while dma is running!!
1323 * @param chain_id - Chained logical channel id.
1326 * @return - Success : 0
1329 int omap_modify_dma_chain_params(int chain_id,
1330 struct omap_dma_channel_params params)
1335 /* Check for input params */
1336 if (unlikely((chain_id < 0
1337 || chain_id >= dma_lch_count))) {
1338 printk(KERN_ERR "Invalid chain id\n");
1342 /* Check if the chain exists */
1343 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1344 printk(KERN_ERR "Chain doesn't exists\n");
1347 channels = dma_linked_lch[chain_id].linked_dmach_q;
1349 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1351 * Allowing client drivers to set common parameters now,
1352 * so that later only relevant (src_start, dest_start
1353 * and element count) can be set
1355 omap_set_dma_params(channels[i], ¶ms);
1360 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1363 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1367 * @return - Success : 0
1370 int omap_free_dma_chain(int chain_id)
1375 /* Check for input params */
1376 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1377 printk(KERN_ERR "Invalid chain id\n");
1381 /* Check if the chain exists */
1382 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1383 printk(KERN_ERR "Chain doesn't exists\n");
1387 channels = dma_linked_lch[chain_id].linked_dmach_q;
1388 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1389 dma_chan[channels[i]].next_linked_ch = -1;
1390 dma_chan[channels[i]].prev_linked_ch = -1;
1391 dma_chan[channels[i]].chain_id = -1;
1392 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1393 omap_free_dma(channels[i]);
1398 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1399 dma_linked_lch[chain_id].chain_mode = -1;
1400 dma_linked_lch[chain_id].chain_state = -1;
1404 EXPORT_SYMBOL(omap_free_dma_chain);
1407 * @brief omap_dma_chain_status - Check if the chain is in
1408 * active / inactive state.
1411 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1414 int omap_dma_chain_status(int chain_id)
1416 /* Check for input params */
1417 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1418 printk(KERN_ERR "Invalid chain id\n");
1422 /* Check if the chain exists */
1423 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1424 printk(KERN_ERR "Chain doesn't exists\n");
1427 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1428 dma_linked_lch[chain_id].q_count);
1430 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1431 return OMAP_DMA_CHAIN_INACTIVE;
1433 return OMAP_DMA_CHAIN_ACTIVE;
1435 EXPORT_SYMBOL(omap_dma_chain_status);
1438 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1439 * set the params and start the transfer.
1442 * @param src_start - buffer start address
1443 * @param dest_start - Dest address
1445 * @param frame_count
1446 * @param callbk_data - channel callback parameter data.
1448 * @return - Success : 0
1449 * Failure: -EINVAL/-EBUSY
1451 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1452 int elem_count, int frame_count, void *callbk_data)
1459 * if buffer size is less than 1 then there is
1460 * no use of starting the chain
1462 if (elem_count < 1) {
1463 printk(KERN_ERR "Invalid buffer size\n");
1467 /* Check for input params */
1468 if (unlikely((chain_id < 0
1469 || chain_id >= dma_lch_count))) {
1470 printk(KERN_ERR "Invalid chain id\n");
1474 /* Check if the chain exists */
1475 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1476 printk(KERN_ERR "Chain doesn't exist\n");
1480 /* Check if all the channels in chain are in use */
1481 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1484 /* Frame count may be negative in case of indexed transfers */
1485 channels = dma_linked_lch[chain_id].linked_dmach_q;
1487 /* Get a free channel */
1488 lch = channels[dma_linked_lch[chain_id].q_tail];
1490 /* Store the callback data */
1491 dma_chan[lch].data = callbk_data;
1493 /* Increment the q_tail */
1494 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1496 /* Set the params to the free channel */
1498 p->dma_write(src_start, CSSA, lch);
1499 if (dest_start != 0)
1500 p->dma_write(dest_start, CDSA, lch);
1502 /* Write the buffer size */
1503 p->dma_write(elem_count, CEN, lch);
1504 p->dma_write(frame_count, CFN, lch);
1507 * If the chain is dynamically linked,
1508 * then we may have to start the chain if its not active
1510 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1513 * In Dynamic chain, if the chain is not started,
1516 if (dma_linked_lch[chain_id].chain_state ==
1517 DMA_CHAIN_NOTSTARTED) {
1518 /* Enable the link in previous channel */
1519 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1521 enable_lnk(dma_chan[lch].prev_linked_ch);
1522 dma_chan[lch].state = DMA_CH_QUEUED;
1526 * Chain is already started, make sure its active,
1527 * if not then start the chain
1532 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1534 enable_lnk(dma_chan[lch].prev_linked_ch);
1535 dma_chan[lch].state = DMA_CH_QUEUED;
1537 if (0 == ((1 << 7) & p->dma_read(
1538 CCR, dma_chan[lch].prev_linked_ch))) {
1539 disable_lnk(dma_chan[lch].
1541 pr_debug("\n prev ch is stopped\n");
1546 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1548 enable_lnk(dma_chan[lch].prev_linked_ch);
1549 dma_chan[lch].state = DMA_CH_QUEUED;
1552 omap_enable_channel_irq(lch);
1554 l = p->dma_read(CCR, lch);
1556 if ((0 == (l & (1 << 24))))
1560 if (start_dma == 1) {
1561 if (0 == (l & (1 << 7))) {
1563 dma_chan[lch].state = DMA_CH_STARTED;
1564 pr_debug("starting %d\n", lch);
1565 p->dma_write(l, CCR, lch);
1569 if (0 == (l & (1 << 7)))
1570 p->dma_write(l, CCR, lch);
1572 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1578 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1581 * @brief omap_start_dma_chain_transfers - Start the chain
1585 * @return - Success : 0
1586 * Failure : -EINVAL/-EBUSY
1588 int omap_start_dma_chain_transfers(int chain_id)
1593 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1594 printk(KERN_ERR "Invalid chain id\n");
1598 channels = dma_linked_lch[chain_id].linked_dmach_q;
1600 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1601 printk(KERN_ERR "Chain is already started\n");
1605 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1606 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1608 enable_lnk(channels[i]);
1609 omap_enable_channel_irq(channels[i]);
1612 omap_enable_channel_irq(channels[0]);
1615 l = p->dma_read(CCR, channels[0]);
1617 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1618 dma_chan[channels[0]].state = DMA_CH_STARTED;
1620 if ((0 == (l & (1 << 24))))
1624 p->dma_write(l, CCR, channels[0]);
1626 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1630 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1633 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1637 * @return - Success : 0
1640 int omap_stop_dma_chain_transfers(int chain_id)
1646 /* Check for input params */
1647 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1648 printk(KERN_ERR "Invalid chain id\n");
1652 /* Check if the chain exists */
1653 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1654 printk(KERN_ERR "Chain doesn't exists\n");
1657 channels = dma_linked_lch[chain_id].linked_dmach_q;
1659 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1660 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1662 /* Middle mode reg set no Standby */
1663 l &= ~((1 << 12)|(1 << 13));
1664 p->dma_write(l, OCP_SYSCONFIG, 0);
1667 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1669 /* Stop the Channel transmission */
1670 l = p->dma_read(CCR, channels[i]);
1672 p->dma_write(l, CCR, channels[i]);
1674 /* Disable the link in all the channels */
1675 disable_lnk(channels[i]);
1676 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1679 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1681 /* Reset the Queue pointers */
1682 OMAP_DMA_CHAIN_QINIT(chain_id);
1684 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1685 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1689 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1691 /* Get the index of the ongoing DMA in chain */
1693 * @brief omap_get_dma_chain_index - Get the element and frame index
1694 * of the ongoing DMA in chain
1697 * @param ei - Element index
1698 * @param fi - Frame index
1700 * @return - Success : 0
1703 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1708 /* Check for input params */
1709 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1710 printk(KERN_ERR "Invalid chain id\n");
1714 /* Check if the chain exists */
1715 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1716 printk(KERN_ERR "Chain doesn't exists\n");
1722 channels = dma_linked_lch[chain_id].linked_dmach_q;
1724 /* Get the current channel */
1725 lch = channels[dma_linked_lch[chain_id].q_head];
1727 *ei = p->dma_read(CCEN, lch);
1728 *fi = p->dma_read(CCFN, lch);
1732 EXPORT_SYMBOL(omap_get_dma_chain_index);
1735 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1736 * ongoing DMA in chain
1740 * @return - Success : Destination position
1743 int omap_get_dma_chain_dst_pos(int chain_id)
1748 /* Check for input params */
1749 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1750 printk(KERN_ERR "Invalid chain id\n");
1754 /* Check if the chain exists */
1755 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1756 printk(KERN_ERR "Chain doesn't exists\n");
1760 channels = dma_linked_lch[chain_id].linked_dmach_q;
1762 /* Get the current channel */
1763 lch = channels[dma_linked_lch[chain_id].q_head];
1765 return p->dma_read(CDAC, lch);
1767 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1770 * @brief omap_get_dma_chain_src_pos - Get the source position
1771 * of the ongoing DMA in chain
1774 * @return - Success : Destination position
1777 int omap_get_dma_chain_src_pos(int chain_id)
1782 /* Check for input params */
1783 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1784 printk(KERN_ERR "Invalid chain id\n");
1788 /* Check if the chain exists */
1789 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1790 printk(KERN_ERR "Chain doesn't exists\n");
1794 channels = dma_linked_lch[chain_id].linked_dmach_q;
1796 /* Get the current channel */
1797 lch = channels[dma_linked_lch[chain_id].q_head];
1799 return p->dma_read(CSAC, lch);
1801 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1802 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1804 /*----------------------------------------------------------------------------*/
1806 #ifdef CONFIG_ARCH_OMAP1
1808 static int omap1_dma_handle_ch(int ch)
1812 if (enable_1510_mode && ch >= 6) {
1813 csr = dma_chan[ch].saved_csr;
1814 dma_chan[ch].saved_csr = 0;
1816 csr = p->dma_read(CSR, ch);
1817 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1818 dma_chan[ch + 6].saved_csr = csr >> 7;
1821 if ((csr & 0x3f) == 0)
1823 if (unlikely(dma_chan[ch].dev_id == -1)) {
1824 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1825 "%d (CSR %04x)\n", ch, csr);
1828 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1829 printk(KERN_WARNING "DMA timeout with device %d\n",
1830 dma_chan[ch].dev_id);
1831 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1832 printk(KERN_WARNING "DMA synchronization event drop occurred "
1833 "with device %d\n", dma_chan[ch].dev_id);
1834 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1835 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1836 if (likely(dma_chan[ch].callback != NULL))
1837 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1842 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1844 int ch = ((int) dev_id) - 1;
1848 int handled_now = 0;
1850 handled_now += omap1_dma_handle_ch(ch);
1851 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1852 handled_now += omap1_dma_handle_ch(ch + 6);
1855 handled += handled_now;
1858 return handled ? IRQ_HANDLED : IRQ_NONE;
1862 #define omap1_dma_irq_handler NULL
1865 #ifdef CONFIG_ARCH_OMAP2PLUS
1867 static int omap2_dma_handle_ch(int ch)
1869 u32 status = p->dma_read(CSR, ch);
1872 if (printk_ratelimit())
1873 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1875 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1878 if (unlikely(dma_chan[ch].dev_id == -1)) {
1879 if (printk_ratelimit())
1880 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1881 "channel %d\n", status, ch);
1884 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1886 "DMA synchronization event drop occurred with device "
1887 "%d\n", dma_chan[ch].dev_id);
1888 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1889 printk(KERN_INFO "DMA transaction error with device %d\n",
1890 dma_chan[ch].dev_id);
1891 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1894 ccr = p->dma_read(CCR, ch);
1895 ccr &= ~OMAP_DMA_CCR_EN;
1896 p->dma_write(ccr, CCR, ch);
1897 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1900 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1901 printk(KERN_INFO "DMA secure error with device %d\n",
1902 dma_chan[ch].dev_id);
1903 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1904 printk(KERN_INFO "DMA misaligned error with device %d\n",
1905 dma_chan[ch].dev_id);
1907 p->dma_write(status, CSR, ch);
1908 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1909 /* read back the register to flush the write */
1910 p->dma_read(IRQSTATUS_L0, ch);
1912 /* If the ch is not chained then chain_id will be -1 */
1913 if (dma_chan[ch].chain_id != -1) {
1914 int chain_id = dma_chan[ch].chain_id;
1915 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1916 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1917 dma_chan[dma_chan[ch].next_linked_ch].state =
1919 if (dma_linked_lch[chain_id].chain_mode ==
1920 OMAP_DMA_DYNAMIC_CHAIN)
1923 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1924 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1926 status = p->dma_read(CSR, ch);
1927 p->dma_write(status, CSR, ch);
1930 if (likely(dma_chan[ch].callback != NULL))
1931 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1936 /* STATUS register count is from 1-32 while our is 0-31 */
1937 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1939 u32 val, enable_reg;
1942 val = p->dma_read(IRQSTATUS_L0, 0);
1944 if (printk_ratelimit())
1945 printk(KERN_WARNING "Spurious DMA IRQ\n");
1948 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1949 val &= enable_reg; /* Dispatch only relevant interrupts */
1950 for (i = 0; i < dma_lch_count && val != 0; i++) {
1952 omap2_dma_handle_ch(i);
1959 static struct irqaction omap24xx_dma_irq = {
1961 .handler = omap2_dma_irq_handler,
1962 .flags = IRQF_DISABLED
1966 static struct irqaction omap24xx_dma_irq;
1969 /*----------------------------------------------------------------------------*/
1971 void omap_dma_global_context_save(void)
1973 omap_dma_global_context.dma_irqenable_l0 =
1974 p->dma_read(IRQENABLE_L0, 0);
1975 omap_dma_global_context.dma_ocp_sysconfig =
1976 p->dma_read(OCP_SYSCONFIG, 0);
1977 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1980 void omap_dma_global_context_restore(void)
1984 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1985 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1987 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1990 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1991 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1993 for (ch = 0; ch < dma_chan_count; ch++)
1994 if (dma_chan[ch].dev_id != -1)
1998 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2005 p = pdev->dev.platform_data;
2007 dev_err(&pdev->dev, "%s: System DMA initialized without"
2008 "platform data\n", __func__);
2015 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2016 && (omap_dma_reserve_channels <= dma_lch_count))
2017 d->lch_count = omap_dma_reserve_channels;
2019 dma_lch_count = d->lch_count;
2020 dma_chan_count = dma_lch_count;
2022 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2024 if (cpu_class_is_omap2()) {
2025 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2026 dma_lch_count, GFP_KERNEL);
2027 if (!dma_linked_lch) {
2029 goto exit_dma_lch_fail;
2033 spin_lock_init(&dma_chan_lock);
2034 for (ch = 0; ch < dma_chan_count; ch++) {
2036 if (cpu_class_is_omap2())
2037 omap2_disable_irq_lch(ch);
2039 dma_chan[ch].dev_id = -1;
2040 dma_chan[ch].next_lch = -1;
2042 if (ch >= 6 && enable_1510_mode)
2045 if (cpu_class_is_omap1()) {
2047 * request_irq() doesn't like dev_id (ie. ch) being
2048 * zero, so we have to kludge around this.
2050 sprintf(&irq_name[0], "%d", ch);
2051 dma_irq = platform_get_irq_byname(pdev, irq_name);
2055 goto exit_dma_irq_fail;
2058 /* INT_DMA_LCD is handled in lcd_dma.c */
2059 if (dma_irq == INT_DMA_LCD)
2062 ret = request_irq(dma_irq,
2063 omap1_dma_irq_handler, 0, "DMA",
2066 goto exit_dma_irq_fail;
2070 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2071 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2072 DMA_DEFAULT_FIFO_DEPTH, 0);
2074 if (cpu_class_is_omap2()) {
2075 strcpy(irq_name, "0");
2076 dma_irq = platform_get_irq_byname(pdev, irq_name);
2078 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2079 goto exit_dma_lch_fail;
2081 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2083 dev_err(&pdev->dev, "set_up failed for IRQ %d"
2084 "for DMA (error %d)\n", dma_irq, ret);
2085 goto exit_dma_lch_fail;
2089 /* reserve dma channels 0 and 1 in high security devices */
2090 if (cpu_is_omap34xx() &&
2091 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2092 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2094 dma_chan[0].dev_id = 0;
2095 dma_chan[1].dev_id = 1;
2101 dev_err(&pdev->dev, "unable to request IRQ %d"
2102 "for DMA (error %d)\n", dma_irq, ret);
2103 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2104 dma_irq = platform_get_irq(pdev, irq_rel);
2105 free_irq(dma_irq, (void *)(irq_rel + 1));
2115 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2119 if (cpu_class_is_omap2()) {
2121 strcpy(irq_name, "0");
2122 dma_irq = platform_get_irq_byname(pdev, irq_name);
2123 remove_irq(dma_irq, &omap24xx_dma_irq);
2126 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2127 dma_irq = platform_get_irq(pdev, irq_rel);
2128 free_irq(dma_irq, (void *)(irq_rel + 1));
2137 static struct platform_driver omap_system_dma_driver = {
2138 .probe = omap_system_dma_probe,
2139 .remove = omap_system_dma_remove,
2141 .name = "omap_dma_system"
2145 static int __init omap_system_dma_init(void)
2147 return platform_driver_register(&omap_system_dma_driver);
2149 arch_initcall(omap_system_dma_init);
2151 static void __exit omap_system_dma_exit(void)
2153 platform_driver_unregister(&omap_system_dma_driver);
2156 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2157 MODULE_LICENSE("GPL");
2158 MODULE_ALIAS("platform:" DRIVER_NAME);
2159 MODULE_AUTHOR("Texas Instruments Inc");
2162 * Reserve the omap SDMA channels using cmdline bootarg
2163 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2165 static int __init omap_dma_cmdline_reserve_ch(char *str)
2167 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2168 omap_dma_reserve_channels = 0;
2172 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);