arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/sched.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/io.h>
  32
  33 #include <asm/system.h>
  34 #include <mach/hardware.h>
  35 #include <mach/dma.h>
  36
  37 #include <mach/tc.h>
  38
  39 #undef DEBUG
  40
  41 #ifndef CONFIG_ARCH_OMAP1
  42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  43         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  44 };
  45
  46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  47 #endif
  48
  49 #define OMAP_DMA_ACTIVE                 0x01
  50 #define OMAP_DMA_CCR_EN                 (1 << 7)
  51 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  52
  53 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  54
  55 static int enable_1510_mode;
  56
  57 struct omap_dma_lch {
  58         int next_lch;
  59         int dev_id;
  60         u16 saved_csr;
  61         u16 enabled_irqs;
  62         const char *dev_name;
  63         void (*callback)(int lch, u16 ch_status, void *data);
  64         void *data;
  65
  66 #ifndef CONFIG_ARCH_OMAP1
  67         /* required for Dynamic chaining */
  68         int prev_linked_ch;
  69         int next_linked_ch;
  70         int state;
  71         int chain_id;
  72
  73         int status;
  74 #endif
  75         long flags;
  76 };
  77
  78 struct dma_link_info {
  79         int *linked_dmach_q;
  80         int no_of_lchs_linked;
  81
  82         int q_count;
  83         int q_tail;
  84         int q_head;
  85
  86         int chain_state;
  87         int chain_mode;
  88
  89 };
  90
  91 static struct dma_link_info *dma_linked_lch;
  92
  93 #ifndef CONFIG_ARCH_OMAP1
  94
  95 /* Chain handling macros */
  96 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  97         do {                                                            \
  98                 dma_linked_lch[chain_id].q_head =                       \
  99                 dma_linked_lch[chain_id].q_tail =                       \
 100                 dma_linked_lch[chain_id].q_count = 0;                   \
 101         } while (0)
 102 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 103                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 104                 dma_linked_lch[chain_id].q_count)
 105 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 106         do {                                                            \
 107                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 108                 dma_linked_lch[chain_id].q_count)                       \
 109         } while (0)
 110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 111                 (0 == dma_linked_lch[chain_id].q_count)
 112 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 113         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 115         do {                                                            \
 116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 117                 dma_linked_lch[chain_id].q_count--;                     \
 118         } while (0)
 119
 120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 121         do {                                                            \
 122                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 123                 dma_linked_lch[chain_id].q_count++; \
 124         } while (0)
 125 #endif
 126
 127 static int dma_lch_count;
 128 static int dma_chan_count;
 129 static int omap_dma_reserve_channels;
 130
 131 static spinlock_t dma_chan_lock;
 132 static struct omap_dma_lch *dma_chan;
 133 static void __iomem *omap_dma_base;
 134
 135 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 136         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 137         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 138         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 139         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 140         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 141 };
 142
 143 static inline void disable_lnk(int lch);
 144 static void omap_disable_channel_irq(int lch);
 145 static inline void omap_enable_channel_irq(int lch);
 146
 147 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 148                                                 __func__);
 149
 150 #define dma_read(reg)                                                   \
 151 ({                                                                      \
 152         u32 __val;                                                      \
 153         if (cpu_class_is_omap1())                                       \
 154                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 155         else                                                            \
 156                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 157         __val;                                                          \
 158 })
 159
 160 #define dma_write(val, reg)                                             \
 161 ({                                                                      \
 162         if (cpu_class_is_omap1())                                       \
 163                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 164         else                                                            \
 165                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 166 })
 167
 168 #ifdef CONFIG_ARCH_OMAP15XX
 169 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 170 int omap_dma_in_1510_mode(void)
 171 {
 172         return enable_1510_mode;
 173 }
 174 #else
 175 #define omap_dma_in_1510_mode()         0
 176 #endif
 177
 178 #ifdef CONFIG_ARCH_OMAP1
 179 static inline int get_gdma_dev(int req)
 180 {
 181         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 182         int shift = ((req - 1) % 5) * 6;
 183
 184         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 185 }
 186
 187 static inline void set_gdma_dev(int req, int dev)
 188 {
 189         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 190         int shift = ((req - 1) % 5) * 6;
 191         u32 l;
 192
 193         l = omap_readl(reg);
 194         l &= ~(0x3f << shift);
 195         l |= (dev - 1) << shift;
 196         omap_writel(l, reg);
 197 }
 198 #else
 199 #define set_gdma_dev(req, dev)  do {} while (0)
 200 #endif
 201
 202 /* Omap1 only */
 203 static void clear_lch_regs(int lch)
 204 {
 205         int i;
 206         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 207
 208         for (i = 0; i < 0x2c; i += 2)
 209                 __raw_writew(0, lch_base + i);
 210 }
 211
 212 void omap_set_dma_priority(int lch, int dst_port, int priority)
 213 {
 214         unsigned long reg;
 215         u32 l;
 216
 217         if (cpu_class_is_omap1()) {
 218                 switch (dst_port) {
 219                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 220                         reg = OMAP_TC_OCPT1_PRIOR;
 221                         break;
 222                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 223                         reg = OMAP_TC_OCPT2_PRIOR;
 224                         break;
 225                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 226                         reg = OMAP_TC_EMIFF_PRIOR;
 227                         break;
 228                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 229                         reg = OMAP_TC_EMIFS_PRIOR;
 230                         break;
 231                 default:
 232                         BUG();
 233                         return;
 234                 }
 235                 l = omap_readl(reg);
 236                 l &= ~(0xf << 8);
 237                 l |= (priority & 0xf) << 8;
 238                 omap_writel(l, reg);
 239         }
 240
 241         if (cpu_class_is_omap2()) {
 242                 u32 ccr;
 243
 244                 ccr = dma_read(CCR(lch));
 245                 if (priority)
 246                         ccr |= (1 << 6);
 247                 else
 248                         ccr &= ~(1 << 6);
 249                 dma_write(ccr, CCR(lch));
 250         }
 251 }
 252 EXPORT_SYMBOL(omap_set_dma_priority);
 253
 254 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 255                                   int frame_count, int sync_mode,
 256                                   int dma_trigger, int src_or_dst_synch)
 257 {
 258         u32 l;
 259
 260         l = dma_read(CSDP(lch));
 261         l &= ~0x03;
 262         l |= data_type;
 263         dma_write(l, CSDP(lch));
 264
 265         if (cpu_class_is_omap1()) {
 266                 u16 ccr;
 267
 268                 ccr = dma_read(CCR(lch));
 269                 ccr &= ~(1 << 5);
 270                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 271                         ccr |= 1 << 5;
 272                 dma_write(ccr, CCR(lch));
 273
 274                 ccr = dma_read(CCR2(lch));
 275                 ccr &= ~(1 << 2);
 276                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 277                         ccr |= 1 << 2;
 278                 dma_write(ccr, CCR2(lch));
 279         }
 280
 281         if (cpu_class_is_omap2() && dma_trigger) {
 282                 u32 val;
 283
 284                 val = dma_read(CCR(lch));
 285
 286                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 287                 val &= ~((3 << 19) | 0x1f);
 288                 val |= (dma_trigger & ~0x1f) << 14;
 289                 val |= dma_trigger & 0x1f;
 290
 291                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 292                         val |= 1 << 5;
 293                 else
 294                         val &= ~(1 << 5);
 295
 296                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 297                         val |= 1 << 18;
 298                 else
 299                         val &= ~(1 << 18);
 300
 301                 if (src_or_dst_synch)
 302                         val |= 1 << 24;         /* source synch */
 303                 else
 304                         val &= ~(1 << 24);      /* dest synch */
 305
 306                 dma_write(val, CCR(lch));
 307         }
 308
 309         dma_write(elem_count, CEN(lch));
 310         dma_write(frame_count, CFN(lch));
 311 }
 312 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 313
 314 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 315 {
 316         BUG_ON(omap_dma_in_1510_mode());
 317
 318         if (cpu_class_is_omap1()) {
 319                 u16 w;
 320
 321                 w = dma_read(CCR2(lch));
 322                 w &= ~0x03;
 323
 324                 switch (mode) {
 325                 case OMAP_DMA_CONSTANT_FILL:
 326                         w |= 0x01;
 327                         break;
 328                 case OMAP_DMA_TRANSPARENT_COPY:
 329                         w |= 0x02;
 330                         break;
 331                 case OMAP_DMA_COLOR_DIS:
 332                         break;
 333                 default:
 334                         BUG();
 335                 }
 336                 dma_write(w, CCR2(lch));
 337
 338                 w = dma_read(LCH_CTRL(lch));
 339                 w &= ~0x0f;
 340                 /* Default is channel type 2D */
 341                 if (mode) {
 342                         dma_write((u16)color, COLOR_L(lch));
 343                         dma_write((u16)(color >> 16), COLOR_U(lch));
 344                         w |= 1;         /* Channel type G */
 345                 }
 346                 dma_write(w, LCH_CTRL(lch));
 347         }
 348
 349         if (cpu_class_is_omap2()) {
 350                 u32 val;
 351
 352                 val = dma_read(CCR(lch));
 353                 val &= ~((1 << 17) | (1 << 16));
 354
 355                 switch (mode) {
 356                 case OMAP_DMA_CONSTANT_FILL:
 357                         val |= 1 << 16;
 358                         break;
 359                 case OMAP_DMA_TRANSPARENT_COPY:
 360                         val |= 1 << 17;
 361                         break;
 362                 case OMAP_DMA_COLOR_DIS:
 363                         break;
 364                 default:
 365                         BUG();
 366                 }
 367                 dma_write(val, CCR(lch));
 368
 369                 color &= 0xffffff;
 370                 dma_write(color, COLOR(lch));
 371         }
 372 }
 373 EXPORT_SYMBOL(omap_set_dma_color_mode);
 374
 375 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 376 {
 377         if (cpu_class_is_omap2()) {
 378                 u32 csdp;
 379
 380                 csdp = dma_read(CSDP(lch));
 381                 csdp &= ~(0x3 << 16);
 382                 csdp |= (mode << 16);
 383                 dma_write(csdp, CSDP(lch));
 384         }
 385 }
 386 EXPORT_SYMBOL(omap_set_dma_write_mode);
 387
 388 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 389 {
 390         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 391                 u32 l;
 392
 393                 l = dma_read(LCH_CTRL(lch));
 394                 l &= ~0x7;
 395                 l |= mode;
 396                 dma_write(l, LCH_CTRL(lch));
 397         }
 398 }
 399 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 400
 401 /* Note that src_port is only for omap1 */
 402 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 403                              unsigned long src_start,
 404                              int src_ei, int src_fi)
 405 {
 406         u32 l;
 407
 408         if (cpu_class_is_omap1()) {
 409                 u16 w;
 410
 411                 w = dma_read(CSDP(lch));
 412                 w &= ~(0x1f << 2);
 413                 w |= src_port << 2;
 414                 dma_write(w, CSDP(lch));
 415         }
 416
 417         l = dma_read(CCR(lch));
 418         l &= ~(0x03 << 12);
 419         l |= src_amode << 12;
 420         dma_write(l, CCR(lch));
 421
 422         if (cpu_class_is_omap1()) {
 423                 dma_write(src_start >> 16, CSSA_U(lch));
 424                 dma_write((u16)src_start, CSSA_L(lch));
 425         }
 426
 427         if (cpu_class_is_omap2())
 428                 dma_write(src_start, CSSA(lch));
 429
 430         dma_write(src_ei, CSEI(lch));
 431         dma_write(src_fi, CSFI(lch));
 432 }
 433 EXPORT_SYMBOL(omap_set_dma_src_params);
 434
 435 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 436 {
 437         omap_set_dma_transfer_params(lch, params->data_type,
 438                                      params->elem_count, params->frame_count,
 439                                      params->sync_mode, params->trigger,
 440                                      params->src_or_dst_synch);
 441         omap_set_dma_src_params(lch, params->src_port,
 442                                 params->src_amode, params->src_start,
 443                                 params->src_ei, params->src_fi);
 444
 445         omap_set_dma_dest_params(lch, params->dst_port,
 446                                  params->dst_amode, params->dst_start,
 447                                  params->dst_ei, params->dst_fi);
 448         if (params->read_prio || params->write_prio)
 449                 omap_dma_set_prio_lch(lch, params->read_prio,
 450                                       params->write_prio);
 451 }
 452 EXPORT_SYMBOL(omap_set_dma_params);
 453
 454 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 455 {
 456         if (cpu_class_is_omap2())
 457                 return;
 458
 459         dma_write(eidx, CSEI(lch));
 460         dma_write(fidx, CSFI(lch));
 461 }
 462 EXPORT_SYMBOL(omap_set_dma_src_index);
 463
 464 void omap_set_dma_src_data_pack(int lch, int enable)
 465 {
 466         u32 l;
 467
 468         l = dma_read(CSDP(lch));
 469         l &= ~(1 << 6);
 470         if (enable)
 471                 l |= (1 << 6);
 472         dma_write(l, CSDP(lch));
 473 }
 474 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 475
 476 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 477 {
 478         unsigned int burst = 0;
 479         u32 l;
 480
 481         l = dma_read(CSDP(lch));
 482         l &= ~(0x03 << 7);
 483
 484         switch (burst_mode) {
 485         case OMAP_DMA_DATA_BURST_DIS:
 486                 break;
 487         case OMAP_DMA_DATA_BURST_4:
 488                 if (cpu_class_is_omap2())
 489                         burst = 0x1;
 490                 else
 491                         burst = 0x2;
 492                 break;
 493         case OMAP_DMA_DATA_BURST_8:
 494                 if (cpu_class_is_omap2()) {
 495                         burst = 0x2;
 496                         break;
 497                 }
 498                 /* not supported by current hardware on OMAP1
 499                  * w |= (0x03 << 7);
 500                  * fall through
 501                  */
 502         case OMAP_DMA_DATA_BURST_16:
 503                 if (cpu_class_is_omap2()) {
 504                         burst = 0x3;
 505                         break;
 506                 }
 507                 /* OMAP1 don't support burst 16
 508                  * fall through
 509                  */
 510         default:
 511                 BUG();
 512         }
 513
 514         l |= (burst << 7);
 515         dma_write(l, CSDP(lch));
 516 }
 517 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 518
 519 /* Note that dest_port is only for OMAP1 */
 520 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 521                               unsigned long dest_start,
 522                               int dst_ei, int dst_fi)
 523 {
 524         u32 l;
 525
 526         if (cpu_class_is_omap1()) {
 527                 l = dma_read(CSDP(lch));
 528                 l &= ~(0x1f << 9);
 529                 l |= dest_port << 9;
 530                 dma_write(l, CSDP(lch));
 531         }
 532
 533         l = dma_read(CCR(lch));
 534         l &= ~(0x03 << 14);
 535         l |= dest_amode << 14;
 536         dma_write(l, CCR(lch));
 537
 538         if (cpu_class_is_omap1()) {
 539                 dma_write(dest_start >> 16, CDSA_U(lch));
 540                 dma_write(dest_start, CDSA_L(lch));
 541         }
 542
 543         if (cpu_class_is_omap2())
 544                 dma_write(dest_start, CDSA(lch));
 545
 546         dma_write(dst_ei, CDEI(lch));
 547         dma_write(dst_fi, CDFI(lch));
 548 }
 549 EXPORT_SYMBOL(omap_set_dma_dest_params);
 550
 551 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 552 {
 553         if (cpu_class_is_omap2())
 554                 return;
 555
 556         dma_write(eidx, CDEI(lch));
 557         dma_write(fidx, CDFI(lch));
 558 }
 559 EXPORT_SYMBOL(omap_set_dma_dest_index);
 560
 561 void omap_set_dma_dest_data_pack(int lch, int enable)
 562 {
 563         u32 l;
 564
 565         l = dma_read(CSDP(lch));
 566         l &= ~(1 << 13);
 567         if (enable)
 568                 l |= 1 << 13;
 569         dma_write(l, CSDP(lch));
 570 }
 571 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 572
 573 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 574 {
 575         unsigned int burst = 0;
 576         u32 l;
 577
 578         l = dma_read(CSDP(lch));
 579         l &= ~(0x03 << 14);
 580
 581         switch (burst_mode) {
 582         case OMAP_DMA_DATA_BURST_DIS:
 583                 break;
 584         case OMAP_DMA_DATA_BURST_4:
 585                 if (cpu_class_is_omap2())
 586                         burst = 0x1;
 587                 else
 588                         burst = 0x2;
 589                 break;
 590         case OMAP_DMA_DATA_BURST_8:
 591                 if (cpu_class_is_omap2())
 592                         burst = 0x2;
 593                 else
 594                         burst = 0x3;
 595                 break;
 596         case OMAP_DMA_DATA_BURST_16:
 597                 if (cpu_class_is_omap2()) {
 598                         burst = 0x3;
 599                         break;
 600                 }
 601                 /* OMAP1 don't support burst 16
 602                  * fall through
 603                  */
 604         default:
 605                 printk(KERN_ERR "Invalid DMA burst mode\n");
 606                 BUG();
 607                 return;
 608         }
 609         l |= (burst << 14);
 610         dma_write(l, CSDP(lch));
 611 }
 612 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 613
 614 static inline void omap_enable_channel_irq(int lch)
 615 {
 616         u32 status;
 617
 618         /* Clear CSR */
 619         if (cpu_class_is_omap1())
 620                 status = dma_read(CSR(lch));
 621         else if (cpu_class_is_omap2())
 622                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 623
 624         /* Enable some nice interrupts. */
 625         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 626 }
 627
 628 static void omap_disable_channel_irq(int lch)
 629 {
 630         if (cpu_class_is_omap2())
 631                 dma_write(0, CICR(lch));
 632 }
 633
 634 void omap_enable_dma_irq(int lch, u16 bits)
 635 {
 636         dma_chan[lch].enabled_irqs |= bits;
 637 }
 638 EXPORT_SYMBOL(omap_enable_dma_irq);
 639
 640 void omap_disable_dma_irq(int lch, u16 bits)
 641 {
 642         dma_chan[lch].enabled_irqs &= ~bits;
 643 }
 644 EXPORT_SYMBOL(omap_disable_dma_irq);
 645
 646 static inline void enable_lnk(int lch)
 647 {
 648         u32 l;
 649
 650         l = dma_read(CLNK_CTRL(lch));
 651
 652         if (cpu_class_is_omap1())
 653                 l &= ~(1 << 14);
 654
 655         /* Set the ENABLE_LNK bits */
 656         if (dma_chan[lch].next_lch != -1)
 657                 l = dma_chan[lch].next_lch | (1 << 15);
 658
 659 #ifndef CONFIG_ARCH_OMAP1
 660         if (cpu_class_is_omap2())
 661                 if (dma_chan[lch].next_linked_ch != -1)
 662                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 663 #endif
 664
 665         dma_write(l, CLNK_CTRL(lch));
 666 }
 667
 668 static inline void disable_lnk(int lch)
 669 {
 670         u32 l;
 671
 672         l = dma_read(CLNK_CTRL(lch));
 673
 674         /* Disable interrupts */
 675         if (cpu_class_is_omap1()) {
 676                 dma_write(0, CICR(lch));
 677                 /* Set the STOP_LNK bit */
 678                 l |= 1 << 14;
 679         }
 680
 681         if (cpu_class_is_omap2()) {
 682                 omap_disable_channel_irq(lch);
 683                 /* Clear the ENABLE_LNK bit */
 684                 l &= ~(1 << 15);
 685         }
 686
 687         dma_write(l, CLNK_CTRL(lch));
 688         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 689 }
 690
 691 static inline void omap2_enable_irq_lch(int lch)
 692 {
 693         u32 val;
 694         unsigned long flags;
 695
 696         if (!cpu_class_is_omap2())
 697                 return;
 698
 699         spin_lock_irqsave(&dma_chan_lock, flags);
 700         val = dma_read(IRQENABLE_L0);
 701         val |= 1 << lch;
 702         dma_write(val, IRQENABLE_L0);
 703         spin_unlock_irqrestore(&dma_chan_lock, flags);
 704 }
 705
 706 int omap_request_dma(int dev_id, const char *dev_name,
 707                      void (*callback)(int lch, u16 ch_status, void *data),
 708                      void *data, int *dma_ch_out)
 709 {
 710         int ch, free_ch = -1;
 711         unsigned long flags;
 712         struct omap_dma_lch *chan;
 713
 714         spin_lock_irqsave(&dma_chan_lock, flags);
 715         for (ch = 0; ch < dma_chan_count; ch++) {
 716                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 717                         free_ch = ch;
 718                         if (dev_id == 0)
 719                                 break;
 720                 }
 721         }
 722         if (free_ch == -1) {
 723                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 724                 return -EBUSY;
 725         }
 726         chan = dma_chan + free_ch;
 727         chan->dev_id = dev_id;
 728
 729         if (cpu_class_is_omap1())
 730                 clear_lch_regs(free_ch);
 731
 732         if (cpu_class_is_omap2())
 733                 omap_clear_dma(free_ch);
 734
 735         spin_unlock_irqrestore(&dma_chan_lock, flags);
 736
 737         chan->dev_name = dev_name;
 738         chan->callback = callback;
 739         chan->data = data;
 740         chan->flags = 0;
 741
 742 #ifndef CONFIG_ARCH_OMAP1
 743         if (cpu_class_is_omap2()) {
 744                 chan->chain_id = -1;
 745                 chan->next_linked_ch = -1;
 746         }
 747 #endif
 748
 749         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 750
 751         if (cpu_class_is_omap1())
 752                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 753         else if (cpu_class_is_omap2())
 754                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 755                         OMAP2_DMA_TRANS_ERR_IRQ;
 756
 757         if (cpu_is_omap16xx()) {
 758                 /* If the sync device is set, configure it dynamically. */
 759                 if (dev_id != 0) {
 760                         set_gdma_dev(free_ch + 1, dev_id);
 761                         dev_id = free_ch + 1;
 762                 }
 763                 /*
 764                  * Disable the 1510 compatibility mode and set the sync device
 765                  * id.
 766                  */
 767                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 768         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 769                 dma_write(dev_id, CCR(free_ch));
 770         }
 771
 772         if (cpu_class_is_omap2()) {
 773                 omap2_enable_irq_lch(free_ch);
 774                 omap_enable_channel_irq(free_ch);
 775                 /* Clear the CSR register and IRQ status register */
 776                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 777                 dma_write(1 << free_ch, IRQSTATUS_L0);
 778         }
 779
 780         *dma_ch_out = free_ch;
 781
 782         return 0;
 783 }
 784 EXPORT_SYMBOL(omap_request_dma);
 785
 786 void omap_free_dma(int lch)
 787 {
 788         unsigned long flags;
 789
 790         if (dma_chan[lch].dev_id == -1) {
 791                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 792                        lch);
 793                 return;
 794         }
 795
 796         if (cpu_class_is_omap1()) {
 797                 /* Disable all DMA interrupts for the channel. */
 798                 dma_write(0, CICR(lch));
 799                 /* Make sure the DMA transfer is stopped. */
 800                 dma_write(0, CCR(lch));
 801         }
 802
 803         if (cpu_class_is_omap2()) {
 804                 u32 val;
 805
 806                 spin_lock_irqsave(&dma_chan_lock, flags);
 807                 /* Disable interrupts */
 808                 val = dma_read(IRQENABLE_L0);
 809                 val &= ~(1 << lch);
 810                 dma_write(val, IRQENABLE_L0);
 811                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 812
 813                 /* Clear the CSR register and IRQ status register */
 814                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 815                 dma_write(1 << lch, IRQSTATUS_L0);
 816
 817                 /* Disable all DMA interrupts for the channel. */
 818                 dma_write(0, CICR(lch));
 819
 820                 /* Make sure the DMA transfer is stopped. */
 821                 dma_write(0, CCR(lch));
 822                 omap_clear_dma(lch);
 823         }
 824
 825         spin_lock_irqsave(&dma_chan_lock, flags);
 826         dma_chan[lch].dev_id = -1;
 827         dma_chan[lch].next_lch = -1;
 828         dma_chan[lch].callback = NULL;
 829         spin_unlock_irqrestore(&dma_chan_lock, flags);
 830 }
 831 EXPORT_SYMBOL(omap_free_dma);
 832
 833 /**
 834  * @brief omap_dma_set_global_params : Set global priority settings for dma
 835  *
 836  * @param arb_rate
 837  * @param max_fifo_depth
 838  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 839  *                                                 DMA_THREAD_RESERVE_ONET
 840  *                                                 DMA_THREAD_RESERVE_TWOT
 841  *                                                 DMA_THREAD_RESERVE_THREET
 842  */
 843 void
 844 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 845 {
 846         u32 reg;
 847
 848         if (!cpu_class_is_omap2()) {
 849                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 850                 return;
 851         }
 852
 853         if (max_fifo_depth == 0)
 854                 max_fifo_depth = 1;
 855         if (arb_rate == 0)
 856                 arb_rate = 1;
 857
 858         reg = 0xff & max_fifo_depth;
 859         reg |= (0x3 & tparams) << 12;
 860         reg |= (arb_rate & 0xff) << 16;
 861
 862         dma_write(reg, GCR);
 863 }
 864 EXPORT_SYMBOL(omap_dma_set_global_params);
 865
 866 /**
 867  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 868  *
 869  * @param lch
 870  * @param read_prio - Read priority
 871  * @param write_prio - Write priority
 872  * Both of the above can be set with one of the following values :
 873  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 874  */
 875 int
 876 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 877                       unsigned char write_prio)
 878 {
 879         u32 l;
 880
 881         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 882                 printk(KERN_ERR "Invalid channel id\n");
 883                 return -EINVAL;
 884         }
 885         l = dma_read(CCR(lch));
 886         l &= ~((1 << 6) | (1 << 26));
 887         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
 888                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 889         else
 890                 l |= ((read_prio & 0x1) << 6);
 891
 892         dma_write(l, CCR(lch));
 893
 894         return 0;
 895 }
 896 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 897
 898 /*
 899  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 900  * through omap_start_dma(). Any buffers in flight are discarded.
 901  */
 902 void omap_clear_dma(int lch)
 903 {
 904         unsigned long flags;
 905
 906         local_irq_save(flags);
 907
 908         if (cpu_class_is_omap1()) {
 909                 u32 l;
 910
 911                 l = dma_read(CCR(lch));
 912                 l &= ~OMAP_DMA_CCR_EN;
 913                 dma_write(l, CCR(lch));
 914
 915                 /* Clear pending interrupts */
 916                 l = dma_read(CSR(lch));
 917         }
 918
 919         if (cpu_class_is_omap2()) {
 920                 int i;
 921                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 922                 for (i = 0; i < 0x44; i += 4)
 923                         __raw_writel(0, lch_base + i);
 924         }
 925
 926         local_irq_restore(flags);
 927 }
 928 EXPORT_SYMBOL(omap_clear_dma);
 929
 930 void omap_start_dma(int lch)
 931 {
 932         u32 l;
 933
 934         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 935                 int next_lch, cur_lch;
 936                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 937
 938                 dma_chan_link_map[lch] = 1;
 939                 /* Set the link register of the first channel */
 940                 enable_lnk(lch);
 941
 942                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 943                 cur_lch = dma_chan[lch].next_lch;
 944                 do {
 945                         next_lch = dma_chan[cur_lch].next_lch;
 946
 947                         /* The loop case: we've been here already */
 948                         if (dma_chan_link_map[cur_lch])
 949                                 break;
 950                         /* Mark the current channel */
 951                         dma_chan_link_map[cur_lch] = 1;
 952
 953                         enable_lnk(cur_lch);
 954                         omap_enable_channel_irq(cur_lch);
 955
 956                         cur_lch = next_lch;
 957                 } while (next_lch != -1);
 958         } else if (cpu_is_omap242x() ||
 959                 (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
 960
 961                 /* Errata: Need to write lch even if not using chaining */
 962                 dma_write(lch, CLNK_CTRL(lch));
 963         }
 964
 965         omap_enable_channel_irq(lch);
 966
 967         l = dma_read(CCR(lch));
 968
 969         /*
 970          * Errata: On ES2.0 BUFFERING disable must be set.
 971          * This will always fail on ES1.0
 972          */
 973         if (cpu_is_omap24xx())
 974                 l |= OMAP_DMA_CCR_EN;
 975
 976         l |= OMAP_DMA_CCR_EN;
 977         dma_write(l, CCR(lch));
 978
 979         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 980 }
 981 EXPORT_SYMBOL(omap_start_dma);
 982
 983 void omap_stop_dma(int lch)
 984 {
 985         u32 l;
 986
 987         /* Disable all interrupts on the channel */
 988         if (cpu_class_is_omap1())
 989                 dma_write(0, CICR(lch));
 990
 991         l = dma_read(CCR(lch));
 992         l &= ~OMAP_DMA_CCR_EN;
 993         dma_write(l, CCR(lch));
 994
 995         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 996                 int next_lch, cur_lch = lch;
 997                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 998
 999                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
1000                 do {
1001                         /* The loop case: we've been here already */
1002                         if (dma_chan_link_map[cur_lch])
1003                                 break;
1004                         /* Mark the current channel */
1005                         dma_chan_link_map[cur_lch] = 1;
1006
1007                         disable_lnk(cur_lch);
1008
1009                         next_lch = dma_chan[cur_lch].next_lch;
1010                         cur_lch = next_lch;
1011                 } while (next_lch != -1);
1012         }
1013
1014         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1015 }
1016 EXPORT_SYMBOL(omap_stop_dma);
1017
1018 /*
1019  * Allows changing the DMA callback function or data. This may be needed if
1020  * the driver shares a single DMA channel for multiple dma triggers.
1021  */
1022 int omap_set_dma_callback(int lch,
1023                           void (*callback)(int lch, u16 ch_status, void *data),
1024                           void *data)
1025 {
1026         unsigned long flags;
1027
1028         if (lch < 0)
1029                 return -ENODEV;
1030
1031         spin_lock_irqsave(&dma_chan_lock, flags);
1032         if (dma_chan[lch].dev_id == -1) {
1033                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1034                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1035                 return -EINVAL;
1036         }
1037         dma_chan[lch].callback = callback;
1038         dma_chan[lch].data = data;
1039         spin_unlock_irqrestore(&dma_chan_lock, flags);
1040
1041         return 0;
1042 }
1043 EXPORT_SYMBOL(omap_set_dma_callback);
1044
1045 /*
1046  * Returns current physical source address for the given DMA channel.
1047  * If the channel is running the caller must disable interrupts prior calling
1048  * this function and process the returned value before re-enabling interrupt to
1049  * prevent races with the interrupt handler. Note that in continuous mode there
1050  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1051  * in incorrect return value.
1052  */
1053 dma_addr_t omap_get_dma_src_pos(int lch)
1054 {
1055         dma_addr_t offset = 0;
1056
1057         if (cpu_is_omap15xx())
1058                 offset = dma_read(CPC(lch));
1059         else
1060                 offset = dma_read(CSAC(lch));
1061
1062         /*
1063          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1064          * read before the DMA controller finished disabling the channel.
1065          */
1066         if (!cpu_is_omap15xx() && offset == 0)
1067                 offset = dma_read(CSAC(lch));
1068
1069         if (cpu_class_is_omap1())
1070                 offset |= (dma_read(CSSA_U(lch)) << 16);
1071
1072         return offset;
1073 }
1074 EXPORT_SYMBOL(omap_get_dma_src_pos);
1075
1076 /*
1077  * Returns current physical destination address for the given DMA channel.
1078  * If the channel is running the caller must disable interrupts prior calling
1079  * this function and process the returned value before re-enabling interrupt to
1080  * prevent races with the interrupt handler. Note that in continuous mode there
1081  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1082  * in incorrect return value.
1083  */
1084 dma_addr_t omap_get_dma_dst_pos(int lch)
1085 {
1086         dma_addr_t offset = 0;
1087
1088         if (cpu_is_omap15xx())
1089                 offset = dma_read(CPC(lch));
1090         else
1091                 offset = dma_read(CDAC(lch));
1092
1093         /*
1094          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1095          * read before the DMA controller finished disabling the channel.
1096          */
1097         if (!cpu_is_omap15xx() && offset == 0)
1098                 offset = dma_read(CDAC(lch));
1099
1100         if (cpu_class_is_omap1())
1101                 offset |= (dma_read(CDSA_U(lch)) << 16);
1102
1103         return offset;
1104 }
1105 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1106
1107 int omap_get_dma_active_status(int lch)
1108 {
1109         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1110 }
1111 EXPORT_SYMBOL(omap_get_dma_active_status);
1112
1113 int omap_dma_running(void)
1114 {
1115         int lch;
1116
1117         /* Check if LCD DMA is running */
1118         if (cpu_is_omap16xx())
1119                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1120                         return 1;
1121
1122         for (lch = 0; lch < dma_chan_count; lch++)
1123                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1124                         return 1;
1125
1126         return 0;
1127 }
1128
1129 /*
1130  * lch_queue DMA will start right after lch_head one is finished.
1131  * For this DMA link to start, you still need to start (see omap_start_dma)
1132  * the first one. That will fire up the entire queue.
1133  */
1134 void omap_dma_link_lch(int lch_head, int lch_queue)
1135 {
1136         if (omap_dma_in_1510_mode()) {
1137                 if (lch_head == lch_queue) {
1138                         dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1139                                                                 CCR(lch_head));
1140                         return;
1141                 }
1142                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1143                 BUG();
1144                 return;
1145         }
1146
1147         if ((dma_chan[lch_head].dev_id == -1) ||
1148             (dma_chan[lch_queue].dev_id == -1)) {
1149                 printk(KERN_ERR "omap_dma: trying to link "
1150                        "non requested channels\n");
1151                 dump_stack();
1152         }
1153
1154         dma_chan[lch_head].next_lch = lch_queue;
1155 }
1156 EXPORT_SYMBOL(omap_dma_link_lch);
1157
1158 /*
1159  * Once the DMA queue is stopped, we can destroy it.
1160  */
1161 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1162 {
1163         if (omap_dma_in_1510_mode()) {
1164                 if (lch_head == lch_queue) {
1165                         dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1166                                                                 CCR(lch_head));
1167                         return;
1168                 }
1169                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1170                 BUG();
1171                 return;
1172         }
1173
1174         if (dma_chan[lch_head].next_lch != lch_queue ||
1175             dma_chan[lch_head].next_lch == -1) {
1176                 printk(KERN_ERR "omap_dma: trying to unlink "
1177                        "non linked channels\n");
1178                 dump_stack();
1179         }
1180
1181         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1182             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1183                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1184                        "before unlinking\n");
1185                 dump_stack();
1186         }
1187
1188         dma_chan[lch_head].next_lch = -1;
1189 }
1190 EXPORT_SYMBOL(omap_dma_unlink_lch);
1191
1192 /*----------------------------------------------------------------------------*/
1193
1194 #ifndef CONFIG_ARCH_OMAP1
1195 /* Create chain of DMA channesls */
1196 static void create_dma_lch_chain(int lch_head, int lch_queue)
1197 {
1198         u32 l;
1199
1200         /* Check if this is the first link in chain */
1201         if (dma_chan[lch_head].next_linked_ch == -1) {
1202                 dma_chan[lch_head].next_linked_ch = lch_queue;
1203                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1204                 dma_chan[lch_queue].next_linked_ch = lch_head;
1205                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1206         }
1207
1208         /* a link exists, link the new channel in circular chain */
1209         else {
1210                 dma_chan[lch_queue].next_linked_ch =
1211                                         dma_chan[lch_head].next_linked_ch;
1212                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1213                 dma_chan[lch_head].next_linked_ch = lch_queue;
1214                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1215                                         lch_queue;
1216         }
1217
1218         l = dma_read(CLNK_CTRL(lch_head));
1219         l &= ~(0x1f);
1220         l |= lch_queue;
1221         dma_write(l, CLNK_CTRL(lch_head));
1222
1223         l = dma_read(CLNK_CTRL(lch_queue));
1224         l &= ~(0x1f);
1225         l |= (dma_chan[lch_queue].next_linked_ch);
1226         dma_write(l, CLNK_CTRL(lch_queue));
1227 }
1228
1229 /**
1230  * @brief omap_request_dma_chain : Request a chain of DMA channels
1231  *
1232  * @param dev_id - Device id using the dma channel
1233  * @param dev_name - Device name
1234  * @param callback - Call back function
1235  * @chain_id -
1236  * @no_of_chans - Number of channels requested
1237  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1238  *                                            OMAP_DMA_DYNAMIC_CHAIN
1239  * @params - Channel parameters
1240  *
1241  * @return - Succes : 0
1242  *           Failure: -EINVAL/-ENOMEM
1243  */
1244 int omap_request_dma_chain(int dev_id, const char *dev_name,
1245                            void (*callback) (int lch, u16 ch_status,
1246                                              void *data),
1247                            int *chain_id, int no_of_chans, int chain_mode,
1248                            struct omap_dma_channel_params params)
1249 {
1250         int *channels;
1251         int i, err;
1252
1253         /* Is the chain mode valid ? */
1254         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1255                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1256                 printk(KERN_ERR "Invalid chain mode requested\n");
1257                 return -EINVAL;
1258         }
1259
1260         if (unlikely((no_of_chans < 1
1261                         || no_of_chans > dma_lch_count))) {
1262                 printk(KERN_ERR "Invalid Number of channels requested\n");
1263                 return -EINVAL;
1264         }
1265
1266         /* Allocate a queue to maintain the status of the channels
1267          * in the chain */
1268         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1269         if (channels == NULL) {
1270                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1271                 return -ENOMEM;
1272         }
1273
1274         /* request and reserve DMA channels for the chain */
1275         for (i = 0; i < no_of_chans; i++) {
1276                 err = omap_request_dma(dev_id, dev_name,
1277                                         callback, NULL, &channels[i]);
1278                 if (err < 0) {
1279                         int j;
1280                         for (j = 0; j < i; j++)
1281                                 omap_free_dma(channels[j]);
1282                         kfree(channels);
1283                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1284                         return err;
1285                 }
1286                 dma_chan[channels[i]].prev_linked_ch = -1;
1287                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1288
1289                 /*
1290                  * Allowing client drivers to set common parameters now,
1291                  * so that later only relevant (src_start, dest_start
1292                  * and element count) can be set
1293                  */
1294                 omap_set_dma_params(channels[i], &params);
1295         }
1296
1297         *chain_id = channels[0];
1298         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1299         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1300         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1301         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1302
1303         for (i = 0; i < no_of_chans; i++)
1304                 dma_chan[channels[i]].chain_id = *chain_id;
1305
1306         /* Reset the Queue pointers */
1307         OMAP_DMA_CHAIN_QINIT(*chain_id);
1308
1309         /* Set up the chain */
1310         if (no_of_chans == 1)
1311                 create_dma_lch_chain(channels[0], channels[0]);
1312         else {
1313                 for (i = 0; i < (no_of_chans - 1); i++)
1314                         create_dma_lch_chain(channels[i], channels[i + 1]);
1315         }
1316
1317         return 0;
1318 }
1319 EXPORT_SYMBOL(omap_request_dma_chain);
1320
1321 /**
1322  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1323  * params after setting it. Dont do this while dma is running!!
1324  *
1325  * @param chain_id - Chained logical channel id.
1326  * @param params
1327  *
1328  * @return - Success : 0
1329  *           Failure : -EINVAL
1330  */
1331 int omap_modify_dma_chain_params(int chain_id,
1332                                 struct omap_dma_channel_params params)
1333 {
1334         int *channels;
1335         u32 i;
1336
1337         /* Check for input params */
1338         if (unlikely((chain_id < 0
1339                         || chain_id >= dma_lch_count))) {
1340                 printk(KERN_ERR "Invalid chain id\n");
1341                 return -EINVAL;
1342         }
1343
1344         /* Check if the chain exists */
1345         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1346                 printk(KERN_ERR "Chain doesn't exists\n");
1347                 return -EINVAL;
1348         }
1349         channels = dma_linked_lch[chain_id].linked_dmach_q;
1350
1351         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1352                 /*
1353                  * Allowing client drivers to set common parameters now,
1354                  * so that later only relevant (src_start, dest_start
1355                  * and element count) can be set
1356                  */
1357                 omap_set_dma_params(channels[i], &params);
1358         }
1359
1360         return 0;
1361 }
1362 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1363
1364 /**
1365  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1366  *
1367  * @param chain_id
1368  *
1369  * @return - Success : 0
1370  *           Failure : -EINVAL
1371  */
1372 int omap_free_dma_chain(int chain_id)
1373 {
1374         int *channels;
1375         u32 i;
1376
1377         /* Check for input params */
1378         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1379                 printk(KERN_ERR "Invalid chain id\n");
1380                 return -EINVAL;
1381         }
1382
1383         /* Check if the chain exists */
1384         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1385                 printk(KERN_ERR "Chain doesn't exists\n");
1386                 return -EINVAL;
1387         }
1388
1389         channels = dma_linked_lch[chain_id].linked_dmach_q;
1390         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1391                 dma_chan[channels[i]].next_linked_ch = -1;
1392                 dma_chan[channels[i]].prev_linked_ch = -1;
1393                 dma_chan[channels[i]].chain_id = -1;
1394                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1395                 omap_free_dma(channels[i]);
1396         }
1397
1398         kfree(channels);
1399
1400         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1401         dma_linked_lch[chain_id].chain_mode = -1;
1402         dma_linked_lch[chain_id].chain_state = -1;
1403
1404         return (0);
1405 }
1406 EXPORT_SYMBOL(omap_free_dma_chain);
1407
1408 /**
1409  * @brief omap_dma_chain_status - Check if the chain is in
1410  * active / inactive state.
1411  * @param chain_id
1412  *
1413  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1414  *           Failure : -EINVAL
1415  */
1416 int omap_dma_chain_status(int chain_id)
1417 {
1418         /* Check for input params */
1419         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1420                 printk(KERN_ERR "Invalid chain id\n");
1421                 return -EINVAL;
1422         }
1423
1424         /* Check if the chain exists */
1425         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1426                 printk(KERN_ERR "Chain doesn't exists\n");
1427                 return -EINVAL;
1428         }
1429         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1430                         dma_linked_lch[chain_id].q_count);
1431
1432         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1433                 return OMAP_DMA_CHAIN_INACTIVE;
1434
1435         return OMAP_DMA_CHAIN_ACTIVE;
1436 }
1437 EXPORT_SYMBOL(omap_dma_chain_status);
1438
1439 /**
1440  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1441  * set the params and start the transfer.
1442  *
1443  * @param chain_id
1444  * @param src_start - buffer start address
1445  * @param dest_start - Dest address
1446  * @param elem_count
1447  * @param frame_count
1448  * @param callbk_data - channel callback parameter data.
1449  *
1450  * @return  - Success : 0
1451  *            Failure: -EINVAL/-EBUSY
1452  */
1453 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1454                         int elem_count, int frame_count, void *callbk_data)
1455 {
1456         int *channels;
1457         u32 l, lch;
1458         int start_dma = 0;
1459
1460         /*
1461          * if buffer size is less than 1 then there is
1462          * no use of starting the chain
1463          */
1464         if (elem_count < 1) {
1465                 printk(KERN_ERR "Invalid buffer size\n");
1466                 return -EINVAL;
1467         }
1468
1469         /* Check for input params */
1470         if (unlikely((chain_id < 0
1471                         || chain_id >= dma_lch_count))) {
1472                 printk(KERN_ERR "Invalid chain id\n");
1473                 return -EINVAL;
1474         }
1475
1476         /* Check if the chain exists */
1477         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1478                 printk(KERN_ERR "Chain doesn't exist\n");
1479                 return -EINVAL;
1480         }
1481
1482         /* Check if all the channels in chain are in use */
1483         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1484                 return -EBUSY;
1485
1486         /* Frame count may be negative in case of indexed transfers */
1487         channels = dma_linked_lch[chain_id].linked_dmach_q;
1488
1489         /* Get a free channel */
1490         lch = channels[dma_linked_lch[chain_id].q_tail];
1491
1492         /* Store the callback data */
1493         dma_chan[lch].data = callbk_data;
1494
1495         /* Increment the q_tail */
1496         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1497
1498         /* Set the params to the free channel */
1499         if (src_start != 0)
1500                 dma_write(src_start, CSSA(lch));
1501         if (dest_start != 0)
1502                 dma_write(dest_start, CDSA(lch));
1503
1504         /* Write the buffer size */
1505         dma_write(elem_count, CEN(lch));
1506         dma_write(frame_count, CFN(lch));
1507
1508         /*
1509          * If the chain is dynamically linked,
1510          * then we may have to start the chain if its not active
1511          */
1512         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1513
1514                 /*
1515                  * In Dynamic chain, if the chain is not started,
1516                  * queue the channel
1517                  */
1518                 if (dma_linked_lch[chain_id].chain_state ==
1519                                                 DMA_CHAIN_NOTSTARTED) {
1520                         /* Enable the link in previous channel */
1521                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1522                                                                 DMA_CH_QUEUED)
1523                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1524                         dma_chan[lch].state = DMA_CH_QUEUED;
1525                 }
1526
1527                 /*
1528                  * Chain is already started, make sure its active,
1529                  * if not then start the chain
1530                  */
1531                 else {
1532                         start_dma = 1;
1533
1534                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1535                                                         DMA_CH_STARTED) {
1536                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1537                                 dma_chan[lch].state = DMA_CH_QUEUED;
1538                                 start_dma = 0;
1539                                 if (0 == ((1 << 7) & dma_read(
1540                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1541                                         disable_lnk(dma_chan[lch].
1542                                                     prev_linked_ch);
1543                                         pr_debug("\n prev ch is stopped\n");
1544                                         start_dma = 1;
1545                                 }
1546                         }
1547
1548                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1549                                                         == DMA_CH_QUEUED) {
1550                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1551                                 dma_chan[lch].state = DMA_CH_QUEUED;
1552                                 start_dma = 0;
1553                         }
1554                         omap_enable_channel_irq(lch);
1555
1556                         l = dma_read(CCR(lch));
1557
1558                         if ((0 == (l & (1 << 24))))
1559                                 l &= ~(1 << 25);
1560                         else
1561                                 l |= (1 << 25);
1562                         if (start_dma == 1) {
1563                                 if (0 == (l & (1 << 7))) {
1564                                         l |= (1 << 7);
1565                                         dma_chan[lch].state = DMA_CH_STARTED;
1566                                         pr_debug("starting %d\n", lch);
1567                                         dma_write(l, CCR(lch));
1568                                 } else
1569                                         start_dma = 0;
1570                         } else {
1571                                 if (0 == (l & (1 << 7)))
1572                                         dma_write(l, CCR(lch));
1573                         }
1574                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1575                 }
1576         }
1577
1578         return 0;
1579 }
1580 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1581
1582 /**
1583  * @brief omap_start_dma_chain_transfers - Start the chain
1584  *
1585  * @param chain_id
1586  *
1587  * @return - Success : 0
1588  *           Failure : -EINVAL/-EBUSY
1589  */
1590 int omap_start_dma_chain_transfers(int chain_id)
1591 {
1592         int *channels;
1593         u32 l, i;
1594
1595         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1596                 printk(KERN_ERR "Invalid chain id\n");
1597                 return -EINVAL;
1598         }
1599
1600         channels = dma_linked_lch[chain_id].linked_dmach_q;
1601
1602         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1603                 printk(KERN_ERR "Chain is already started\n");
1604                 return -EBUSY;
1605         }
1606
1607         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1608                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1609                                                                         i++) {
1610                         enable_lnk(channels[i]);
1611                         omap_enable_channel_irq(channels[i]);
1612                 }
1613         } else {
1614                 omap_enable_channel_irq(channels[0]);
1615         }
1616
1617         l = dma_read(CCR(channels[0]));
1618         l |= (1 << 7);
1619         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1620         dma_chan[channels[0]].state = DMA_CH_STARTED;
1621
1622         if ((0 == (l & (1 << 24))))
1623                 l &= ~(1 << 25);
1624         else
1625                 l |= (1 << 25);
1626         dma_write(l, CCR(channels[0]));
1627
1628         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1629
1630         return 0;
1631 }
1632 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1633
1634 /**
1635  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1636  *
1637  * @param chain_id
1638  *
1639  * @return - Success : 0
1640  *           Failure : EINVAL
1641  */
1642 int omap_stop_dma_chain_transfers(int chain_id)
1643 {
1644         int *channels;
1645         u32 l, i;
1646         u32 sys_cf;
1647
1648         /* Check for input params */
1649         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1650                 printk(KERN_ERR "Invalid chain id\n");
1651                 return -EINVAL;
1652         }
1653
1654         /* Check if the chain exists */
1655         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1656                 printk(KERN_ERR "Chain doesn't exists\n");
1657                 return -EINVAL;
1658         }
1659         channels = dma_linked_lch[chain_id].linked_dmach_q;
1660
1661         /*
1662          * DMA Errata:
1663          * Special programming model needed to disable DMA before end of block
1664          */
1665         sys_cf = dma_read(OCP_SYSCONFIG);
1666         l = sys_cf;
1667         /* Middle mode reg set no Standby */
1668         l &= ~((1 << 12)|(1 << 13));
1669         dma_write(l, OCP_SYSCONFIG);
1670
1671         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1672
1673                 /* Stop the Channel transmission */
1674                 l = dma_read(CCR(channels[i]));
1675                 l &= ~(1 << 7);
1676                 dma_write(l, CCR(channels[i]));
1677
1678                 /* Disable the link in all the channels */
1679                 disable_lnk(channels[i]);
1680                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1681
1682         }
1683         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1684
1685         /* Reset the Queue pointers */
1686         OMAP_DMA_CHAIN_QINIT(chain_id);
1687
1688         /* Errata - put in the old value */
1689         dma_write(sys_cf, OCP_SYSCONFIG);
1690
1691         return 0;
1692 }
1693 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1694
1695 /* Get the index of the ongoing DMA in chain */
1696 /**
1697  * @brief omap_get_dma_chain_index - Get the element and frame index
1698  * of the ongoing DMA in chain
1699  *
1700  * @param chain_id
1701  * @param ei - Element index
1702  * @param fi - Frame index
1703  *
1704  * @return - Success : 0
1705  *           Failure : -EINVAL
1706  */
1707 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1708 {
1709         int lch;
1710         int *channels;
1711
1712         /* Check for input params */
1713         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1714                 printk(KERN_ERR "Invalid chain id\n");
1715                 return -EINVAL;
1716         }
1717
1718         /* Check if the chain exists */
1719         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1720                 printk(KERN_ERR "Chain doesn't exists\n");
1721                 return -EINVAL;
1722         }
1723         if ((!ei) || (!fi))
1724                 return -EINVAL;
1725
1726         channels = dma_linked_lch[chain_id].linked_dmach_q;
1727
1728         /* Get the current channel */
1729         lch = channels[dma_linked_lch[chain_id].q_head];
1730
1731         *ei = dma_read(CCEN(lch));
1732         *fi = dma_read(CCFN(lch));
1733
1734         return 0;
1735 }
1736 EXPORT_SYMBOL(omap_get_dma_chain_index);
1737
1738 /**
1739  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1740  * ongoing DMA in chain
1741  *
1742  * @param chain_id
1743  *
1744  * @return - Success : Destination position
1745  *           Failure : -EINVAL
1746  */
1747 int omap_get_dma_chain_dst_pos(int chain_id)
1748 {
1749         int lch;
1750         int *channels;
1751
1752         /* Check for input params */
1753         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1754                 printk(KERN_ERR "Invalid chain id\n");
1755                 return -EINVAL;
1756         }
1757
1758         /* Check if the chain exists */
1759         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1760                 printk(KERN_ERR "Chain doesn't exists\n");
1761                 return -EINVAL;
1762         }
1763
1764         channels = dma_linked_lch[chain_id].linked_dmach_q;
1765
1766         /* Get the current channel */
1767         lch = channels[dma_linked_lch[chain_id].q_head];
1768
1769         return dma_read(CDAC(lch));
1770 }
1771 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1772
1773 /**
1774  * @brief omap_get_dma_chain_src_pos - Get the source position
1775  * of the ongoing DMA in chain
1776  * @param chain_id
1777  *
1778  * @return - Success : Destination position
1779  *           Failure : -EINVAL
1780  */
1781 int omap_get_dma_chain_src_pos(int chain_id)
1782 {
1783         int lch;
1784         int *channels;
1785
1786         /* Check for input params */
1787         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1788                 printk(KERN_ERR "Invalid chain id\n");
1789                 return -EINVAL;
1790         }
1791
1792         /* Check if the chain exists */
1793         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1794                 printk(KERN_ERR "Chain doesn't exists\n");
1795                 return -EINVAL;
1796         }
1797
1798         channels = dma_linked_lch[chain_id].linked_dmach_q;
1799
1800         /* Get the current channel */
1801         lch = channels[dma_linked_lch[chain_id].q_head];
1802
1803         return dma_read(CSAC(lch));
1804 }
1805 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1806 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1807
1808 /*----------------------------------------------------------------------------*/
1809
1810 #ifdef CONFIG_ARCH_OMAP1
1811
1812 static int omap1_dma_handle_ch(int ch)
1813 {
1814         u32 csr;
1815
1816         if (enable_1510_mode && ch >= 6) {
1817                 csr = dma_chan[ch].saved_csr;
1818                 dma_chan[ch].saved_csr = 0;
1819         } else
1820                 csr = dma_read(CSR(ch));
1821         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1822                 dma_chan[ch + 6].saved_csr = csr >> 7;
1823                 csr &= 0x7f;
1824         }
1825         if ((csr & 0x3f) == 0)
1826                 return 0;
1827         if (unlikely(dma_chan[ch].dev_id == -1)) {
1828                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1829                        "%d (CSR %04x)\n", ch, csr);
1830                 return 0;
1831         }
1832         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1833                 printk(KERN_WARNING "DMA timeout with device %d\n",
1834                        dma_chan[ch].dev_id);
1835         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1836                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1837                        "with device %d\n", dma_chan[ch].dev_id);
1838         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1839                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1840         if (likely(dma_chan[ch].callback != NULL))
1841                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1842
1843         return 1;
1844 }
1845
1846 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1847 {
1848         int ch = ((int) dev_id) - 1;
1849         int handled = 0;
1850
1851         for (;;) {
1852                 int handled_now = 0;
1853
1854                 handled_now += omap1_dma_handle_ch(ch);
1855                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1856                         handled_now += omap1_dma_handle_ch(ch + 6);
1857                 if (!handled_now)
1858                         break;
1859                 handled += handled_now;
1860         }
1861
1862         return handled ? IRQ_HANDLED : IRQ_NONE;
1863 }
1864
1865 #else
1866 #define omap1_dma_irq_handler   NULL
1867 #endif
1868
1869 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1870                         defined(CONFIG_ARCH_OMAP4)
1871
1872 static int omap2_dma_handle_ch(int ch)
1873 {
1874         u32 status = dma_read(CSR(ch));
1875
1876         if (!status) {
1877                 if (printk_ratelimit())
1878                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1879                                 ch);
1880                 dma_write(1 << ch, IRQSTATUS_L0);
1881                 return 0;
1882         }
1883         if (unlikely(dma_chan[ch].dev_id == -1)) {
1884                 if (printk_ratelimit())
1885                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1886                                         "channel %d\n", status, ch);
1887                 return 0;
1888         }
1889         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1890                 printk(KERN_INFO
1891                        "DMA synchronization event drop occurred with device "
1892                        "%d\n", dma_chan[ch].dev_id);
1893         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1894                 printk(KERN_INFO "DMA transaction error with device %d\n",
1895                        dma_chan[ch].dev_id);
1896                 if (cpu_class_is_omap2()) {
1897                         /* Errata: sDMA Channel is not disabled
1898                          * after a transaction error. So we explicitely
1899                          * disable the channel
1900                          */
1901                         u32 ccr;
1902
1903                         ccr = dma_read(CCR(ch));
1904                         ccr &= ~OMAP_DMA_CCR_EN;
1905                         dma_write(ccr, CCR(ch));
1906                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1907                 }
1908         }
1909         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1910                 printk(KERN_INFO "DMA secure error with device %d\n",
1911                        dma_chan[ch].dev_id);
1912         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1913                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1914                        dma_chan[ch].dev_id);
1915
1916         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1917         dma_write(1 << ch, IRQSTATUS_L0);
1918
1919         /* If the ch is not chained then chain_id will be -1 */
1920         if (dma_chan[ch].chain_id != -1) {
1921                 int chain_id = dma_chan[ch].chain_id;
1922                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1923                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1924                         dma_chan[dma_chan[ch].next_linked_ch].state =
1925                                                         DMA_CH_STARTED;
1926                 if (dma_linked_lch[chain_id].chain_mode ==
1927                                                 OMAP_DMA_DYNAMIC_CHAIN)
1928                         disable_lnk(ch);
1929
1930                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1931                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1932
1933                 status = dma_read(CSR(ch));
1934         }
1935
1936         dma_write(status, CSR(ch));
1937
1938         if (likely(dma_chan[ch].callback != NULL))
1939                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1940
1941         return 0;
1942 }
1943
1944 /* STATUS register count is from 1-32 while our is 0-31 */
1945 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1946 {
1947         u32 val, enable_reg;
1948         int i;
1949
1950         val = dma_read(IRQSTATUS_L0);
1951         if (val == 0) {
1952                 if (printk_ratelimit())
1953                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1954                 return IRQ_HANDLED;
1955         }
1956         enable_reg = dma_read(IRQENABLE_L0);
1957         val &= enable_reg; /* Dispatch only relevant interrupts */
1958         for (i = 0; i < dma_lch_count && val != 0; i++) {
1959                 if (val & 1)
1960                         omap2_dma_handle_ch(i);
1961                 val >>= 1;
1962         }
1963
1964         return IRQ_HANDLED;
1965 }
1966
1967 static struct irqaction omap24xx_dma_irq = {
1968         .name = "DMA",
1969         .handler = omap2_dma_irq_handler,
1970         .flags = IRQF_DISABLED
1971 };
1972
1973 #else
1974 static struct irqaction omap24xx_dma_irq;
1975 #endif
1976
1977 /*----------------------------------------------------------------------------*/
1978
1979 static struct lcd_dma_info {
1980         spinlock_t lock;
1981         int reserved;
1982         void (*callback)(u16 status, void *data);
1983         void *cb_data;
1984
1985         int active;
1986         unsigned long addr, size;
1987         int rotate, data_type, xres, yres;
1988         int vxres;
1989         int mirror;
1990         int xscale, yscale;
1991         int ext_ctrl;
1992         int src_port;
1993         int single_transfer;
1994 } lcd_dma;
1995
1996 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1997                          int data_type)
1998 {
1999         lcd_dma.addr = addr;
2000         lcd_dma.data_type = data_type;
2001         lcd_dma.xres = fb_xres;
2002         lcd_dma.yres = fb_yres;
2003 }
2004 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2005
2006 void omap_set_lcd_dma_src_port(int port)
2007 {
2008         lcd_dma.src_port = port;
2009 }
2010
2011 void omap_set_lcd_dma_ext_controller(int external)
2012 {
2013         lcd_dma.ext_ctrl = external;
2014 }
2015 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2016
2017 void omap_set_lcd_dma_single_transfer(int single)
2018 {
2019         lcd_dma.single_transfer = single;
2020 }
2021 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2022
2023 void omap_set_lcd_dma_b1_rotation(int rotate)
2024 {
2025         if (omap_dma_in_1510_mode()) {
2026                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2027                 BUG();
2028                 return;
2029         }
2030         lcd_dma.rotate = rotate;
2031 }
2032 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2033
2034 void omap_set_lcd_dma_b1_mirror(int mirror)
2035 {
2036         if (omap_dma_in_1510_mode()) {
2037                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2038                 BUG();
2039         }
2040         lcd_dma.mirror = mirror;
2041 }
2042 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2043
2044 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2045 {
2046         if (omap_dma_in_1510_mode()) {
2047                 printk(KERN_ERR "DMA virtual resulotion is not supported "
2048                                 "in 1510 mode\n");
2049                 BUG();
2050         }
2051         lcd_dma.vxres = vxres;
2052 }
2053 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2054
2055 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2056 {
2057         if (omap_dma_in_1510_mode()) {
2058                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2059                 BUG();
2060         }
2061         lcd_dma.xscale = xscale;
2062         lcd_dma.yscale = yscale;
2063 }
2064 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2065
2066 static void set_b1_regs(void)
2067 {
2068         unsigned long top, bottom;
2069         int es;
2070         u16 w;
2071         unsigned long en, fn;
2072         long ei, fi;
2073         unsigned long vxres;
2074         unsigned int xscale, yscale;
2075
2076         switch (lcd_dma.data_type) {
2077         case OMAP_DMA_DATA_TYPE_S8:
2078                 es = 1;
2079                 break;
2080         case OMAP_DMA_DATA_TYPE_S16:
2081                 es = 2;
2082                 break;
2083         case OMAP_DMA_DATA_TYPE_S32:
2084                 es = 4;
2085                 break;
2086         default:
2087                 BUG();
2088                 return;
2089         }
2090
2091         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2092         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2093         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2094         BUG_ON(vxres < lcd_dma.xres);
2095
2096 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2097                 ((y) * vxres * yscale + (x) * xscale) * es)
2098 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2099
2100         switch (lcd_dma.rotate) {
2101         case 0:
2102                 if (!lcd_dma.mirror) {
2103                         top = PIXADDR(0, 0);
2104                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2105                         /* 1510 DMA requires the bottom address to be 2 more
2106                          * than the actual last memory access location. */
2107                         if (omap_dma_in_1510_mode() &&
2108                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2109                                         bottom += 2;
2110                         ei = PIXSTEP(0, 0, 1, 0);
2111                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2112                 } else {
2113                         top = PIXADDR(lcd_dma.xres - 1, 0);
2114                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2115                         ei = PIXSTEP(1, 0, 0, 0);
2116                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2117                 }
2118                 en = lcd_dma.xres;
2119                 fn = lcd_dma.yres;
2120                 break;
2121         case 90:
2122                 if (!lcd_dma.mirror) {
2123                         top = PIXADDR(0, lcd_dma.yres - 1);
2124                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2125                         ei = PIXSTEP(0, 1, 0, 0);
2126                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2127                 } else {
2128                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2129                         bottom = PIXADDR(0, 0);
2130                         ei = PIXSTEP(0, 1, 0, 0);
2131                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2132                 }
2133                 en = lcd_dma.yres;
2134                 fn = lcd_dma.xres;
2135                 break;
2136         case 180:
2137                 if (!lcd_dma.mirror) {
2138                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2139                         bottom = PIXADDR(0, 0);
2140                         ei = PIXSTEP(1, 0, 0, 0);
2141                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2142                 } else {
2143                         top = PIXADDR(0, lcd_dma.yres - 1);
2144                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2145                         ei = PIXSTEP(0, 0, 1, 0);
2146                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2147                 }
2148                 en = lcd_dma.xres;
2149                 fn = lcd_dma.yres;
2150                 break;
2151         case 270:
2152                 if (!lcd_dma.mirror) {
2153                         top = PIXADDR(lcd_dma.xres - 1, 0);
2154                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2155                         ei = PIXSTEP(0, 0, 0, 1);
2156                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2157                 } else {
2158                         top = PIXADDR(0, 0);
2159                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2160                         ei = PIXSTEP(0, 0, 0, 1);
2161                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2162                 }
2163                 en = lcd_dma.yres;
2164                 fn = lcd_dma.xres;
2165                 break;
2166         default:
2167                 BUG();
2168                 return; /* Suppress warning about uninitialized vars */
2169         }
2170
2171         if (omap_dma_in_1510_mode()) {
2172                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2173                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2174                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2175                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2176
2177                 return;
2178         }
2179
2180         /* 1610 regs */
2181         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2182         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2183         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2184         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2185
2186         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2187         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2188
2189         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2190         w &= ~0x03;
2191         w |= lcd_dma.data_type;
2192         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2193
2194         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2195         /* Always set the source port as SDRAM for now*/
2196         w &= ~(0x03 << 6);
2197         if (lcd_dma.callback != NULL)
2198                 w |= 1 << 1;            /* Block interrupt enable */
2199         else
2200                 w &= ~(1 << 1);
2201         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2202
2203         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2204               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2205                 return;
2206
2207         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2208         /* Set the double-indexed addressing mode */
2209         w |= (0x03 << 12);
2210         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2211
2212         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2213         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2214         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2215 }
2216
2217 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2218 {
2219         u16 w;
2220
2221         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2222         if (unlikely(!(w & (1 << 3)))) {
2223                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2224                 return IRQ_NONE;
2225         }
2226         /* Ack the IRQ */
2227         w |= (1 << 3);
2228         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2229         lcd_dma.active = 0;
2230         if (lcd_dma.callback != NULL)
2231                 lcd_dma.callback(w, lcd_dma.cb_data);
2232
2233         return IRQ_HANDLED;
2234 }
2235
2236 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2237                          void *data)
2238 {
2239         spin_lock_irq(&lcd_dma.lock);
2240         if (lcd_dma.reserved) {
2241                 spin_unlock_irq(&lcd_dma.lock);
2242                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2243                 BUG();
2244                 return -EBUSY;
2245         }
2246         lcd_dma.reserved = 1;
2247         spin_unlock_irq(&lcd_dma.lock);
2248         lcd_dma.callback = callback;
2249         lcd_dma.cb_data = data;
2250         lcd_dma.active = 0;
2251         lcd_dma.single_transfer = 0;
2252         lcd_dma.rotate = 0;
2253         lcd_dma.vxres = 0;
2254         lcd_dma.mirror = 0;
2255         lcd_dma.xscale = 0;
2256         lcd_dma.yscale = 0;
2257         lcd_dma.ext_ctrl = 0;
2258         lcd_dma.src_port = 0;
2259
2260         return 0;
2261 }
2262 EXPORT_SYMBOL(omap_request_lcd_dma);
2263
2264 void omap_free_lcd_dma(void)
2265 {
2266         spin_lock(&lcd_dma.lock);
2267         if (!lcd_dma.reserved) {
2268                 spin_unlock(&lcd_dma.lock);
2269                 printk(KERN_ERR "LCD DMA is not reserved\n");
2270                 BUG();
2271                 return;
2272         }
2273         if (!enable_1510_mode)
2274                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2275                             OMAP1610_DMA_LCD_CCR);
2276         lcd_dma.reserved = 0;
2277         spin_unlock(&lcd_dma.lock);
2278 }
2279 EXPORT_SYMBOL(omap_free_lcd_dma);
2280
2281 void omap_enable_lcd_dma(void)
2282 {
2283         u16 w;
2284
2285         /*
2286          * Set the Enable bit only if an external controller is
2287          * connected. Otherwise the OMAP internal controller will
2288          * start the transfer when it gets enabled.
2289          */
2290         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2291                 return;
2292
2293         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2294         w |= 1 << 8;
2295         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2296
2297         lcd_dma.active = 1;
2298
2299         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2300         w |= 1 << 7;
2301         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2302 }
2303 EXPORT_SYMBOL(omap_enable_lcd_dma);
2304
2305 void omap_setup_lcd_dma(void)
2306 {
2307         BUG_ON(lcd_dma.active);
2308         if (!enable_1510_mode) {
2309                 /* Set some reasonable defaults */
2310                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2311                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2312                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2313         }
2314         set_b1_regs();
2315         if (!enable_1510_mode) {
2316                 u16 w;
2317
2318                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2319                 /*
2320                  * If DMA was already active set the end_prog bit to have
2321                  * the programmed register set loaded into the active
2322                  * register set.
2323                  */
2324                 w |= 1 << 11;           /* End_prog */
2325                 if (!lcd_dma.single_transfer)
2326                         w |= (3 << 8);  /* Auto_init, repeat */
2327                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2328         }
2329 }
2330 EXPORT_SYMBOL(omap_setup_lcd_dma);
2331
2332 void omap_stop_lcd_dma(void)
2333 {
2334         u16 w;
2335
2336         lcd_dma.active = 0;
2337         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2338                 return;
2339
2340         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2341         w &= ~(1 << 7);
2342         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2343
2344         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2345         w &= ~(1 << 8);
2346         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2347 }
2348 EXPORT_SYMBOL(omap_stop_lcd_dma);
2349
2350 /*----------------------------------------------------------------------------*/
2351
2352 static int __init omap_init_dma(void)
2353 {
2354         int ch, r;
2355
2356         if (cpu_class_is_omap1()) {
2357                 omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
2358                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2359         } else if (cpu_is_omap24xx()) {
2360                 omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
2361                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2362         } else if (cpu_is_omap34xx()) {
2363                 omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
2364                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2365         } else if (cpu_is_omap44xx()) {
2366                 omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
2367                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2368         } else {
2369                 pr_err("DMA init failed for unsupported omap\n");
2370                 return -ENODEV;
2371         }
2372
2373         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2374                         && (omap_dma_reserve_channels <= dma_lch_count))
2375                 dma_lch_count = omap_dma_reserve_channels;
2376
2377         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2378                                 GFP_KERNEL);
2379         if (!dma_chan)
2380                 return -ENOMEM;
2381
2382         if (cpu_class_is_omap2()) {
2383                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2384                                                 dma_lch_count, GFP_KERNEL);
2385                 if (!dma_linked_lch) {
2386                         kfree(dma_chan);
2387                         return -ENOMEM;
2388                 }
2389         }
2390
2391         if (cpu_is_omap15xx()) {
2392                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2393                 dma_chan_count = 9;
2394                 enable_1510_mode = 1;
2395         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2396                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2397                        dma_read(HW_ID));
2398                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2399                        (dma_read(CAPS_0_U) << 16) |
2400                        dma_read(CAPS_0_L),
2401                        (dma_read(CAPS_1_U) << 16) |
2402                        dma_read(CAPS_1_L),
2403                        dma_read(CAPS_2), dma_read(CAPS_3),
2404                        dma_read(CAPS_4));
2405                 if (!enable_1510_mode) {
2406                         u16 w;
2407
2408                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2409                         w = dma_read(GSCR);
2410                         w |= 1 << 3;
2411                         dma_write(w, GSCR);
2412                         dma_chan_count = 16;
2413                 } else
2414                         dma_chan_count = 9;
2415                 if (cpu_is_omap16xx()) {
2416                         u16 w;
2417
2418                         /* this would prevent OMAP sleep */
2419                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2420                         w &= ~(1 << 8);
2421                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2422                 }
2423         } else if (cpu_class_is_omap2()) {
2424                 u8 revision = dma_read(REVISION) & 0xff;
2425                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2426                        revision >> 4, revision & 0xf);
2427                 dma_chan_count = dma_lch_count;
2428         } else {
2429                 dma_chan_count = 0;
2430                 return 0;
2431         }
2432
2433         spin_lock_init(&lcd_dma.lock);
2434         spin_lock_init(&dma_chan_lock);
2435
2436         for (ch = 0; ch < dma_chan_count; ch++) {
2437                 omap_clear_dma(ch);
2438                 dma_chan[ch].dev_id = -1;
2439                 dma_chan[ch].next_lch = -1;
2440
2441                 if (ch >= 6 && enable_1510_mode)
2442                         continue;
2443
2444                 if (cpu_class_is_omap1()) {
2445                         /*
2446                          * request_irq() doesn't like dev_id (ie. ch) being
2447                          * zero, so we have to kludge around this.
2448                          */
2449                         r = request_irq(omap1_dma_irq[ch],
2450                                         omap1_dma_irq_handler, 0, "DMA",
2451                                         (void *) (ch + 1));
2452                         if (r != 0) {
2453                                 int i;
2454
2455                                 printk(KERN_ERR "unable to request IRQ %d "
2456                                        "for DMA (error %d)\n",
2457                                        omap1_dma_irq[ch], r);
2458                                 for (i = 0; i < ch; i++)
2459                                         free_irq(omap1_dma_irq[i],
2460                                                  (void *) (i + 1));
2461                                 return r;
2462                         }
2463                 }
2464         }
2465
2466         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2467                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2468                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2469
2470         if (cpu_class_is_omap2()) {
2471                 int irq;
2472                 if (cpu_is_omap44xx())
2473                         irq = INT_44XX_SDMA_IRQ0;
2474                 else
2475                         irq = INT_24XX_SDMA_IRQ0;
2476                 setup_irq(irq, &omap24xx_dma_irq);
2477         }
2478
2479         /* Enable smartidle idlemodes and autoidle */
2480         if (cpu_is_omap34xx()) {
2481                 u32 v = dma_read(OCP_SYSCONFIG);
2482                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2483                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
2484                                 DMA_SYSCONFIG_AUTOIDLE);
2485                 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2486                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2487                         DMA_SYSCONFIG_AUTOIDLE);
2488                 dma_write(v , OCP_SYSCONFIG);
2489         }
2490
2491
2492         /* FIXME: Update LCD DMA to work on 24xx */
2493         if (cpu_class_is_omap1()) {
2494                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2495                                 "LCD DMA", NULL);
2496                 if (r != 0) {
2497                         int i;
2498
2499                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2500                                "(error %d)\n", r);
2501                         for (i = 0; i < dma_chan_count; i++)
2502                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2503                         return r;
2504                 }
2505         }
2506
2507         return 0;
2508 }
2509
2510 arch_initcall(omap_init_dma);
2511
2512 /*
2513  * Reserve the omap SDMA channels using cmdline bootarg
2514  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2515  */
2516 static int __init omap_dma_cmdline_reserve_ch(char *str)
2517 {
2518         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2519                 omap_dma_reserve_channels = 0;
2520         return 1;
2521 }
2522
2523 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2524
2525