2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
12 #include <linux/dmaengine.h>
13 #include <linux/workqueue.h>
14 #include <linux/interrupt.h>
15 #include <linux/dmaengine.h>
17 /* dev types for memcpy */
18 #define STEDMA40_DEV_DST_MEMORY (-1)
19 #define STEDMA40_DEV_SRC_MEMORY (-1)
22 * Description of bitfields of channel_type variable is available in
27 #define STEDMA40_INFO_PRIO_TYPE_POS 2
28 #define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS)
29 #define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS)
32 #define STEDMA40_INFO_CH_MODE_TYPE_POS 6
33 #define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS)
34 #define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS)
35 #define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS)
38 #define STEDMA40_INFO_CH_MODE_OPT_POS 8
39 #define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
40 #define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
41 #define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
42 #define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
43 #define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
44 #define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
47 #define STEDMA40_INFO_TIM_POS 10
48 #define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS)
49 #define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS)
51 /* End of channel_type configuration */
53 #define STEDMA40_ESIZE_8_BIT 0x0
54 #define STEDMA40_ESIZE_16_BIT 0x1
55 #define STEDMA40_ESIZE_32_BIT 0x2
56 #define STEDMA40_ESIZE_64_BIT 0x3
58 /* The value 4 indicates that PEN-reg shall be set to 0 */
59 #define STEDMA40_PSIZE_PHY_1 0x4
60 #define STEDMA40_PSIZE_PHY_2 0x0
61 #define STEDMA40_PSIZE_PHY_4 0x1
62 #define STEDMA40_PSIZE_PHY_8 0x2
63 #define STEDMA40_PSIZE_PHY_16 0x3
66 * The number of elements differ in logical and
69 #define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
70 #define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
71 #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
72 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
74 /* Maximum number of possible physical channels */
75 #define STEDMA40_MAX_PHYS 32
77 enum stedma40_flow_ctrl {
78 STEDMA40_NO_FLOW_CTRL,
82 enum stedma40_endianess {
83 STEDMA40_LITTLE_ENDIAN,
87 enum stedma40_periph_data_width {
88 STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
89 STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
90 STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
91 STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
94 struct stedma40_half_channel_info {
95 enum stedma40_endianess endianess;
96 enum stedma40_periph_data_width data_width;
98 enum stedma40_flow_ctrl flow_ctrl;
101 enum stedma40_xfer_dir {
102 STEDMA40_MEM_TO_MEM = 1,
103 STEDMA40_MEM_TO_PERIPH,
104 STEDMA40_PERIPH_TO_MEM,
105 STEDMA40_PERIPH_TO_PERIPH
110 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
112 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
113 * @channel_type: priority, mode, mode options and interrupt configuration.
114 * @src_dev_type: Src device type
115 * @dst_dev_type: Dst device type
116 * @src_info: Parameters for dst half channel
117 * @dst_info: Parameters for dst half channel
118 * @pre_transfer_data: Data to be passed on to the pre_transfer() function.
119 * @pre_transfer: Callback used if needed before preparation of transfer.
120 * Only called if device is set. size of bytes to transfer
121 * (in case of multiple element transfer size is size of the first element).
124 * This structure has to be filled by the client drivers.
125 * It is recommended to do all dma configurations for clients in the machine.
128 struct stedma40_chan_cfg {
129 enum stedma40_xfer_dir dir;
130 unsigned int channel_type;
133 struct stedma40_half_channel_info src_info;
134 struct stedma40_half_channel_info dst_info;
135 void *pre_transfer_data;
136 int (*pre_transfer) (struct dma_chan *chan,
142 * struct stedma40_platform_data - Configuration struct for the dma device.
144 * @dev_len: length of dev_tx and dev_rx
145 * @dev_tx: mapping between destination event line and io address
146 * @dev_rx: mapping between source event line and io address
147 * @memcpy: list of memcpy event lines
148 * @memcpy_len: length of memcpy
149 * @memcpy_conf_phy: default configuration of physical channel memcpy
150 * @memcpy_conf_log: default configuration of logical channel memcpy
151 * @llis_per_log: number of max linked list items per logical channel
152 * @disabled_channels: A vector, ending with -1, that marks physical channels
153 * that are for different reasons not available for the driver.
155 struct stedma40_platform_data {
157 const dma_addr_t *dev_tx;
158 const dma_addr_t *dev_rx;
161 struct stedma40_chan_cfg *memcpy_conf_phy;
162 struct stedma40_chan_cfg *memcpy_conf_log;
163 unsigned int llis_per_log;
164 int disabled_channels[STEDMA40_MAX_PHYS];
168 * setdma40_set_psize() - Used for changing the package size of an
169 * already configured dma channel.
171 * @chan: dmaengine handle
172 * @src_psize: new package side for src. (STEDMA40_PSIZE*)
173 * @src_psize: new package side for dst. (STEDMA40_PSIZE*)
175 * returns 0 on ok, otherwise negative error number.
177 int stedma40_set_psize(struct dma_chan *chan,
182 * stedma40_filter() - Provides stedma40_chan_cfg to the
183 * ste_dma40 dma driver via the dmaengine framework.
184 * does some checking of what's provided.
186 * Never directly called by client. It used by dmaengine.
187 * @chan: dmaengine handle.
188 * @data: Must be of type: struct stedma40_chan_cfg and is
189 * the configuration of the framework.
194 bool stedma40_filter(struct dma_chan *chan, void *data);
197 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
198 * scattergatter lists.
200 * @chan: dmaengine handle
201 * @sgl_dst: Destination scatter list
202 * @sgl_src: Source scatter list
203 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
204 * and each element must match the corresponding element in the other scatter
206 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
209 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
210 struct scatterlist *sgl_dst,
211 struct scatterlist *sgl_src,
212 unsigned int sgl_len,
213 unsigned long flags);
216 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
219 * @chan: dmaengine handle
220 * @addr: source or destination physicall address.
221 * @size: bytes to transfer
222 * @direction: direction of transfer
223 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
227 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
230 enum dma_data_direction direction,
233 struct scatterlist sg;
234 sg_init_table(&sg, 1);
235 sg.dma_address = addr;
238 return chan->device->device_prep_slave_sg(chan, &sg, 1,